PCB wiring structure of differential transmission line and serial data transmission system

Abstract

The invention provides a PCB wiring structure of a differential transmission line and a serial data transmission system, and the wiring structure comprises a first wiring section which is disposed at a pin fan-out via hole position of a BGA array packaging device, and in the first wiring section, at least parts of two signal lines adopt separated wiring so as to maintain at least a first interval between the two signal lines; the first spacing is greater than the diameter of the via hole; the second wiring section is arranged adjacent to the first wiring section, in the second wiring section, at least parts of the two signal lines adopt tight coupling wiring so as to keep a second interval between the two signal lines, and the second interval is smaller than the diameter of the via hole; and the third wiring section is arranged adjacent to the second wiring section, at least parts of the two signal lines in the third wiring section adopt tight coupling wiring so as to keep a third interval between the two signal lines, and the third interval is smaller than the first interval. In the serial data transmission system, the differential transmission line of the wiring structure is adopted for signal connection. On the premise that the cost is not increased, the return loss parameter of the differential transmission line is further optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial data transmission, and more particularly, to a PCB wiring structure for differential transmission lines and a serial data transmission system. Background Art

[0002] High-speed serial data transmission at 20 Gbps to 28 Gbps is widely used in communication technologies. Its physical implementation form on a printed circuit board generally starts from a pad of a BGA array package pin, passes through vias and differential transmission lines, and enters a pad of another BGA array package pin. A differential transmission line uses two transmission lines to transmit two signals. It is required that the edges of the two signals are aligned and the flipping directions are opposite. That is, when wiring the transmission lines, it is required that the two lines are parallel, have the same length and width, are close to each other and symmetrically wired.

[0003] With the rapid development of the communication industry, the requirements for the performance of high-speed serial data transmission are increasing day by day. Generally, the S-parameters of the passive channel of the entire link of line-via-pad are used as a reference for performance indicators. Among the S-parameters, the insertion loss is often determined by the board material and the line length, and the line width plays an auxiliary role; the return loss is determined by details such as wiring and vias. For example, using back drilling to remove the via stubs is a commonly used measure to optimize the return loss. However, back drilling increases the manufacturing steps and manufacturing costs, so it is not widely used.

[0004] Generally speaking, due to the requirement of the line width for the insertion loss, the differential transmission lines will try to maintain a relatively wide line width for wiring. However, within the BGA array package area, due to the dense vias of the pin fan-out, the differential transmission lines often cannot enter the pins in the form of a continuous and uniform line width and spacing that always remain the same. Instead, the line width and line spacing are narrowed to enter the area with dense vias. The above two-segment differential wiring will try to maintain the impedance of the relatively wide transmission line at the target required value, and the impedance of the relatively narrow transmission line is the same as or slightly lower than the continuous value. Also, since the via is basically at the lowest impedance valley in the entire link, the wiring here often determines the amplitude of the impedance mutation of the entire link. To meet the performance requirements, without increasing costs, it is urgent to solve the problem of how to further optimize the return loss parameters of the existing wiring method. Summary of the Invention

[0005] The present invention aims to at least solve one of the above technical problems existing in the prior art.

[0006] To this end, the first aspect of the present invention provides a PCB wiring structure for differential transmission lines.

[0007] The second aspect of the present invention provides a serial data transmission system.

[0008] The present invention provides a PCB wiring structure for differential transmission lines, including:

[0009] The first wiring segment is arranged at the via position where the pins of the BGA array package device are fanned out. In the first wiring segment, at least part of the positive signal line and the negative signal line are separately wired to maintain at least a first spacing between them; the first spacing is greater than the via diameter.

[0010] The second wiring segment is arranged adjacent to the first wiring segment. In the second wiring segment, at least part of the positive signal line and the negative signal line are tightly coupled and wired to maintain a second spacing between them, and the second spacing is less than the via diameter.

[0011] The third wiring segment is arranged adjacent to the second wiring segment. In the second wiring segment, at least part of the positive signal line and the negative signal line are tightly coupled and wired to maintain a third spacing between them, and the third spacing is less than the first spacing.

[0012] The PCB wiring structure of the differential transmission line according to the above technical solution of the present invention may further have the following additional technical features:

[0013] In the above technical solution, the area where the second wiring segment is located is defined as a dense via area. The density of vias in the dense via area is greater than the density of vias in the area where the third wiring segment is located, and is not less than the density of vias in the area where the first wiring segment is located.

[0014] In the above technical solution, the line width of the signal lines in the third wiring segment is greater than the line width of the signal lines in the second wiring segment.

[0015] In the above technical solution, the line width of the signal lines in the first wiring segment is equal to the line width of the signal lines in the second wiring segment.

[0016] In the above technical solution, the length of the first spacing between the positive signal line and the negative signal line in the first wiring segment is A, and A is greater than or equal to pitch and less than or equal to 2 * pitch;

[0017] Wherein, pitch represents the distance between the centers of two adjacent vias.

[0018] In the above technical solution, in the first wiring segment, the line lengths of the positive and negative signal lines of the entire differential transmission line are matched.

[0019] In the above technical solution, in the second wiring segment, the positive signal line and the negative signal line are parallel and symmetrically wired, and the two are close to each other;

[0020] And / or, in the third wiring segment, the positive signal line and the negative signal line are parallel and symmetrically wired, and the two are close to each other.

[0021] In the above technical solution, the data transmission rate of the differential transmission line is 20 Gbps to 28 Gbps.

[0022] The present invention also provides a serial data transmission system, including a first BGA array package pin pad and a second BGA array package pin pad;

[0023] The first BGA array package pin pad and the second BGA array package pin pad are signal-connected through a differential transmission line, wherein the differential data line is arranged on the first BGA array package pin pad and / or the second BGA array package pin pad by using the PCB wiring structure described in any one of claims 1 to 8.

[0024] In the above technical solution, it further includes: a DC-blocking capacitor, and the DC-blocking capacitor is arranged on the transmission path of the differential transmission line for connecting the first BGA array package pin pad and the second BGA array package pin pad;

[0025] In the first wiring segment and the third wiring segment, the line lengths of the positive and negative signal lines of the whole differential transmission line are matched.

[0026] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are as follows:

[0027] Through the differential wiring structure adopted in the first wiring segment, the present invention appropriately widens the distance between the positive and negative signal lines at the pin fan-out, raises the transmission line impedance here, and can also raise the transmission impedance at the via, so that the amplitude of impedance mutation on the entire passive channel is reduced, and the return loss parameter can be optimized by 3dB to 4dB.

[0028] At the same time, segmented wiring is adopted within a limited area, which occupies less space; the manufacturing cost and steps of the overall wiring structure do not increase. It has extremely strong application value in the field of high-speed digital transmission technology.

[0029] The additional aspects and advantages of the present invention will become obvious in the following description part, or will be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein:

[0031] Figure 1 is an overall view of the PCB wiring structure of a traditional differential transmission line (without an AC coupling capacitor);

[0032] Figure 2 is Figure 1 a schematic structural diagram of the PCB wiring structure of the traditional differential transmission line shown in the BGA array package area;

[0033] Figure 3Is an overall view of the PCB wiring structure of a traditional differential transmission line (with AC coupling capacitors);

[0034] Figure 4 Is Figure 3 An enlarged view of the PCB wiring structure of the traditional differential transmission line shown within the BGA array package area (with AC coupling capacitors);

[0035] Figure 5 Is a schematic diagram of the simulation result of the SDD11 return loss graph of the PCB wiring structure of a traditional differential transmission line (without AC coupling capacitors);

[0036] Figure 6 Is a schematic diagram of the simulation result of the SDD11 return loss graph of the PCB wiring structure of a traditional differential transmission line (with AC coupling capacitors);

[0037] Figure 7 Is a schematic structural diagram of the PCB wiring structure of the differential transmission line according to an embodiment of the present invention;

[0038] Figure 8 Is a schematic structural diagram of a serial data transmission system according to an embodiment of the present invention (with AC coupling capacitors);

[0039] Figure 9 Is a schematic diagram of the simulation result of the SDD11 return loss graph of the PCB wiring structure of the differential transmission line according to an embodiment of the present invention (without AC coupling capacitors);

[0040] Figure 10 Is a schematic diagram of the simulation result of the SDD11 return loss graph of the PCB wiring structure of the differential transmission line according to an embodiment of the present invention (with AC coupling capacitors and using the wiring structure of the present invention at both ends of the link);

[0041] Figure 11 Is a schematic diagram of the simulation result of the SDD11 return loss graph of the PCB wiring structure of the differential transmission line according to an embodiment of the present invention (with AC coupling capacitors and using the wiring structure of the present invention at only one end of the link).

[0042] Among them, Figures 1 to 11 The corresponding relationship between the reference numerals and the component names in

[0043] 1. First wiring segment; 2. Second wiring segment; 3. Third wiring segment;

[0044] 4. Via; 5. First BGA array package pin pad; 6. Second BGA array package pin pad. Detailed implementation manners

[0045] To better understand the above objects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0046] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0047] The following refers to Figures 1 to 11 to describe the PCB wiring structure of differential transmission lines and the serial data transmission system according to some embodiments of the present invention. The embodiments of the present disclosure are described by taking the high-speed serial data transmission of 20 Gbps to 28 Gbps as an example. Specifically, a certain high-speed digital board has 26 layers, and the 24th layer and the 22nd layer are high-speed wiring layers. The 28 Gbps rate link is FPGA - wiring - capacitor - wiring - FPGA; the 20 Gbps rate link is FPGA - wiring - optical module.

[0048] It should be noted that the PCB wiring structure of the differential transmission line proposed in the present disclosure is not only applicable to the transmission rate of 20 Gbps to 28 Gbps and the above-mentioned transmission link, but those skilled in the art can also make the wiring structure of the present invention adapt to other transmission rates or other application scenarios with reference to the content of the present invention.

[0049] Figures 1 to 4 The traditional two-segment wiring structure of differential transmission lines (without AC coupling capacitor and with AC coupling capacitor) is shown. Due to the excessive number of signal lines, the fan-out vias of array packaged devices (such as FPGA or optical module, etc.) are dense, and the spacing between vias is limited. To lay a pair of tightly coupled differentials with a specific impedance value, it is necessary to narrow the line width and the spacing of the differential transmission line as much as possible, that is, the first wiring segment; after the differential transmission line leaves the dense via area, to optimize the insertion loss parameter of the wiring channel as much as possible, the differential transmission line will widen the line width while meeting the impedance value consistent with the first segment of wiring, and match the appropriate line spacing according to the impedance value, that is, the second wiring segment. At this time, the return loss parameters of 10 GHz to 14 GHz (corresponding to the line rate of 20 Gbps to 28 Gbps) are about in the range of -13.1 dB to -6.5 dB (link without capacitor), -7.5 dB to -5.2 dB (link with capacitor).

[0050] Based on the above wiring structure, the simulation results of the SDD11 return loss pattern are as Figure 5 and Figure 6 shown. Among them, Figure 5 the schematic simulation waveform is the Sdd11 return loss pattern of the link without AC coupling capacitor;Figure 6 The schematic simulation waveform is the Sdd11 return loss graph of the link with an AC coupling capacitor.

[0051] To optimize the return loss parameters of the above PCB wiring structure, some embodiments of the present application provide a PCB wiring structure for differential transmission lines.

[0052] As Figure 7 shown, the first embodiment of the present invention proposes a PCB wiring structure for differential transmission lines, including a first wiring segment 1, a second wiring segment 2, and a third wiring segment 3. The differential transmission line includes a positive signal line and a negative signal line. It can be understood that the above first wiring segment 1, second wiring segment 2, and third wiring segment 3 are all partial paragraphs of the transmission path of the differential transmission line.

[0053] The first wiring segment 1 is arranged at the position of the via 4 in the pin fan-out of the BGA array package device. In the first wiring segment 1, the positive signal line and the negative signal line are at least partially separated for wiring to maintain at least a first spacing between them; the first spacing is greater than the diameter of the via 4.

[0054] The second wiring segment 2 is arranged adjacent to the first wiring segment 1. In the second wiring segment 2, the positive signal line and the negative signal line are at least partially tightly coupled for wiring to maintain a second spacing between them, and the second spacing is less than the diameter of the via 4.

[0055] The third wiring segment 3 is arranged adjacent to the second wiring segment 2. In the third wiring segment 3, the positive signal line and the negative signal line are at least partially tightly coupled for wiring to maintain a third spacing between them, and the third spacing is less than the first spacing.

[0056] Specifically, the area where the second wiring segment 2 is located is defined as a dense via area. The density of the vias 4 in the dense via area is greater than the density of the vias 4 in the area where the third wiring segment 3 is located, and is not less than the density of the vias 4 in the area where the first wiring segment 1 is located.

[0057] That is to say, in the first wiring segment 1, by appropriately increasing the spacing between the positive and negative signal lines at the pin fan-out, the transmission line impedance here can be increased, which can also increase the transmission impedance at the via 4, reducing the amplitude of the impedance mutation on the entire passive channel. When the traveling path of the differential transmission line passes through an area with a relatively dense distribution of vias 4, the two signal lines of the differential transmission line adopt the wiring method of the second wiring segment 2, that is, a smaller spacing for tight coupling wiring; when the traveling path of the differential transmission line leaves the area with dense vias in the array package device, the third wiring segment 3 is used for wiring. Further, the line width of the signal lines in the third wiring segment 3 is greater than the line width of the signal lines in the second wiring segment 2. It can be understood that in the third wiring segment 3, the wiring method can be generally summarized as tight coupling wiring with a wider line width.

[0058] In some embodiments, the line width of the signal lines in the first wiring segment 1 is equal to the line width of the signal lines in the second wiring segment 2. When the signal lines with a lower line width are used in the first wiring segment 1 and the second wiring segment 2, it is easier to deploy the signal lines on the via-dense area.

[0059] In some embodiments, the length of the first spacing between the positive signal line and the negative signal line in the first wiring segment 1 is A, where A is greater than or equal to pitch and less than or equal to 2 * pitch; wherein, pitch represents the distance between the centers of two adjacent vias 4.

[0060] In some embodiments, within the first wiring segment 1, the line lengths of the positive and negative signal lines of the differential transmission line as a whole are matched. Since the two signal lines in the first wiring segment 1 are already separated by vias 4, there is no need to consider the problem of positive-negative symmetric wiring. Therefore, the line lengths of the positive and negative signal lines of the differential transmission line as a whole can be directly matched in this segment, that is, the lengths of the positive signal line and the negative signal line are kept the same. The situation where the lengths of the two signal lines are uneven due to other paragraphs or bends can be adjusted in the first wiring segment 1 to ensure that the positive and negative signal components are propagated synchronously through the connection.

[0061] When no AC coupling capacitors are arranged on the transmission path, in the second wiring segment 2 and the third wiring segment 3, the positive signal line and the negative signal line are parallel and symmetrically wired, and they are close to each other. Parallel wiring means that the positive and negative signal lines in the differential pair are wired along the same direction with a constant spacing, so that the two lines are as consistent as possible in length and routing path. Being close to each other means that the distance between the positive and negative signal lines should be as small as possible. Usually, within the range allowed by the design rules, a small spacing is maintained. Symmetric wiring means that during the wiring process, it is ensured that the positive and negative signal lines are symmetric in geometric shape and routing path, including the bending of the lines, vias 4, etc., which should all be kept symmetric.

[0062] Some other embodiments of the present invention provide a serial data transmission system, as Figure 8 shown, including a first BGA array package pin pad 5 and a second BGA array package pin pad 6;

[0063] The first BGA array package pin pad 5 and the second BGA array package pin pad 6 are signal-connected through a differential transmission line. Among them, the differential data line is arranged on the first BGA array package pin pad 5 and / or the second BGA array package pin pad 6 by using the PCB wiring structure described in any one of the above embodiments.

[0064] It is understandable that when the PCB wiring structure proposed in the present disclosure is applied, it can be equipped only at one end of the transmission link, or it can be equipped at both ends at the same time, that is, wiring is performed only on the first BGA array package pin pad 5 or the second BGA array package pin pad 6 according to the PCB wiring structure proposed in the present disclosure, or wiring is performed on the first BGA array package pin pad 5 and the second BGA array package pin pad 6 according to the PCB wiring structure proposed in the present disclosure. Both can achieve the effect of optimizing the return loss parameter.

[0065] In some embodiments, the serial data transmission system further includes a DC blocking capacitor, which is arranged on a transmission path of a differential transmission line for connecting the first BGA array package pin pad 5 and the second BGA array package pin pad 6 .

[0066] At this time, if the line length matching capability in the first wiring segment 1 is insufficient, the line length matching of the positive and negative signal lines of the differential transmission line as a whole can be performed in both the first wiring segment 1 and the third wiring segment 3 .

[0067] In a specific embodiment, in the high-speed digital board with 26 layers, by adding the differential separation wiring of the first wiring segment 1, the transmission impedance at the via 4 can be raised, so that the impedance mutation amplitude on the entire passive channel is reduced, and the return loss parameter can be optimized.

[0068] Based on the wiring structure proposed by the present invention, the simulation results of the SDD11 return loss graph are as follows: Figures 9 to 11 As shown. Among them, Figure 9 The simulated waveform shown is the Sdd11 return loss graph of the link without AC coupling capacitor; Figure 10 and Figure 11 The illustrated simulation waveform is an Sdd11 return loss graph with an AC coupling capacitor in the link.

[0069] like Figure 9 As shown in Figure 1, the return loss parameter of 10GHz to 14GHz (corresponding to line rates of 20Gbps to 28Gbps) is approximately in the range of -15.1dB to -9.7dB (link has no capacitance). Figure 10 As shown in the figure, the return loss parameter of 10GHz to 14GHz (corresponding to line rate 20Gbps to 28Gbps) is approximately in the range of -11dB to -8dB (the link has capacitance). Figure 10 The diagram shows the return loss parameters of the wiring structure of the present invention used at both ends of the signal link, and the return loss parameters are in the range of -11dB to -9.8dB; Figure 11 The schematic diagram shows the return loss parameter of the wiring structure of the present invention only at one end of the signal link, and the return loss parameter is in the range of -10.1dB to -8dB. Compared with the traditional method, the return loss is improved by about 3dB to 4dB.

[0070] In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0071] Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A PCB wiring structure of a differential transmission line, characterized in that: include: A first wiring segment is arranged at a fan-out via position of a pin of a BGA array package device, wherein at least a portion of the positive signal line and the negative signal line are separately wired in the first wiring segment to maintain at least a first spacing between the positive signal line and the negative signal line; The first spacing is greater than the via diameter; A second wiring segment is arranged adjacent to the first wiring segment, and in the second wiring segment, the positive signal line and the negative signal line are at least partially tightly coupled to maintain a second spacing between the two, and the second spacing is smaller than the via diameter; The third wiring segment is arranged adjacent to the second wiring segment. In the third wiring segment, the positive signal line and the negative signal line are at least partially tightly coupled to maintain a third spacing between the two, which is smaller than the first spacing.

2. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: The area where the second wiring segment is located is defined as a dense via area, and the density of vias in the dense via area is greater than the density of vias in the area where the third wiring segment is located, and is not less than the density of vias in the area where the first wiring segment is located.

3. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: The line width of the signal line in the third wiring segment is greater than the line width of the signal line in the second wiring segment.

4. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: The line width of the signal line in the first wiring segment is equal to the line width of the signal line in the second wiring segment.

5. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: The length of the first spacing between the positive signal line and the negative signal line in the first wiring segment is A, where A is greater than or equal to pitch and less than or equal to 2*pitch; Among them, pitch represents the distance between the centers of two adjacent vias.

6. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: In the first wiring segment, line length matching of the positive and negative signal lines of the differential transmission line as a whole is performed.

7. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: In the second wiring segment, the positive signal line and the negative signal line are arranged in parallel and symmetrically, and the two are close to each other; And / or, in the third wiring segment, the positive signal line and the negative signal line are wired in parallel and symmetrically, and are close to each other.

8. The PCB wiring structure of the differential transmission line according to claim 1, characterized in that: The data transmission rate of the differential transmission line is 20 Gbps to 28 Gbps.

9. A serial data transmission system, characterized in that: It includes a first BGA array package pin pad and a second BGA array package pin pad; The first BGA array package pin pad and the second BGA array package pin pad are signal-connected via a differential transmission line, wherein the differential data line is arranged on the first BGA array package pin pad and / or the second BGA array package pin pad using a PCB wiring structure as described in any one of claims 1 to 8.

10. The serial data transmission system according to claim 9, characterized in that: Also includes: A DC blocking capacitor, wherein the DC blocking capacitor is arranged on a transmission path of a differential transmission line for connecting a first BGA array package pin pad and a second BGA array package pin pad; In the first wiring segment and the third wiring segment, line length matching of the positive and negative signal lines of the differential transmission line as a whole is performed.

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