Electronic device

Abstract

The invention provides an electronic device which is provided with a peripheral area. The electronic device comprises a first substrate, a second substrate, a first supporting piece, a flat layer and an alignment layer. The second substrate and the first substrate are oppositely arranged. The first supporting piece is arranged in the peripheral area and is arranged between the first substrate and the second substrate. The flat layer is arranged on the first substrate and is provided with a first part and an opening. The first portion is disposed in the opening, and the first support and the first portion overlap in a normal direction of the first substrate. The alignment layer is arranged on the flat layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.

Description

[0001] This invention is a divisional application of the patent application for invention titled "Electronic Device" with the application number 201911013323.3 filed on October 23, 2019. Technical Field

[0002] This disclosure relates to an electronic device, and more particularly to an electronic device having an opening provided in a peripheral area. Background Art

[0003] Electronic products have become indispensable necessities in modern society. With the booming development of such electronic products, consumers have high expectations for the quality, functions, or prices of these products.

[0004] Therefore, electronic products need to be improved. For example, the reliability of electronic devices needs to be improved, but there are still some problems to be solved. Summary of the Invention

[0005] This disclosure is directed to an electronic device having better reliability or display quality.

[0006] According to an embodiment of this disclosure, an electronic device has a peripheral area, including a first substrate, a second substrate, a first support member, a flat layer, and an alignment layer. The second substrate is disposed opposite to the first substrate. The first support member is disposed in the peripheral area and between the first substrate and the second substrate. The flat layer is disposed on the first substrate and has a first portion and an opening. The first portion is disposed in the opening, and the first support member and the first portion overlap in the normal direction of the first substrate. The alignment layer is disposed on the flat layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.

[0007] In summary, for the electronic device according to the embodiment of this disclosure, by providing the flat layer with an opening and a first portion located in the opening, the structural reliability, reliability, performance, or display quality of the electronic device can be improved. Brief Description of the Drawings

[0008] Drawings are included to facilitate a further understanding of this disclosure, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of this disclosure and, together with the description, are used to explain the principles of this disclosure.

[0009] Figure 1 is a top view schematic diagram of an electronic device according to an embodiment of this disclosure;

[0010] Figure 2 is Figure 1 a schematic cross-sectional view taken along section lines A - A' and section lines B - B' of the electronic device;

[0011] Figure 3Top view schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0012] Figure 4 is Figure 3 Cross-sectional schematic diagrams of the electronic device along section lines A-A' and C-C'. Detailed implementation manners

[0013] In the present disclosure, when it is described that a structure (or layer, component, substrate) is located above another structure (or layer, component, substrate), it may mean that the two structures are adjacent and directly connected, or it may mean that the two structures are adjacent but not directly connected. Not being directly connected means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer solid structure or non-solid structure, without limitation. In the present disclosure, when a certain structure is disposed "on" other structures, it may mean that a certain structure is "directly" on other structures, or it may mean that a certain structure is "indirectly" on other structures, that is, there is at least one structure sandwiched between a certain structure and other structures.

[0014] In the present disclosure, the described electrical connection or coupling can both refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the elements on the two circuits are directly connected or connected to each other by a conductor segment. In the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable elements, or a combination of the above elements between the endpoints of the elements on the two circuits, but not limited thereto.

[0015] In the present disclosure, the thickness of each layer can be measured by a scanning electron microscope (SEM), a film thickness profiler (α-step), an ellipsometer or other suitable means. Specifically, in some embodiments, a cross-sectional image of the structure can be obtained using a scanning electron microscope, and the thickness of each layer in the image can be measured. The above thickness can be the maximum thickness in the normal direction in any cross-sectional image, in other words, it can be the maximum thickness in a local area of the electronic device. In addition, the above method of measuring the thickness using a scanning electron microscope includes, after disassembling and cleaving the electronic device to obtain a single substrate, then using the scanning electron microscope to measure the layer thickness. In the present disclosure, the thickness can be measured by an optical microscope (OM), a scanning electron microscope or other suitable means.

[0016] The display device disclosed herein can be applied to various electronic devices. The electronic device may include, but is not limited to, a display device, an antenna device, a sensing device, or a splicing device. The electronic device can be a bendable or flexible electronic device. The electronic device may, for example, include liquid crystal or light-emitting diodes; the light-emitting diodes may, for example, include organic light-emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (quantum dot, QD, which may be, for example, QLED, QDLED), fluorescence, phosphorescence, or other suitable materials, and the materials can be arranged and combined arbitrarily, but are not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any of the foregoing arrangements and combinations, but is not limited thereto. The following will illustrate the content of the present disclosure by taking the display device as the electronic device or the splicing device, but the present disclosure is not limited thereto.

[0017] In the present disclosure, the various embodiments described below can be used in combination without departing from the spirit and scope of the present disclosure. For example, some features of one embodiment can be combined with some features of another embodiment to form another embodiment.

[0018] Reference will now be made in detail to the exemplary embodiments of the present disclosure. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to represent the same or similar parts.

[0019] Figure 1 It is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure. For clarity and convenience of illustration in the drawings, Figure 1 several elements are omitted from showing. Figure 2 For Figure 1 it is a cross-sectional schematic diagram taken along the section lines A-A' and B-B' of the electronic device. For clarity and convenience of illustration in the drawings, Figure 2 several elements are omitted from showing. Please refer to Figure 1 as well as Figure 2, the electronic device 10 includes a first substrate 100, a second substrate 200, a support member (including a first support member PS1), a planarization layer 130, and an alignment layer 150. In this embodiment, the second substrate 200 is disposed opposite to the first substrate 100, and the first support member PS1 is disposed between the first substrate 100 and the second substrate 200. The planarization layer 130 is disposed on the first substrate 100 and has a first portion 131 and an opening 133. The first portion 131 of the planarization layer 130 is located in the opening 133 in the normal direction N, and the first support member PS1 and the first portion 131 overlap in the normal direction N of the first substrate 100. The alignment layer 150 is disposed on the planarization layer 130. In this embodiment, the electronic device 10 may further include a multi-layer conductive layer (including a first conductive layer M1 and a second conductive layer M2 (labeled in Figure 4 )), an insulating layer 140, a packaging element 160, a light-shielding layer BM, a filling layer 220 (overcoat layer, OC), or a display medium layer DM (labeled in Figure 4 ). The insulating layer 140 is disposed on the planarization layer 130. The packaging element 160 is disposed on the insulating layer 140 around the support member. The light-shielding layer BM is disposed on the second substrate 200, and the filling layer 220 is disposed on the light-shielding layer BM such that the light-shielding layer BM is located between the filling layer 220 and the second substrate 200. The first support member PS1 may be disposed on the filling layer 220. In addition, the light-shielding layer BM is disposed between the second substrate 200 and the first support member PS1. In this embodiment, the opening 133 of the planarization layer 130 may form a receiving space, increasing the contact area between the planarization layer 130 and the packaging element 160. In addition, the alignment layer 150 may be formed in the receiving space of the opening 133, increasing the contact area between the alignment layer 150 and the planarization layer 130. In this way, the adhesion between the packaging element 160 and the planarization layer 130 and / or between the alignment layer 150 and the planarization layer 130 can be enhanced, increasing the reliability of the electronic device 10. In addition, the receiving space formed by the opening 133 can buffer the lateral stress of the insulating layer 140 extruded and / or pushed by the support member, reducing the risk of the insulating layer 140 being extruded and broken by the support member, and reducing the influence of moisture passing through the broken insulating layer 140 on the planarization layer 130 or the conductive layer, thereby enhancing the reliability and / or performance of the electronic device 10.

[0020] In this embodiment, the electronic device 10 includes a first substrate 100, a second substrate 200 disposed opposite to the first substrate 100, and a plurality of support members disposed between the first substrate 100 and the second substrate 200. The first substrate 100 or the second substrate 200 may be a transparent substrate, such as a transparent plastic substrate or a glass substrate. For example, the material of the first substrate 100 or the second substrate 200 may include glass, quartz, sapphire, ceramics, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), glass fiber, ceramics, other suitable substrate materials, or a combination of the foregoing, but is not limited thereto. The material of the support member includes a photoresist material or other suitable materials. The material of the support member may also include inorganic materials, organic materials, other suitable materials, or a combination of the above materials, but is not limited thereto. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The above organic materials are, for example (but not limited to): polyimide-based resins, epoxy-based resins, or acrylic-based resins and other polymer materials.

[0021] As Figure 1 and Figure 2 described, the electronic device 10 of this embodiment has a peripheral region 12. The peripheral region 12 can be defined as a region disposed at the edge of the electronic device 10 and surrounding the working area (shown in Figure 3 and Figure 4 ), but this embodiment is not limited thereto. In this embodiment, the support member includes a plurality of first support members PS1 disposed on the first substrate 100 and / or the second substrate 200, and these first support members PS1 are disposed in the peripheral region 12, but this embodiment is not limited thereto. In some embodiments, the support member may also be disposed in the working area. In this embodiment, the support member may be disposed in the peripheral region 12 in an array manner or other suitable manner, but is not limited thereto.

[0022] In this embodiment, the first conductive layer M1 may be disposed on the first substrate 100, and then a plurality of traces, a plurality of electrodes, or a plurality of pads are formed through a patterning process. For example, as Figure 1 and Figure 2As shown, on the first substrate 100, the first conductive layer M1 can form scan lines, gate lines (not shown in the figure), or gates G at least in the peripheral region 12, but is not limited thereto. In some embodiments, the first conductive layer M1 can be disposed on the first substrate 100 and patterned at any position on the first substrate 100 as required. In this embodiment, the material of the first conductive layer M1 includes metal materials, such as aluminum, molybdenum, copper, nickel, titanium, silver, other suitable metals, alloys of the above metals, or combinations of the above metals, but is not limited thereto. In this embodiment, the patterning process of the first conductive layer M1 includes photolithography, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or screen printing, but this embodiment is not limited thereto.

[0023] The gate insulating layer 110 is disposed on the first substrate 100 and partially covers the first conductive layer M1. The material of the gate insulating layer 110 includes inorganic materials, organic materials, other suitable materials, or combinations of the above materials, but is not limited thereto. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The above organic materials are, for example (but not limited to): polymer materials such as polyimide-based resins, epoxy-based resins, or acrylic-based resins.

[0024] In this embodiment, a plurality of active elements T can be disposed on the first substrate 100. The active element T includes a gate G, a semiconductor layer CH, a source S, and a drain D. As Figure 1 and Figure 2 shown, the semiconductor layer CH is disposed on the gate insulating layer 110, and the source S and the drain D are in electrical contact with the semiconductor layer CH. The dielectric layer 120 is disposed on the gate insulating layer 110 and partially covers the semiconductor layer CH, the source S, and the drain D, but this embodiment is not limited thereto. The active element T includes a thin film transistor (TFT), such as a top-gate thin film transistor, a bottom-gate thin film transistor, or other suitable thin film transistors, but is not limited thereto. In this embodiment, the gate G belongs to the first conductive layer M1, and the source S and the drain D belong to the second conductive layer M2. The material of the second conductive layer M2 can include molybdenum, aluminum, copper, nickel, titanium, silver, other suitable metals, alloys of the above metals, or combinations of the above metals, but is not limited thereto. The semiconductor layer CH can include amorphous silicon, low-temperature polycrystalline silicon, or metal oxides, but is not limited thereto. In some embodiments, different active elements T can include different semiconductor layer CH materials, but is not limited thereto.

[0025] In this embodiment, the second conductive layer M2 may be disposed on the gate insulating layer 110, and a plurality of signal traces or pads may be formed through a patterning process. The plurality of signal traces are, for example, data lines (not shown), common electrode lines (not shown), power lines (not shown), ground lines (not shown), or other suitable lines, but this embodiment is not limited thereto. In this embodiment, a plurality of active elements T may be in the gate insulating layer 110 and the dielectric layer 120, electrically connecting the first conductive layer M1 and the second conductive layer M2 and applied as an active element array or a gate on array (GOA), but this embodiment is not limited thereto.

[0026] The dielectric layer 120 is disposed on the gate insulating layer 110 and partially covers the second conductive layer M2. The material of the dielectric layer 120 includes inorganic materials, organic materials, other suitable materials, or a combination of the above materials, but is not limited thereto. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The above organic materials are, for example (but not limited to): polyimide-based resins, epoxy-based resins, or acrylic-based resins and other polymer materials.

[0027] The planarization layer 130 is disposed on the dielectric layer 120. In this embodiment, the planarization layer 130 is, for example, disposed entirely on the dielectric layer 120, and is partially located in the peripheral region 12 and has a distance (not marked) from the outer edge of the electronic device 10. That is, the planarization layer 130 is not flush with the edge of the first substrate 100. From another perspective, the planarization layer 130 has a spaced distance from the edge of the first substrate 100. The planarization layer 130 overlaps the first conductive layer M1, the second conductive layer M2, and / or a plurality of active elements T in the normal direction N of the first substrate 100. The material of the planarization layer 130 includes organic materials, but this embodiment is not limited thereto. For example, the material of the planarization layer 130 includes materials such as perfluoroalkoxy polymer resin (PFA), polymer film on array (PFA), fluoroelastomers, etc., but is not limited thereto. In some embodiments, the material of the planarization layer 130 may also include inorganic materials, other suitable materials, or a combination of the above materials, but is not limited thereto.

[0028] In this embodiment, the thickness of the planarization layer 130 is, for example, from 0.1 micrometer (μm) to 5 micrometers (0.1 μm ≤ thickness ≤ 5 μm), or from 1.5 micrometers to 2.5 micrometers (1.5 μm ≤ thickness ≤ 2.5 μm), but the present disclosure is not limited thereto. In this embodiment, the thickness of the planarization layer 130 can be defined as the maximum thickness of the planarization layer 130 in the normal direction N of the first substrate 100 after dicing. With the above settings, the planarization layer 130 can have a sufficient thickness so that the openings 133 in the peripheral region 12 can also have a sufficient thickness, enabling the subsequent alignment layer 150 to flow into the openings 133 during manufacturing, reducing the thickness of the alignment layer 151 on the planarization layer 130, and increasing the thickness of the alignment layer 153 in the openings 133. The increase in the thickness of the alignment layer 153 can increase its anchoring energy. In addition, the reduction in the thickness of the alignment layer 151 on the first portion 131 can reduce the fragments that may be generated in subsequent processes, improving the reliability or performance of the electronic device 10, or improving the display quality of the electronic device 10.

[0029] The insulating layer 140 is disposed on the planarization layer 130. In this embodiment, the insulating layer 140 is, for example, disposed entirely on the first substrate 100 and partially covers the planarization layer 130, and is partially located in the peripheral region 12. The material of the insulating layer 140 includes inorganic materials. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. In some embodiments, the material of the insulating layer 140 further includes organic materials, other suitable materials, or a combination of the above materials, but is not limited thereto. The above organic materials are, for example (but not limited to): polyimide-based resins, epoxy-based resins, or acrylic-based resins and other polymer materials. In this embodiment, the insulating layer 140 is an inorganic material and the planarization layer 130 is an organic material, but is not limited thereto.

[0030] In this embodiment, the thickness of the insulating layer 140 is, for example, from 0.1 micrometer to 0.8 micrometers (0.1 μm ≤ thickness ≤ 0.8 μm), or from 0.25 micrometers to 0.75 micrometers (0.25 μm ≤ thickness ≤ 0.75 μm), but the present disclosure is not limited thereto. In this embodiment, the thickness of the insulating layer 140 can be defined as the maximum thickness of the insulating layer 140 in the normal direction N of the first substrate 100 after dicing. It should be noted that the thickness of the planarization layer 130 divided by the thickness of the insulating layer 140 is greater than or equal to 1.5 and less than or equal to 25 With the above settings, the insulating layer 140 can protect the planarization layer 130 from the influence of moisture, or the planarization layer 130 can have a sufficient thickness so that the surface of the planarization layer 130 in contact with the insulating layer 140 can be flat, improving the structural reliability of the electronic device 10.

[0031] The alignment layer 150 is disposed on the insulating layer 140 on the flat layer 130. In the present embodiment, the alignment layer 150 is disposed on the first substrate 100, and a part of the alignment layer 150 is located in the peripheral region 12. The alignment layer 150 may overlap a part of the flat layer 130 or the insulating layer 140 in the normal direction N of the first substrate 100. In other words, the insulating layer 140 is disposed between the flat layer 130 and the alignment layer 150, but the present embodiment is not limited thereto. The material of the alignment layer 150 includes an organic material, such as polyimide, but the present disclosure is not limited thereto. In some embodiments, the material of the alignment layer 150 may also include an inorganic material. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials.

[0032] In the present embodiment, the thickness of the alignment layer 150 is, for example, 300 angstroms to 1500 angstroms (300 angstroms ≤ thickness ≤ 1500 angstroms), or 500 angstroms to 1200 angstroms (500 angstroms ≤ thickness ≤ 1200 angstroms), but the present disclosure is not limited thereto. In the present embodiment, the thickness of the alignment layer 150 can be defined as the maximum thickness of the alignment layer 150 in the normal direction N of the first substrate 100 after dicing.

[0033] The light-shielding layer BM is disposed on the second substrate 200. In the present embodiment, the light-shielding layer BM may be partially located in the peripheral region 12. The light-shielding layer BM is, for example, a black matrix, but the present disclosure is not limited thereto. The light-shielding layer BM can be patterned to have a plurality of patterned openings (not shown in the figure) corresponding to a plurality of pixel regions (not shown in the figure). For example, the light-shielding layer BM can overlap, in the normal direction N of the first substrate 100, the patterned traces (not shown in the figure) of the first conductive layer M1 or the patterned signal traces (not shown in the figure) of the second conductive layer M2, but the present disclosure is not limited thereto.

[0034] The planarization layer 220 is disposed on the light-shielding layer BM. In the present embodiment, the planarization layer 220 can be disposed on the light-shielding layer BM and is partially located in the peripheral region 12. The planarization layer 220 is, for example, a transparent planarization layer, but the present disclosure is not limited thereto.

[0035] It should be noted that the light-shielding layer BM in this embodiment has a groove OP in the peripheral area 12, and the groove OP can surround the electronic device 10 in the peripheral area 12. The groove OP does not overlap with the flat layer 130 in the normal direction of the first substrate 100. In other words, the groove OP of the light-shielding layer BM is located in the area where the light-shielding layer BM does not overlap with the flat layer 130. In this embodiment, there is a distance K between the groove OP and the outer edge 11 of the electronic device 10. The distance K can be, for example, 10 micrometers to 150 micrometers (10 micrometers ≤ distance K ≤ 150 micrometers), or 50 micrometers to 100 micrometers (50 micrometers ≤ distance K ≤ 100 micrometers). The above-mentioned distance K can be defined as the shortest distance between the outer edge 11 of the electronic device 10 and the outer edge 211 of the groove OP in the local area in the normal direction N perpendicular to the first substrate 100. The width W of the groove OP can be 10 micrometers to 100 micrometers (10 micrometers ≤ width W ≤ 100 micrometers), or 15 micrometers to 25 micrometers (15 micrometers ≤ width W ≤ 25 micrometers). The above-mentioned width W of the groove OP can be defined as the maximum width of the groove OP in the local area in the normal direction N perpendicular to the first substrate 100.

[0036] Under the above settings, the filling layer 220 can be filled into the groove OP to increase the contact area or adhesion strength between the filling layer 220 and the light-shielding layer BM, which can improve the reliability or performance of the electronic device 10, or improve the display quality of the electronic device 10.

[0037] A plurality of support members are disposed on one of the first substrate 100 or the second substrate 200. In this embodiment, the plurality of support members include a plurality of first support members PS1 disposed in the peripheral area 12. The first support member PS1 is disposed on the filling layer 220 on the second substrate 200 and abuts against the flat layer 130 on the first substrate 100. Specifically, the first support member PS1 abuts against the surface of the insulating layer 140 on the flat layer 130, but the present disclosure is not limited thereto. In some embodiments, the first support member PS1 may not contact the insulating layer 140. In some embodiments, the first support member PS1 may also contact the alignment layer 151. Due to the setting of the opening 133, the thickness of the alignment layer 151 on the first portion 131 of the flat layer 130 can be reduced, and the contact between the first support member PS1 and the alignment layer 151 is reduced, so that the fragments of the alignment layer 151 that may be caused by extrusion during contact are reduced, which can improve the reliability or performance of the electronic device 10, or improve the display quality of the electronic device 10.

[0038] In this embodiment, the electronic device 10 further includes an alignment layer 250. The alignment layer 250 may be disposed on the planarization layer 220 and surround the first support PS1. That is, the alignment layer 250 may be in direct contact with the first support PS1. In the normal direction N1 of the first substrate 100, the alignment layer 250 is not located between the first support PS1 and the planarization layer 220, but this embodiment is not limited thereto. In some embodiments, the alignment layer 250 may be in direct contact with the sidewall of the first support PS1. In some embodiments, the alignment layer 250 may be in direct contact with the top surface of the first support PS1. In other embodiments, the alignment layer 250 may not contact the first support PS1. The material of the alignment layer 250 may be the same as or different from that of the alignment layer 150, including organic materials such as polyimide, but this disclosure is not limited thereto. In some embodiments, the material of the alignment layer 250 may also include inorganic materials. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials.

[0039] The encapsulation element 160 is disposed in the peripheral region 12 and is located between the first substrate 100 and the second substrate 200. In this embodiment, the encapsulation element 160 is, for example, a sealant, and is disposed around the electronic device 10 adjacent to the outer edge and overlaps a part of the peripheral region 12. For example, the encapsulation element 160 may overlap a part of the trace of the first conductive layer M1, a part of the signal trace of the second conductive layer M2, and the active element T in the normal direction N of the first substrate 100. The material of the encapsulation element 160 includes epoxy resin, polymethylmethacrylate (PMMA), photo-curable adhesive, thermo-curable adhesive, photo-thermo-curable adhesive, other suitable materials, or a combination of the above materials, but this disclosure is not limited thereto.

[0040] The electronic device 10 of this embodiment is a technology that applies the first support PS1 in the encapsulation element 160. Under the above settings, the encapsulation element 160 can be in direct contact with the alignment layer 150 and the alignment layer 250, and the encapsulation element 160 surrounds the first support PS1. In addition, the electronic device 10 of this embodiment further includes a planarization layer 130 disposed in the peripheral region 12, and the planarization layer 130 partially overlaps the encapsulation element 160 in the normal direction N of the first substrate 100. Since the planarization layer 130 can cover the first conductive layer M1, the second conductive layer M2, and / or the active element T in the peripheral region 12, thereby maintaining the consistency of the thickness of the display medium layer (shown in Figure 4 ) and making the overall thickness of the electronic device 10 consistent or similar, improving the structural reliability or performance. In addition, the planarization layer 130 can also protect the traces and / or the active element T in the peripheral region 12, improving the display quality of the electronic device 10.

[0041] It should be noted that the flat layer 130 has a first portion 131 and an opening 133. As Figure 1 and Figure 2 described, the flat layer 130 can be patterned to form a plurality of openings 133, 133A to surround a plurality of corresponding first portions 131. That is to say, the first portion 131 can be disposed in the opening 133 and / or the opening 133A to form, for example, an island shape. As Figure 1 can be seen, the first portion 131 can be circular in the normal direction N of the first substrate 100 (for example, in the top view direction), and the openings 133, 133A surround the first portion 131 and have an arc-shaped edge in the normal direction N of the first substrate 100, for example, a circular arc shape, but this embodiment is not limited thereto. In some embodiments, the first portion 131, the opening 133 and / or the opening 133A can also be oval, rectangular, triangular, irregular or other suitable shapes in the top view, but are not limited thereto. In this embodiment, the distance W1 between the opening 133 and the opening 133A can be 5 micrometers to 50 micrometers (5 micrometers ≤ distance W1 ≤ 50 micrometers). The width W3 of the first portion 131 is 15 micrometers to 50 micrometers (15 micrometers ≤ width W3 ≤ 50 micrometers), or 25 micrometers to 30 micrometers (25 micrometers ≤ width W3 ≤ 30 micrometers). The distance W1 between the opening 133 and the opening 133A can be defined as the minimum distance between the opening sidewalls of the opening 133, 133A and the first portion 131 in the direction perpendicular to the normal direction N of the first substrate 100. The width W3 of the first portion 131 can be defined as the maximum width of the first portion 131 in the direction perpendicular to the normal direction N of the first substrate 100.

[0042] In this embodiment, the openings 133 and 133A are, for example, grooves formed in the flat layer 130 in the normal direction N of the first substrate 100. The opening 133 may penetrate the flat layer 130 in the normal direction N of the first substrate 100, but this embodiment is not limited thereto. The insulating layer 140 may cover the flat layer 130 and fill the openings 133 and 133A and / or cover the top surface and / or side walls of the first portion 131 in the openings 133 and 133A. The side walls of the first portion 131 are not parallel to the normal direction N, but have an inclination angle. When viewed from a side direction, the formed first portion 131 is generally trapezoidal in shape, which can increase the surface area of the first portion 131. This inclination angle can enable the alignment layer to flow into the openings 133 and 133A during the subsequent process of manufacturing the alignment layer, reducing the thickness of the alignment layer 151 on the first portion 131 and increasing the thickness of the alignment layer 153 in the openings 133 and 133A, but this is not limited thereto. In this way, the flat layer 130 can increase the surface in contact with the insulating layer 140 through the openings 133 and 133A, thereby increasing the adhesion or reliability between the flat layer 130 and the insulating layer 140.

[0043] In addition, the alignment layer 150 formed on the insulating layer 140 may partially overlap the first portion 131, the opening 133, the first portion 131, and the flat layer 130 outside the opening 133 in the normal direction N of the first substrate 100. For example, in the manufacturing process of forming the alignment layer 150, the alignment layer 150 adjacent to the outer edge of the opening 133 will slide along the surface of the insulating layer 140 into the opening 133 and form in the accommodation space of the opening 133. In this way, the alignment layer 150 may include the alignment layer 151 that overlaps a part of the first portion 131 (for example, on the first portion 131) in the normal direction N of the first substrate 100 and the alignment layer 153 located in the opening 133. Under the above settings, the surface area of the alignment layer 150 can be increased. In this way, the area of direct contact between the encapsulation element 160 and the alignment layer 150 (including the alignment layer 151 on the first portion 121 and the alignment layer 153 in the opening 133) can be increased. Thereby, the adhesion or reliability between the encapsulation element 160 and the alignment layer 150 can be increased.

[0044] In this embodiment, the alignment layer 151 on the first portion 131 has a first thickness H1, and the alignment layer 153 in the opening 133 has a second thickness H2. The first thickness H1 is greater than or equal to zero and less than the second thickness H2. For example, the first thickness H1 is greater than or equal to 0 Å and less than or equal to 500 Å, but the present disclosure is not limited thereto. The second thickness is greater than 0 Å and less than or equal to 5000 Å. In some embodiments, the second thickness H2 may also be greater than or equal to 500 Å and less than or equal to 1200 Å, but the present disclosure is not limited thereto. In this embodiment, the first thickness H1 can be defined as the minimum thickness of the alignment layer 151 substantially located on the central region of the first portion 131 in the normal direction N of the first substrate 100. The above minimum thickness can be defined as the minimum thickness in any cross-sectional image of the structure obtained by a scanning electron microscope. The second thickness H2 can be defined as the maximum thickness of the alignment layer 152 located in the opening 133 in the normal direction N of the first substrate 100.

[0045] In addition, the first support member PS1 overlaps the first portion 131 in the normal direction N of the first substrate 100, that is, the first support member PS1 abuts against the first portion 131. In this embodiment, the width W2 of the first support member PS1 is less than the width W3 of the first portion 131. In this embodiment, the width W2 can be defined as the maximum width of the first support member PS1 in a direction perpendicular to the normal direction N of the first substrate 100. The width W3 can be defined as the maximum width of the first portion 131 in a direction perpendicular to the normal direction N of the first substrate 100. The width W2 of the first support member PS1 is 5 μm to 40 μm (5 μm ≤ width W2 ≤ 40 μm), or 9.5 μm to 15 μm (9.5 μm ≤ width W2 ≤ 15 μm), but this embodiment is not limited thereto.

[0046] In some embodiments, the alignment layer 150 in the peripheral region 12 does not align with the outer edge of the first substrate 100, and the alignment layer 250 does not align with the outer edge of the second substrate 200, whereby partial inorganic material layers can be exposed, such as (but not limited to) the insulating layer 140, the dielectric layer 120, the gate insulating layer 110, the first substrate 100, or the second substrate 200. In this way, the packaged component 160 can directly contact the inorganic material layers, which can increase the structural reliability or display quality of the electronic device 10.

[0047] In this embodiment, as Figure 2As shown, the first part 131 located in the opening 133 may overlap with the first conductive layer M1 in the normal direction N of the first substrate 100. The first support PS1 opposite to the first part 131 may overlap with the first conductive layer M1 in the normal direction N of the first substrate 100, but this embodiment is not limited thereto. In some embodiments, the flat layer 130 that does not overlap with the first support PS1 may also overlap with the first conductive layer M1, the second wire layer M2, or the active element T in the normal direction N of the first substrate 100, and this embodiment is not limited thereto. In this embodiment, the insulating layer 140 is disposed between the first support PS1 and the flat layer 130. In this way, when the first support PS1 directly contacts and presses the insulating layer 140, the accommodation space formed by the opening 133 of the flat layer 130 can buffer the lateral stress of the insulating layer 140 pressed and / or pushed by the first support PS1. Specifically, compared with the flat layer 130, the harder insulating layer 140 can pass through the opening 133 on the softer flat layer 130 to allow the insulating layer 140 to move laterally to buffer the influence of stress on the insulating layer 140. Therefore, the risk of the insulating layer 140 being pressed and broken by the first support PS1 can be reduced. In addition, the phenomenon that moisture passes through the broken insulating layer 140 to cause the flat layer 130 to absorb moisture and swell can be reduced, or the influence of moisture on the conductive layer covered by the insulating layer 140 can be reduced, improving the reliability and / or performance or display quality of the electronic device 10.

[0048] In this embodiment, the encapsulation element 160 may also be filled into the opening 133. In this way, the contact area between the encapsulation element 160 and the insulating layer 140 or between the encapsulation element 160 and the flat layer 130 can be increased. Thereby, the adhesion between the encapsulation element 160 and the insulating layer 140 or the flat layer 130 can be enhanced to increase the reliability of the electronic device 10.

[0049] In some embodiments, the plurality of openings 133 may or may not correspond to the supports according to the user's needs. In addition, since the sizes of the plurality of supports can be set according to the user's needs, the sizes of the plurality of openings 133 must also be designed corresponding to the sizes of the corresponding supports. In other words, the distances W1 of the openings 133 may be the same or different, and the distance W1 sizes of the openings 133 at different positions may be the same or different, and this embodiment is not limited thereto. For example, Figure 2The distance W1 of the opening 133 located adjacent to the outer edge 11 of the electronic device 10 as shown may be greater than or equal to the distance W1 of the opening 133A located away from the outer edge 11, but this embodiment is not limited thereto. For example, the distance W1 of the opening 133 adjacent to the outer edge 11 may be 10 micrometers, and the distance W1 of the opening 133A away from the outer edge 11 may be 6 micrometers, but this embodiment is not limited thereto. In this way, the opening width can be adjusted according to the design requirements of the support or the different position requirements where the support is located, so as to increase the adhesion between the support and the insulating layer 140. It should be noted that for the clarity of the drawings and convenience of description, Figure 2 The distances W1 of different openings 133 and 133A and the distances W1 of different supports are schematically shown to be the same, but those skilled in the art should understand that as long as the distance W1 of the opening 133 can overlap the conductive layer and enable the alignment layer 150 to fill the openings 133 and 133A, they can be used in combination without departing from the spirit and scope of this disclosure.

[0050] In this embodiment, a part of the encapsulation element 160 may also overlap the insulating layer 140 and / or the dielectric layer 120 in the normal direction N of the first substrate 100, but does not overlap the planarization layer 130. That is to say, the outer edge of the encapsulation element 160 in the normal direction of the first substrate 100 may be located between the outer edge of the first substrate 100 and the outer edge of the planarization layer 130, but this embodiment is not limited thereto. In some embodiments, the outer edge of the encapsulation element 160 may also be flush with the outer edge of the planarization layer 130. In some embodiments, the outer edge of the encapsulation element 160 may also be flush with the outer edge of the first substrate 100. In addition, the groove OP of the light-shielding layer BM may also not overlap the encapsulation element 160 in the normal direction N, but this embodiment is not limited thereto.

[0051] Briefly speaking, for the electronic device 10 of an embodiment of the present disclosure, since a flat layer 130 can be disposed in the peripheral area 12, and there are a plurality of openings 133 and a first portion 131 located in the openings 133 on the flat layer 130. Thereby, the contact area of the flat layer 130 can be increased, and the alignment layer 150 on the flat layer 130 can flow into the plurality of openings 133 during the manufacturing process, which can reduce the thickness of the alignment layer 151 on the flat layer 130, improve the adhesion between the encapsulation element 160 and the flat layer 130, and enhance the structural reliability of the electronic device 10. In addition, the alignment layer 150 can flow into the openings 133, reducing the thickness of the alignment layer 151 on the flat layer 130, which can reduce the fragments that may be generated by the alignment layer 151. In this way, the reliability or performance of the electronic device 10 can be improved. Additionally, a first thickness H1 of the alignment layer 151 located on the first portion 131 is less than a second thickness H2 of the alignment layer 153 in the openings 133. In this way, the adhesion between the alignment layer 150 and the insulating layer 140 can be increased, or the first support member PS1 can contact the insulating layer 140 to increase the adhesion between the first support member PS1 and the insulating layer 140. Additionally, the adhesion between the encapsulation element 160 and the alignment layer 150 can also be improved. Furthermore, the openings 133 can also buffer the lateral stress of the insulating layer 140 squeezed and / or pushed by the first support member PS1, reducing the risk of the insulating layer 140 being broken due to being squeezed by the first support member PS1, and reducing the phenomenon that moisture passes through the broken insulating layer 140 to cause the flat layer 130 to absorb moisture and swell, improving the reliability, performance or display quality of the electronic device 10. Additionally, the flat layer 130 overlaps the first wire layer M1, the second wire layer M2 or the active element T in the normal direction N of the first substrate 100, which can also protect the above elements, reduce the direct influence of the external environment on the performance of the electronic components, and improve the performance or display quality of the electronic device 10.

[0052] Figure 3 is a top view schematic diagram of an electronic device according to another embodiment of the present disclosure. For the clarity and convenience of illustration in the drawings, Figure 3 several elements are omitted from being shown. Figure 4 is Figure 3 a schematic cross-sectional view of the electronic device along the section lines A-A' and C-C'. For the clarity and convenience of illustration in the drawings, Figure 4 several elements are omitted from being shown. The electronic device 10A of this embodiment is substantially similar to Figure 1 the electronic device 10, so the same and similar components in the two embodiments will not be repeated here. The difference between this embodiment and the electronic device 10 mainly lies in that the electronic device 10A further has a working area 14.

[0053] Specifically, the working area 14 can be defined, for example, as an area where the electronic device 10A has a signal adjustable function, such as an optical signal or an electromagnetic wave signal, but this embodiment is not limited thereto. In this embodiment, the working area 14 can be disposed adjacent to the peripheral area 12 and surrounded by the peripheral area 12, but this embodiment is not limited thereto. The working area 14 may include a plurality of working electrodes (not shown in the figure) (which may be, for example, pixel electrodes and common electrodes) and an active element array (not shown in the figure). Please refer to Figure 3 and Figure 4 , in the working area 14, an active element T is disposed on the first substrate 100, and the planarization layer 130 is disposed on the dielectric layer 120 and partially overlaps the first conductive layer M1, the second conductive layer M2, and the active element T in the normal direction N of the first substrate 100. In this embodiment, a display medium DM can also be disposed between the first substrate 100 and the second substrate 200. The material of the display medium DM includes liquid crystal materials, electro-wetting display materials, electrophoretic display materials, etc., but this embodiment is not limited thereto. The active element T is electrically connected to the pixel electrode and is used to provide a driving electric field to drive the display medium DM to achieve the required signal adjustable effect.

[0054] In this embodiment, the planarization layer 130 of the electronic device 10A further has a plurality of openings 134 disposed in the working area 14. The openings 134 in the working area 14 are substantially similar to the openings 133 in the peripheral area 12, so they will not be described again. The width W4 of the openings 134 in the working area 14 and the distance W1 of the openings 133 in the peripheral area 12 can be the same or different, and this embodiment does not limit it. For example, the distance W1 of the openings 133 in the peripheral area 12 can be greater than or equal to the width W4 of the openings 134 in the working area 14, or the width W4 of the openings 134 in the working area 14 can be greater than or equal to the distance W1 of the openings 133 in the peripheral area 12, but this embodiment is not limited thereto.

[0055] In this embodiment, the alignment layer 150 further includes an alignment layer 152 disposed on the first portion 132 and an alignment layer 154 disposed in the openings 134. As Figure 4 shown, a partial alignment layer on the first portion 132 can slide into the openings 134 to become the alignment layer 154 formed in the accommodation space of the openings 134.

[0056] As Figure 3 and Figure 4As shown, the electronic device 10A further includes a second support member PS2 disposed in the working area 14, and the second support member PS2 is disposed between the first substrate 100 and the second substrate 200. For example, the second support member PS2 may be disposed on the first portion 132 in the opening 134 in the working area 14. The second support member PS2 is substantially similar to the first support member PS1, and thus will not be repeated. The second support member PS2 overlaps the first portion 132 in the normal direction N of the first substrate 100, that is, the second support member PS2 abuts against the first portion 132. In addition, with respect to the first support member PS1, the second support member PS2 may overlap the second conductive layer M2 in the normal direction N of the first substrate 100. In some embodiments, the second support member PS2 may overlap the first conductive layer M1 and the second conductive layer M2 in the normal direction N of the first substrate 100, but is not limited thereto. In some embodiments, the second support member PS2 abuts against the surface of the insulating layer 140 on the flat layer 130, but this embodiment is not limited thereto. In other embodiments, the second support member PS2 may also be in contact with the alignment layer 152. Due to the setting of the opening 134, the thickness of the alignment layer 152 on the first portion 132 of the flat layer 130 can be reduced, and the contact between the second support member PS2 and the alignment layer 152 can be reduced, so that the broken pieces of the alignment layer 152 that may be caused during contact can be reduced. In this way, the reliability or performance of the electronic device 10A can be improved, or the display quality of the electronic device 10A can be improved.

[0057] In this embodiment, the width of the second support member PS2 is smaller than the width of the first portion 132. The width of the second support member PS2 is 15 micrometers to 50 micrometers (15 micrometers ≤ width ≤ 50 micrometers), or 20 micrometers to 30 micrometers (20 micrometers ≤ width ≤ 30 micrometers). The width of the second support member PS2 can be defined as the maximum width of the first support member PS2 in the direction perpendicular to the normal direction N of the first substrate 100. In addition, the width of the first support member PS1 and the width of the second support member PS2 may be the same or different. In some embodiments, the width of the first support member PS1 may be greater than or equal to the width of the second support member PS2. In other embodiments, the width of the second support member PS2 may be greater than or equal to the width of the first support member PS1, but this disclosure is not limited thereto.

[0058] It should be noted that the height H3 of the first support member PS1 in this embodiment is the same as the height H4 of the second support member PS2. For example, the height H3 of the first support member PS1 is from 1 μm to 6 μm (1 μm ≤ height H3 ≤ 6 μm), or from 2 μm to 4 μm (2 μm ≤ height H3 ≤ 4 μm). The height H4 of the second support member PS2 is from 1 μm to 6 μm (1 μm ≤ height H4 ≤ 6 μm), or from 2 μm to 4 μm (2 μm ≤ height H4 ≤ 4 μm). The height H3 of the first support member PS1 can be defined as the maximum height of the first support member PS1 located on the first part 131 in the normal direction N of the first substrate 100. The height H4 of the second support member PS2 can be defined as the maximum height of the second support member PS2 located on the first part 132 in the normal direction N of the first substrate 100. Under the above settings, the thickness maintained by the second support member PS2 in the working area 14 can be substantially the same or similar to the thickness maintained by the first support member PS1 in the peripheral area 12. In this way, the overall thickness of the electronic device 10A can be substantially the same or similar, so as to improve the structural reliability or performance, or improve the display quality of the electronic device 10A.

[0059] In summary, for the electronic device of the disclosed embodiment, since a planarization layer can be provided in the peripheral area and / or the working area, and the planarization layer has a plurality of openings and a first part located in the openings. Thereby, the contact area of the planarization layer can be increased, and the alignment layer on the planarization layer can flow into the plurality of openings during the manufacturing process, which can reduce the thickness of the alignment layer on the planarization layer, reduce the possible fragments generated by the alignment layer, or enable the first support member and / or the second support member to contact the insulating layer to respectively increase the adhesion between the first support member and / or the second support member and the insulating layer, and improve the adhesion between the packaged component and the planarization layer, which can improve the reliability or performance of the electronic device, or improve the overall structural reliability of the electronic device. In addition, the openings can also buffer the lateral stress of the insulating layer squeezed and / or pushed by the supported members (including the first support member or the second support member), so that the risk of the insulating layer being squeezed and broken by the supported members can be reduced, and the phenomenon of moisture absorption and swelling of the planarization layer caused by moisture passing through the broken insulating layer can be reduced, improving the reliability, performance or display quality of the electronic device. The planarization layer overlaps the first wire layer, the second wire layer or the active element in the normal direction of the first substrate, which can protect the electronic components in the electronic device, reduce the influence of the external environment on the performance of the electronic components, and improve the performance or display quality of the electronic device.

[0060] In addition, the ratio of the thickness of the flat layer to that of the insulating layer can enhance the effect of the insulating layer protecting the flat layer from moisture. Making the flat layer have a sufficient thickness can increase the surface flatness of the flat layer in contact with the insulating layer, so as to enhance the structural reliability of the electronic device. The light-shielding layer can be provided with grooves in the area not corresponding to the overlapping flat layer, and the filling layer can be filled into the grooves to increase the adhesion strength, which can enhance the reliability, performance or display quality of the electronic device.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure. Any person skilled in the art in the technical field can make changes, substitutions and refinements without departing from the spirit and scope of the present disclosure. And the protection scope of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. An electronic device having a peripheral region, characterized in that, the peripheral region of the electronic device includes: a first substrate; a second substrate disposed opposite to the first substrate; a plurality of first support members disposed between the first substrate and the second substrate; a flat layer disposed on the first substrate, having a plurality of first portions and a plurality of openings, the plurality of first portions are respectively disposed in the plurality of openings, and at least one of the plurality of first support members and at least one of the plurality of first portions overlap in the normal direction of the first substrate; and an alignment layer disposed on the flat layer, wherein, the alignment layer on the first portion has a first thickness, the alignment layer in the opening has a second thickness, and the first thickness is greater than or equal to zero and less than the second thickness.

2. The electronic device according to claim 1, characterized in that, in the normal direction of the first substrate, the opening has an arc-shaped edge.

3. The electronic device according to claim 1, characterized in that, the first thickness is greater than or equal to 0 Å and less than or equal to 500 Å.

4. The electronic device according to claim 1, characterized in that, further comprising an insulating layer disposed on the flat layer, the insulating layer being disposed between the plurality of first support members and the flat layer.

5. The electronic device according to claim 1, characterized in that, further comprising a packaging element disposed in the peripheral region, and the packaging element surrounds the plurality of first support members.

6. The electronic device according to claim 5, characterized in that, the packaging element is in direct contact with the alignment layer.

7. The electronic device according to claim 5, characterized in that, the packaging element and the flat layer overlap in the normal direction of the first substrate.

8. The electronic device according to claim 1, characterized in that, the electronic device further has a working region disposed adjacent to the peripheral region, wherein the electronic device further includes: a second support member disposed in the working region and disposed between the first substrate and the second substrate, and the height of the plurality of first support members is the same as the height of the second support member.

9. The electronic device according to claim 1, characterized in that, further comprising a first conductive layer, and the first portion and the first conductive layer overlap in the normal direction of the first substrate.

10. The electronic device according to claim 1, characterized in that, further comprising: a light-shielding layer disposed between the second substrate and the plurality of first support members, wherein the groove of the light-shielding layer does not overlap with the flat layer in the normal direction of the first substrate.

11. An electronic device having a peripheral region, characterized in that, the peripheral region of the electronic device includes: a first substrate; a second substrate disposed opposite to the first substrate; a first support member disposed between the first substrate and the second substrate; A flat layer is disposed on the first substrate, having a plurality of first portions and a plurality of openings. In a top view, the plurality of first portions have an island-like appearance, the plurality of openings respectively surround the plurality of first portions, and the plurality of first support members and the plurality of first portions overlap in the normal direction of the first substrate; and An alignment layer is disposed on the flat layer, wherein the alignment layer on one of the plurality of first portions has a first thickness, the alignment layer in one of the plurality of openings has a second thickness, and the first thickness is greater than or equal to zero and less than the second thickness.

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