Array substrate and display panel
By setting a flow guide in the edge area of the contact hole of the array substrate, the surface tension of the alignment liquid is damaged, and the problem of stacking of the contact hole edge alignment liquid in COA technology is solved, the consistency of the orientation of the liquid crystal molecules is improved, and the optical performance of the display is improved.
Patent Information
- Application Number
- CN202510527326.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-06-17
AI Technical Summary
In array substrates using COA technology, the accumulation of alignment liquid at the edge of the contact hole leads to uneven distribution of the alignment film thickness, which in turn causes disordered orientation of liquid crystal molecules.
A flow guide is provided in the edge area of the contact hole of the array substrate. The flow guide is located in the opening of the chromoresis layer, and its forward projection is completely located in the forward projection of the opening of the chromoresis layer to destroy the surface tension of the alignment liquid, improve the flow of liquid, and avoid the flow guide from affecting the product surface pressure and taste.
By setting a flow guide on the edge of the contact hole, the surface tension of the alignment liquid is effectively destroyed, the liquid flow is improved, and the accumulation of the alignment liquid is avoided, thereby improving the consistency of the orientation of the liquid crystal molecules, and improving the optical properties such as brightness uniformity and contrast of the display.
Smart Images
Figure CN120161640A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technologies, and in particular, to an array substrate and a display panel. Background Art
[0002] The core structure of a liquid crystal display (LCD) screen generally includes an array substrate and a color filter substrate. During the manufacturing process of the array substrate, the coating and curing of the alignment liquid are one of the key process steps. For example, a polyimide (PI) liquid is coated, pre-baked, and cured to form an alignment film, whose function is to provide a pretilt angle for liquid crystal molecules to ensure the consistency of the alignment of liquid crystal molecules under the action of an electric field. The film thickness uniformity of the alignment film directly affects the alignment effect of the liquid crystal layer, and further determines the optical properties such as the brightness uniformity and contrast of the display.
[0003] In the design of the array substrate, to achieve electrical connection between different conductive layers or electrical components, a large number of contact holes are usually required to be formed on the substrate. These contact holes are formed by etching the insulating layer to ensure vertical conduction of the circuit structure. However, with the evolution of display technologies towards high resolution and high integration (for example, adopting the COA (Color filter On Array) technology to integrate the color filter layer on the array substrate), the structural complexity of the array substrate has increased significantly, thus posing higher requirements on the coating process of the alignment liquid.
[0004] Due to the relatively high surface tension of the alignment liquid itself, the surface tension effect will hinder the liquid flow, resulting in the accumulation of the alignment liquid at the edges of the contact holes. In the subsequent baking process, the accumulated alignment liquid will solidify to form a local film thickness abnormal area around the contact holes, leading to uneven distribution of the alignment film thickness and further causing disorder in the alignment of liquid crystal molecules. Summary of the Invention
[0005] The present application provides an array substrate and a display panel to alleviate the technical problem of the accumulation of the alignment liquid at the edges of the contact holes existing in the array substrate using the COA technology.
[0006] To solve the above problems, the technical solutions provided by the present application are as follows:
[0007] An embodiment of the present application provides an array substrate, which includes:
[0008] A substrate;
[0009] A driving circuit layer disposed on one side of the substrate;
[0010] A color resist layer disposed on the side of the driving circuit layer away from the substrate, the color resist layer being provided with a plurality of openings that expose a part of the driving circuit layer;
[0011] A planar layer is disposed on a side of the color resist layer away from the substrate. The planar layer is provided with a plurality of contact holes. The contact holes are located within the openings and expose a part of the driving circuit layer.
[0012] A flow guiding member is disposed on a side of the planar layer away from the substrate. The flow guiding member is located within the openings and at an edge region of at least one of the contact holes.
[0013] Wherein, a positive projection of the flow guiding member on the substrate is located within a positive projection of the corresponding opening on the substrate.
[0014] In the array substrate provided in the embodiment of the present application, the planar layer is provided with a plurality of the contact holes within a first type of openings among the plurality of openings. The flow guiding member is located between two adjacent ones of the contact holes within the first type of openings.
[0015] In the array substrate provided in the embodiment of the present application, a boundary of the flow guiding member facing the contact hole coincides with a part of a boundary of the contact hole.
[0016] In the array substrate provided in the embodiment of the present application, the driving circuit layer includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the color resist layer.
[0017] Among the plurality of contact holes, a first type of contact holes exposes a part of the first metal layer. Among the plurality of contact holes, a second type of contact holes exposes a part of the first metal layer and a part of the second metal layer.
[0018] Wherein, the plurality of contact holes within the first type of openings includes the first type of contact holes and the second type of contact holes.
[0019] In the array substrate provided in the embodiment of the present application, the planar layer is provided with one contact hole within a second type of openings among the plurality of openings.
[0020] Among the plurality of contact holes, a third type of contact holes exposes a part of the second metal layer. The second type of openings is provided with the second type of contact holes or the third type of contact holes. An aperture of the third type of contact holes is smaller than an aperture of the second type of contact holes and smaller than an aperture of the first type of contact holes.
[0021] In the array substrate provided in the embodiment of the present application, the color resist layer further includes at least one communication groove. The first type of openings is communicated with the second type of openings through the communication groove.
[0022] In the array substrate provided by the embodiment of the present application, the array substrate further includes a first support member disposed on a side of the planar layer away from the substrate. The first support member is located in an edge region of the second type of opening and is close to the contact hole in the second type of opening. A positive projection of the first support member on the substrate at least partially coincides with a positive projection of the color resist layer on the substrate.
[0023] In the array substrate provided by the embodiment of the present application, third type of contact holes are disposed in each of two adjacent second type of openings, and part of the first support member is located between the two adjacent third type of contact holes.
[0024] In the array substrate provided by the embodiment of the present application, the array substrate further includes a second support member disposed on a side of the planar layer away from the substrate. In a thickness direction of the array substrate, a height of the second support member is greater than a height of the first support member, and the height of the first support member is greater than a height of the flow guiding member.
[0025] In the array substrate provided by the embodiment of the present application, a boundary of the first support member facing the contact hole coincides with a part of a boundary of the contact hole.
[0026] In the array substrate provided by the embodiment of the present application, the color resist layer includes a first color resist block, a second color resist block, and a third color resist block that are sequentially adjacent to each other. One first type of opening and two second type of openings are provided on the third color resist block, and three second type of openings are provided on each of the first color resist block and the second color resist block;
[0027] Wherein, one third type of contact hole is provided in each of the two second type of openings on the third color resist block; among the three second type of openings on the first color resist block and the second color resist block, one second type of opening is provided with one second type of contact hole, and one third type of contact hole is provided in each of the other two second type of openings.
[0028] In the array substrate provided by the embodiment of the present application, the first color resist is a red color resist, the second color resist is a green color resist, and the third color resist is a blue color resist.
[0029] In the array substrate provided by the embodiment of the present application, the array substrate further includes a transparent conductive layer disposed on a side of the planar layer away from the substrate. The transparent conductive layer includes a plurality of pixel electrodes disposed at intervals. Each pixel electrode corresponds to a color resist block. The pixel electrode includes a main pixel electrode and a sub-pixel electrode disposed at intervals. The first type of opening and the second type of opening are both located between the main pixel electrode and the sub-pixel electrode;
[0030] The transparent conductive layer further includes a first bridging electrode located in the first contact hole, a second bridging electrode located in the second contact hole, a third bridging electrode located in the third contact hole, and a connection trace connecting the first bridging electrode and the second bridging electrode. A positive projection of the connection trace on the substrate is located within a positive projection of the flow guiding member on the substrate;
[0031] The driving circuit layer further includes a first transistor, a second transistor, and a third transistor disposed between the main pixel electrode and the sub-pixel electrode. The main pixel electrode is connected to the first transistor through one of the third bridging electrodes, the sub-pixel electrode is connected to the second transistor through the other third bridging electrode, and the second transistor and the third transistor are connected.
[0032] In the array substrate provided in the embodiment of the present application, the first metal layer forms a plurality of gate scan lines and a common electrode line located between two adjacent gate scan lines. The gate scan lines are located between the main pixel electrode and the sub-pixel electrode. The common electrode line includes a first common trace and a second common trace connected to each other. The first common trace is disposed around the main pixel electrode, and the second common trace is disposed around the sub-pixel electrode. The second metal layer forms a source and a drain of the first transistor, a source and a drain of the second transistor, and a source of the third transistor;
[0033] Wherein, the main pixel electrode is connected to the drain of the first transistor through one of the third bridging electrodes, the sub-pixel electrode is connected to the drain of the second transistor through the other third bridging electrode, the source of the third transistor is connected to the first common trace through the second bridging electrode, and the first bridging electrode is connected to the second common trace.
[0034] The embodiment of the present application further provides a display panel, which includes:
[0035] A counter substrate;
[0036] The array substrate as described in any one of the foregoing embodiments, and the array substrate is disposed opposite to the counter substrate.
[0037] The beneficial effects of the present application are as follows: In the array substrate and the display panel provided by the present application, the array substrate includes a driving circuit layer, a color resist layer, a planarization layer, and a flow guiding member disposed above the substrate. The color resist layer is provided with a plurality of openings, and part of the driving circuit layer is exposed through the openings. The planarization layer is provided with a plurality of contact holes, and the contact holes are located within the openings and expose part of the driving circuit layer. The flow guiding member is located within the openings and at the edge region of at least one of the contact holes, and the orthographic projection of the flow guiding member on the substrate is located within the orthographic projection of the corresponding opening on the substrate. Thus, by providing the flow guiding member at the edge region of the contact holes, the flow guiding member can disrupt the surface tension of the alignment liquid and improve the problem of the alignment liquid accumulating at the edge of the contact holes. Moreover, the flow guiding member is located within the openings of the color resist layer, and the orthographic projection of the flow guiding member is completely located within the orthographic projection of the openings of the color resist layer, so as to prevent the flow guiding member from standing on the color resist of the color resist layer and playing a supporting role, thereby affecting the surface pressure and taste of the product. Therefore, while improving the problem of the alignment liquid accumulating at the edge of the contact holes, it can also prevent the flow guiding member from playing a supporting role and affecting the surface pressure and taste of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.
[0039] Figure 1 Schematic plan view of a pixel structure is exemplified.
[0040] Figure 2 For Figure 1 Detail structure schematic diagram at M in
[0041] Figure 3 Partial plan view of the array substrate provided by the embodiment of the present application.
[0042] Figure 4 For Figure 3 Detail structure schematic diagram at N in
[0043] Figure 5 For Figure 3 Detail structure schematic diagram at O in
[0044] Figure 6 For Figure 4 Schematic cross-sectional structure diagram along the A-A' direction in
[0045] Figure 7 For Figure 4 Schematic cross-sectional structure diagram along the B-B' direction in
[0046] Figure 8 is Figure 3 a schematic plan view of the first metal layer within the third sub-pixel in
[0047] Figure 9 is Figure 3 a schematic plan view of the second metal layer within the third sub-pixel in
[0048] Figure 10 is Figure 3 a schematic plan view of the transparent conductive layer within the third sub-pixel in
[0049] Reference numerals:
[0050] 100, array substrate;
[0051] 10, substrate; 11, gate insulating layer; 12, interlayer insulating layer; 13, protective layer;
[0052] 20, driving circuit layer;
[0053] 21, first metal layer; SL, gate scanning line; GE1 / GE2 / GE3, gate; Com1, first common trace; Com2, second common trace;
[0054] 22, second metal layer; DL, data line; S1 / S2 / S3, source; D1 / D2 / D3, drain;
[0055] 30, color resist layer; 31, first color resist block; 32, second color resist block; 33, third color resist block; 301, opening; 301-1, first type of opening; 301-2, second type of opening; 302, connecting groove;
[0056] 40, planarization layer; 401, contact hole; 401-1, first type of contact hole; 401-2, second type of contact hole; 401-3, third type of contact hole; 4010, edge region;
[0057] 50, current guiding member; 51, first support member; 52, second support member;
[0058] 60, transparent conductive layer; 61, main pixel electrode; 62, sub-pixel electrode; 63, first bridging electrode; 64, second bridging electrode; 65, third bridging electrode; 66, connecting trace;
[0059] T1, first transistor; T2, second transistor; T3, third transistor;
[0060] R / R’, first sub-pixel; G / G’, second sub-pixel; B / B’, third sub-pixel;
[0061] X, the first direction; Y, the second direction. Detailed implementation manners
[0062] The descriptions of the following embodiments refer to the attached drawings, which are used to illustrate specific embodiments in which the present application can be implemented. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., only refer to the directions of the attached drawings. Therefore, the directional terms used are for explaining and understanding the present application, rather than for limiting the present application. In the drawings, units with similar structures are denoted by the same reference numerals. In the drawings, for clear understanding and easy description, the thicknesses of some layers and regions are exaggerated. That is, the sizes and thicknesses of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.
[0063] Regarding the problem of the accumulation of alignment liquid at the edge of the contact hole existing in the existing array substrate using the COA technology, the inventors of the present application found in the research that a diversion groove can be provided on the color resist layer of the array substrate to break the surface tension of the alignment liquid. Specifically, referring to Figure 1 and Figure 2 , Figure 1 illustrates a schematic plan view of a pixel structure. Figure 2 is Figure 1 a schematic detailed structure view of M in Figure 1 . As shown in Figure 2 , the first sub-pixel R’, the second sub-pixel G’, and the third sub-pixel B’ are arranged in sequence. Among them, the first sub-pixel R’ is a red sub-pixel, the second sub-pixel G’ is a green sub-pixel, and the third sub-pixel B’ is a blue sub-pixel. The color resist layer 30’ includes a red color resist block corresponding to the red sub-pixel, a green color resist block corresponding to the green sub-pixel, and a blue color resist block corresponding to the blue sub-pixel. Taking the third sub-pixel B’ as an example, as shown in
[0064] , the color resist layer 30’ is provided with a plurality of openings 301’ and diversion grooves 302’. Two adjacent openings 301’ are connected through the diversion groove 302’. The passivation layer is provided with a plurality of contact holes 401’. Each opening 301’ is provided with a contact hole 401’. The surface tension of the alignment liquid is broken through the diversion groove 302’, thereby improving the problem of the accumulation of the alignment liquid at the edge of the contact hole.
[0064] In order to meet more and more stringent application environments, the inventors found that the organic insulating film array (Polymer Film On Array, PFA) process can be used to replace the traditional inorganic passivation layer (Passivation, PV) process, thereby improving the taste and reliability. The PFA process effectively improves the planarization characteristics of the substrate surface by coating an organic insulating film with a thickness of about 1.3 μm (much thicker than 0.195 μm of the PV process), and at the same time enhances the moisture resistance and mechanical stress resistance, thereby greatly optimizing the reliability of the display panel.
[0065] However, in an array substrate with a Color Filter On Array (COA) structure, the application of the PFA process has introduced new technical challenges. Specifically, in the PV process, due to the relatively thin PV film thickness, the RGB color resist layer 30' can break the surface tension of the polyimide (PI) alignment liquid by designing diversion channels (such as micron-level trench structures), prompting the PI liquid to flow uniformly in the PV opening area and avoiding local accumulation. In the PFA process, however, the relatively thick organic insulating film requires the sizes of the deep and shallow contact holes to be increased synchronously to meet the reliability requirements of signal conduction. At the same time, the opening area of the color resist layer 30 is partially covered or filled due to the planarization effect of PFA, and the physical structure of the diversion channels is smoothed out, making it impossible to regulate the flow behavior of the PI liquid through the surface topography.
[0066] In this case, when the PI alignment liquid is coated, its high surface tension characteristics are particularly prominent in the wide contact hole area formed by the PFA process. Since the diversion channels are filled by PFA, the function of the diversion channels to break the surface tension of the PI alignment liquid is lost, making it difficult for the PI alignment liquid to effectively wet the sidewalls and bottom of the PFA contact holes. Instead, a large amount of the PI alignment liquid accumulates at the edges of the PFA contact holes. After pre-baking and curing, the accumulated PI alignment liquid forms an alignment film with uneven thickness in the display area, resulting in abnormal distribution of the pre-tilt angle of liquid crystal molecules. Finally, when the display panel is lit, it appears as regular diagonal Mura (non-uniform brightness or chromaticity).
[0067] Therefore, through further exploration and research, the inventor has proposed an array substrate 100 and a display panel to improve the problem of alignment liquid accumulation at the edges of contact holes existing in the array substrate 100 using the PFA and COA technologies.
[0068] Please refer to Figures 3 to 10 , Figure 3 which is a partial planar structure schematic diagram of the array substrate 100 provided by the embodiment of the present application, Figure 4 is Figure 3 a detailed structure schematic diagram of the N position in Figure 5 is Figure 3 a detailed structure schematic diagram of the O position in Figure 6 is Figure 4 a cross-sectional structure schematic diagram along the A-A' direction in Figure 7 is Figure 4 a cross-sectional structure schematic diagram along the B-B' direction in Figure 8 is Figure 3 a planar structure schematic diagram of the first metal layer 21 in the third sub-pixel B in Figure 9 is Figure 3 a planar structure schematic diagram of the second metal layer 22 in the third sub-pixel B in Figure 10 isFigure 3 Schematic plan view of the transparent conductive layer 60 in the third sub-pixel B. The array substrate 100 includes a substrate 10, and a driving circuit layer 20, a color resist layer 30, a planarization layer 40, and a current guiding member 50 disposed on the substrate 10.
[0069] The driving circuit layer 20 is disposed on one side of the substrate 10, the color resist layer 30 is disposed on a side of the driving circuit layer 20 away from the substrate 10, the color resist layer 30 is provided with a plurality of openings 301, the openings 301 expose a part of the driving circuit layer 20, the planarization layer 40 is disposed on a side of the color resist layer 30 away from the substrate 10, the planarization layer 40 is provided with a plurality of contact holes 401, the contact holes 401 are located within the openings and expose a part of the driving circuit layer 20, the current guiding member 50 is disposed on a side of the planarization layer 40 away from the substrate 10, the current guiding member 50 is located within the openings 301 and at the edge region 4010 of at least one of the contact holes 401, and a positive projection of the current guiding member 50 on the substrate 10 is located within a positive projection of the corresponding opening 301 on the substrate 10.
[0070] Thus, by disposing the current guiding member 50 at the edge region 4010 of the contact hole 401, the current guiding member 50 can break the surface tension of the alignment liquid and improve the problem of the alignment liquid accumulating at the edge of the contact hole. Moreover, the current guiding member 50 is located within the opening 301 of the color resist layer 30, and a positive projection of the current guiding member 50 is completely located within a positive projection of the opening 301 of the color resist layer 30, so as to prevent the current guiding member 50 from standing on the color resist of the color resist layer 30 and playing a supporting role, thereby affecting the surface pressure and taste of the product. Therefore, while improving the problem of the alignment liquid accumulating at the edge of the contact hole, it is also possible to prevent the current guiding member 50 from playing a supporting role and affecting the surface pressure and taste of the product.
[0071] Specifically, referring to Figure 3 , the array substrate 100 includes a plurality of sub-pixels disposed on the substrate 10, and the plurality of sub-pixels are arranged in sequence along a first direction X. The plurality of sub-pixels include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B, and the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged in sequence in the first direction X. The color resist layer 30 includes a first color resist block 31 corresponding to the first sub-pixel R, a second color resist block 32 corresponding to the second sub-pixel G, and a third color resist block 33 corresponding to the third sub-pixel B.
[0072] In some embodiments, the first sub-pixel R is a red sub-pixel, the second sub-pixel G is a green sub-pixel, and the third sub-pixel B is a blue sub-pixel. Correspondingly, the first color filter block 31 is a red color filter block, the second color filter block 32 is a green color filter block, and the third color filter block 33 is a blue color filter block. The color filter block can transmit light of a specific wavelength while filtering light of other wavelengths. For example, the red color filter block can transmit red light while filtering light of other colors, the green color filter block can transmit green light while filtering light of other colors, and the blue color filter block can transmit blue light while filtering light of other colors.
[0073] In some embodiments, referring to Figure 3 , Figure 4 and Figure 5 , the planar layer 40 is provided with a plurality of contact holes 401 in a first type of opening 301-1 among the plurality of openings 301. For example, the planar layer 40 is provided with two contact holes 401 in the first type of opening 301-1. The flow guide member 50 is located between two adjacent contact holes 401 in the first type of opening 301-1. That is, the flow guide member 50 is located in the first type of opening 301-1 and is located in the edge region 4010 of two adjacent contact holes 401 in the first type of opening 301-1. Optionally, the boundary of the flow guide member 50 facing the contact hole 401 coincides with a part of the boundary of the contact hole 401. That is, the flow guide member 50 is arranged tangentially to the boundary of the contact hole 401 to better guide the flow direction of the alignment liquid, so that the alignment liquid flows into the contact hole 401 and reduces the risk of the alignment liquid accumulating at the edge of the contact hole.
[0074] Specifically, referring to Figure 4 and Figure 5 , the two contact holes 401 located in the first type of opening 301-1 are a first type of contact hole 401-1 and a second type of contact hole 401-2. The first type of contact hole 401-1 and the second type of contact hole 401-2 are arranged at intervals in the second direction Y. The second direction Y is different from the first direction X, and the second direction Y intersects the first direction X at an angle. The range of this angle is greater than 0 degree and less than or equal to 90 degrees. For example, the second direction Y is perpendicular to the first direction X. The flow guide member 50 is located between the first type of contact hole 401-1 and the second type of contact hole 401-2. The boundary of the flow guide member 50 far from the first type of contact hole 401-1 coincides with the boundary of the second type of contact hole 401-2, and the boundary of the flow guide member 50 far from the second type of contact hole 401-2 coincides with the boundary of the first type of contact hole 401-1.
[0075] In some embodiments, continuing to refer to Figure 4 andFigure 5 The flat layer 40 is provided with one contact hole 401 in a second type of opening 301-2 among the plurality of openings. The opening size of the second type of opening 301-2 is smaller than the opening size of the first type of opening 301-1, where the opening size refers to the area of the opening. The contact hole 401 located in the second type of opening 301-2 is the second type of contact hole 401-2 or the third type of contact hole 401-3, and the aperture of the third type of contact hole 401-3 is smaller than the aperture of the second type of contact hole 401-2 and smaller than the aperture of the first type of contact hole 401-1. Herein, the aperture of the contact hole 401 refers to the area of the largest cross-section of the contact hole 401. Optionally, the color resist layer 30 further includes at least one communication groove 302, and the first type of opening 301-1 is communicated with the second type of opening 301-2 through the communication groove 302.
[0076] Specifically, referring to Figure 3 and Figure 4 , within the third sub-pixel B, the third color resist block 33 is provided with one first type of opening 301-1 and two second type of openings 301-2. One first type of contact hole 401-1 and one second type of contact hole 401-2 are provided in the first type of opening 301-1, and one third type of contact hole 401-3 is provided in each second type of opening 301-2. Within the first sub-pixel R and the second sub-pixel G, the first color resist block 31 and the second color resist block 32 are both provided with three second type of openings 301-2. One second type of contact hole 401-2 is provided in one of the second type of openings 301-2, and one third type of contact hole 401-3 is provided in each of the other two second type of openings 301-2.
[0077] In some embodiments, continue to refer to Figure 3 and Figure 4, the array substrate 100 further includes a first support member 51 disposed on a side of the planar layer 40 away from the substrate 10. The first support member 51 is located in an edge region of the second type of opening 301-2 and is close to the contact hole 401 within the second type of opening 301-2. For example, a boundary of the first support member 51 facing the contact hole 401 coincides with a partial boundary of the contact hole 401. A positive projection of the first support member 51 on the substrate 10 coincides with at least a part of a positive projection of the color resist layer 30 on the substrate 10. For example, one first support member 51 is disposed within a part of the third sub-pixel B, and the first support member 51 is located between two adjacent third type contact holes 401-3; two first support members 51 are disposed within the first sub-pixel R and the second sub-pixel G. One first support member 51 is located between two adjacent third type contact holes 401-3, and the other first support member 51 is located in an edge region of the second type contact hole 401-2 and is tangent to a boundary of the second type contact hole 401-2.
[0078] In some embodiments, referring to Figure 3 and Figure 5 , the array substrate 100 further includes a second support member 52 disposed on a side of the planar layer 40 away from the substrate 10. The second support member 52 is located within a part of the sub-pixels. For example, the second support member 52 is disposed within a part of the third sub-pixel B. The second support member 52 can be disposed in an edge region of the communication groove 302. For example, a boundary of the second support member 52 coincides with a partial boundary of the communication groove 302. In a thickness direction of the array substrate 100, a height of the second support member 52 is greater than a height of the first support member 51, and the height of the first support member 51 is greater than a height of the flow guiding member 50. Wherein, the first support member 51 and the second support member 52 are used to support a liquid crystal cell thickness, and the flow guiding member 50 is used to break a surface tension of an alignment liquid. The flow guiding member 50 does not participate in supporting the liquid crystal cell thickness to avoid affecting a surface pressure and taste of the display panel.
[0079] Optionally, the first support member 51 and the second support member 52 are made of the same material. For example, the material of the first support member 51 includes an organic photoresist and the like. The flow guiding member 50 is made of the same material as the first support member 51, so that the flow guiding member 50, the first support member 51, and the second support member 52 are formed under the same manufacturing process to simplify the process.
[0080] In some embodiments, the maximum cross-sectional area of the flow guide member 50 is smaller than the maximum cross-sectional area of the second support member 52, and the maximum cross-sectional area of the second support member 52 is smaller than the maximum cross-sectional area of the first support member 51, so that the flow guide member 50 is significantly different from the first support member 51 and the second support member 52, thereby increasing the size difference between the flow guide member 50 and the first support member 51 and the second support member 52, and preventing mis-capture in machine platform monitoring and measurement. At the same time, the maximum cross-sectional area of the flow guide member 50 cannot be too small to avoid reducing the effect of the flow guide member 50 in improving the accumulation of the alignment liquid at the edge of the contact hole, and to avoid film layer separation between the flow guide member 50 and the planarization layer 40 due to the flow guide member 50 being too small.
[0081] Referring to Figure 6 and Figure 7 , the driving circuit layer 20 includes a first metal layer 21 and a second metal layer 22, and the second metal layer 22 is located between the first metal layer 21 and the color resist layer 30. Specifically, the first metal layer 21 is disposed on the substrate 10, and the second metal layer 22 is disposed on a side of the first metal layer 21 away from the substrate 10. A plurality of insulating layers are provided between the first metal layer 21 and the second metal layer 22, such as a gate insulating layer 11 covering the first metal layer 21 and the substrate 10, and an interlayer insulating layer 12 covering the gate insulating layer 11, and the first metal layer 21 is disposed on the interlayer insulating layer 12. Optionally, a protective layer 13 is further provided between the second metal layer 22 and the color resist layer 30, and the protective layer 13 covers the second metal layer 22 and the interlayer insulating layer 12. The materials of the first metal layer 21 and the second metal layer 22 include single layers or stacked layers formed of conductive metals such as copper, aluminum, titanium, molybdenum or their combinations.
[0082] Referring to Figure 6 , the color resist layer 30 is disposed on a side of the second metal layer 22 away from the first metal layer 21. The color resist layer 30 is provided with a plurality of openings 301, and each opening 301 penetrates through the color resist layer 30, so that the color resist layer 30 forms a color resist portion surrounding the opening 301, that is, the color resist portion is the main body portion of the color resist layer 30 except for the opening 301. For example, the third color resist block 33 of the color resist layer 30 is provided with a plurality of the second type of openings 301-2, and the second type of openings 301-2 penetrate through the third color resist block 33, so that the third color resist block 33 forms a color resist portion surrounding the second type of openings 301-2.
[0083] Continuing to refer to Figure 6, the flat layer 40 is disposed on a side of the color resist layer 30 away from the second metal layer 22. The flat layer 40 covers the color resist layer 30 and the opening 301 on the color resist layer 30 to flatten the surface of the color resist layer 30. For example, the flat layer 40 covers the second type of opening 301-2 on the third color resist block 33 to fill the second type of opening 301-2. The flat layer 40 is formed by a Polymer Film On Array (PFA) process.
[0084] The flat layer 40 is provided with contact holes 401 corresponding to the openings 301 of the color resist layer 30. The contact holes 401 are located within the openings 301, and the orthographic projection of the contact holes 401 on the substrate 10 is located within the orthographic projection of the openings 301 on the substrate 10. For example, the flat layer 40 is provided with third type of contact holes 401-3 at positions corresponding to the second type of openings 301-2. The third type of contact holes 401-3 are located within the second type of openings 301-2, and the third type of contact holes 401-3 penetrate through the flat layer 40 to expose a part of the second metal layer 22.
[0085] The third type of contact holes 401-3 are provided in two adjacent second type of openings 301-2, and a part of the first support member 51 is located between the two adjacent third type of contact holes 401-3. The first support member 51 is disposed between the two adjacent third type of contact holes 401-3 to break the surface tension of the alignment liquid so that the alignment liquid can flow into the third type of contact holes 401-3 and prevent the alignment liquid from accumulating at the edges of the third type of contact holes 401-3. The first support member 51 is located on the color resist portion of the color resist layer 30, that is, the orthographic projection of the first support member 51 on the substrate 10 partially overlaps with the orthographic projection of the main body portion of the color resist layer 30 on the substrate 10.
[0086] Refer to Figure 7 , the third color resist block 33 of the color resist layer 30 is further provided with a first type of opening 301-1. The flat layer 40 is provided with a first type of contact hole 401-1 and a second type of contact hole 401-2 corresponding to the first type of opening 301-1. The first type of contact hole 401-1 and the second type of contact hole 401-2 are both located within the first type of opening 301-1. The orthographic projection of the first type of contact hole 401-1 on the substrate 10 is located within the orthographic projection of the first type of opening 301-1 on the substrate 10, and the orthographic projection of the second type of contact hole 401-2 on the substrate 10 is located within the orthographic projection of the first type of opening 301-1 on the substrate 10.
[0087] The first type of contact hole 401-1 exposes a part of the first metal layer 21, and the second type of contact hole 401-2 exposes a part of the first metal layer 21 and a part of the second metal layer 22; the plurality of contact holes 401 in the first type of opening 301-1 include the first type of contact hole 401-1 and the second type of contact hole 401-2.
[0088] The flow guide member 50 is located between the first type of contact hole 401-1 and the second type of contact hole 401-2 to break the surface tension of the alignment liquid so that the alignment liquid can flow into the first type of contact hole 401-1 and the second type of contact hole 401-2, and prevent the alignment liquid from accumulating at the edges of the first type of contact hole 401-1 and the second type of contact hole 401-2. The flow guide member 50 is located in the opening 301 of the color resist layer 30, and the orthographic projection of the flow guide member 50 on the substrate 10 is located within the orthographic projection of the opening 301 on the substrate 10, so that the flow guide member 50 is completely located within the opening 301 of the color resist layer 30, that is, there is no overlapping part between the orthographic projection of the first support member 51 on the substrate 10 and the orthographic projection of the main body part of the color resist layer 30 on the substrate 10, to prevent the flow guide member 50 from being disposed above the main body part of the color resist layer 30 and playing a role in supporting the cell gap, thereby preventing the setting of the flow guide member 50 from affecting the surface pressure and taste of the product.
[0089] In some embodiments, the planarization layer 40 is further provided with the second type of contact hole 401-2 corresponding to the second type of opening 301-2. The second type of contact hole 401-2 is located within the second type of opening 301-2, and the orthographic projection of the second type of contact hole 401-2 on the substrate 10 is located within the orthographic projection of the second type of opening 301-2 on the substrate 10. A part of the first support member 51 is disposed in the edge region of the second type of contact hole 401-2 to break the surface tension of the alignment liquid so that the alignment liquid can flow into the second type of contact hole 401-2, and prevent the alignment liquid from accumulating at the edge of the second type of contact hole 401-2. The first support member 51 is located on the color resist portion of the color resist layer 30, that is, there is a partial overlap between the orthographic projection of the first support member 51 on the substrate 10 and the orthographic projection of the main body part of the color resist layer 30 on the substrate 10.
[0090] Continue to refer to Figures 3 to 10, in some embodiments, one first - type opening 301 - 1 and two second - type openings 301 - 2 are provided on the third - color color - resist block 33, and three second - type openings 301 - 2 are provided on each of the first - color color - resist block 31 and the second - color color - resist block 32. One third - type contact hole 401 - 3 is provided in each of the two second - type openings 301 - 2 on the third - color color - resist block 33; among the three second - type openings 301 - 2 on the first - color color - resist block 31 and the second - color color - resist block 32, one second - type contact hole 401 - 2 is provided in one second - type opening 301 - 2, and one third - type contact hole 401 - 3 is provided in each of the other two second - type openings 301 - 2.
[0091] Referring to Figure 3 and Figure 10 , the array substrate 100 further includes a transparent conductive layer 60 disposed on the side of the planarization layer 40 away from the substrate 10. The material of the transparent conductive layer 60 includes transparent conductive materials such as indium tin oxide (ITO). The transparent conductive layer 60 includes a plurality of pixel electrodes disposed at intervals, each pixel electrode corresponding to a color - resist block. The pixel electrode includes a main pixel electrode 61 and a sub - pixel electrode 62 disposed at intervals, and both the first - type opening 301 - 1 and the second - type opening 301 - 2 are located between the main pixel electrode 61 and the sub - pixel electrode 62.
[0092] Referring to Figure 6 , Figure 7 and Figure 10 , the transparent conductive layer 60 further includes a first bridging electrode 63 located in the first contact hole, a second bridging electrode 64 located in the second contact hole, a third bridging electrode 65 located in the third contact hole, and a connection trace 66 connecting the first bridging electrode 63 and the second bridging electrode 64. The orthographic projection of the connection trace 66 on the substrate 10 is located within the orthographic projection of the flow - guiding member 50 on the substrate 10.
[0093] Referring to Figure 8 , Figure 9 and Figure 10 , the driving - circuit layer 20 further includes a first transistor T1, a second transistor T2, and a third transistor T3 disposed between the main pixel electrode 61 and the sub - pixel electrode 62. The main pixel electrode 61 is connected to the first transistor T1 through one third - bridging electrode 65, the sub - pixel electrode 62 is connected to the second transistor T2 through another third - bridging electrode 65, and the second transistor T2 and the third transistor T3 are connected.
[0094] The first metal layer 21 is formed with a plurality of gate scan lines SL and common electrode lines located between two adjacent gate scan lines SL. The gate scan lines SL are located between the main pixel electrode 61 and the sub-pixel electrode 62. The common electrode lines include a first common trace Com1 and a second common trace Com2 that are connected to each other. The first common trace Com1 is disposed around the main pixel electrode 61, and the second common trace Com2 is disposed around the sub-pixel electrode 62. Of course, the first metal layer 21 is further formed with a gate GE1 of the first transistor T1, a gate GE2 of the second transistor T2, and a gate GE3 of the third transistor T3. The gate GE1 of the first transistor T1, the gate GE2 of the second transistor T2, and the gate GE3 of the third transistor T3 are all connected to the gate scan line SL. For example, the gate GE1 of the first transistor T1, the gate GE2 of the second transistor T2, and the gate GE3 of the third transistor T3 are integrally provided with the gate scan line SL.
[0095] The second metal layer 22 is formed with a source S1 and a drain D1 of the first transistor T1, a source S2 and a drain D2 of the second transistor T2, and a source S3 and a drain D3 of the third transistor T3. Of course, the second metal layer 22 may further be formed with a data line DL, and the data line DL is connected to the source S1 of the first transistor T1 and the source S2 of the second transistor T2.
[0096] The main pixel electrode 61 is connected to the drain D1 of the first transistor T1 through one of the third bridging electrodes 65. The sub-pixel electrode 62 is connected to the drain D2 of the second transistor T2 through another third bridging electrode 65. The source S3 of the third transistor T3 is connected to the first common trace Com1 through the second bridging electrode 64. The first bridging electrode 63 is connected to the second common trace Com2, so that the first common trace Com1 is sequentially connected to the second common trace Com2 through the second bridging electrode 64, the connection trace 66, and the first bridging electrode 63, thereby realizing a grid-like design of the common electrode line on the entire surface of the array substrate 100, and improving the uniformity of the signal of the common electrode line on the entire surface.
[0097] Based on the same inventive concept, the present application further provides a display panel. The display panel includes a counter substrate and an array substrate 100 disposed opposite to the counter substrate. The array substrate 100 is the array substrate 100 described in one of the foregoing embodiments. The display panel is a liquid crystal display panel.
[0098] According to the above embodiments, it can be known that:
[0099] In an array substrate and a display panel provided by the present application, the array substrate includes a driving circuit layer, a color resist layer, a planarization layer, and a flow guide member disposed above a substrate. The color resist layer is provided with a plurality of openings that expose a part of the driving circuit layer. The planarization layer is provided with a plurality of contact holes that are located within the openings and expose a part of the driving circuit layer. The flow guide member is located within the openings and at the edge region of at least one of the contact holes. A positive projection of the flow guide member on the substrate is located within a positive projection of the corresponding opening on the substrate. Thus, by providing the flow guide member at the edge region of the contact hole, the flow guide member can break the surface tension of the alignment liquid and improve the problem of the alignment liquid accumulating at the edge of the contact hole. Moreover, the flow guide member is located within the opening of the color resist layer, and a positive projection of the flow guide member is completely located within a positive projection of the opening of the color resist layer, so as to prevent the flow guide member from standing on the color resist of the color resist layer and playing a supporting role, thereby affecting the surface pressure and taste of the product. Therefore, while improving the accumulation of the alignment liquid at the edge of the contact hole, it is also possible to prevent the flow guide member from playing a supporting role and affecting the surface pressure and taste of the product.
[0100] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.
[0101] The above has introduced the embodiments of the present application in detail. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. An array substrate, characterized in that: include: substrate; A driving circuit layer is arranged on one side of the substrate; A color resist layer is arranged on a side of the driving circuit layer away from the substrate, the color resist layer is provided with a plurality of openings, and the openings expose a portion of the driving circuit layer; A planar layer, disposed on a side of the color resist layer away from the substrate, the planar layer being provided with a plurality of contact holes, the contact holes being located in the opening and exposing a portion of the driving circuit layer; A flow guide, disposed on a side of the planar layer away from the substrate, the flow guide being located in the opening and in an edge region of at least one of the contact holes; The orthographic projection of the flow guide on the substrate is located within the orthographic projection of the corresponding opening on the substrate.
2. The array substrate according to claim 1, characterized in that: The planar layer is provided with a plurality of the contact holes in a first type of openings among the plurality of the openings, and the flow guide is located between two adjacent contact holes in the first type of openings.
3. The array substrate according to claim 2, characterized in that: A boundary of the flow guide member facing the contact hole coincides with a portion of a boundary of the contact hole.
4. The array substrate according to claim 2, characterized in that: The driving circuit layer includes a first metal layer and a second metal layer, and the second metal layer is located between the first metal layer and the color resist layer; A first type of contact hole among the plurality of contact holes exposes a portion of the first metal layer, and a second type of contact hole among the plurality of contact holes exposes a portion of the first metal layer and a portion of the second metal layer; The plurality of contact holes in the first type of openings include the first type of contact holes and the second type of contact holes.
5. The array substrate according to claim 4, characterized in that: The planar layer is provided with one of the contact holes in a second type of opening among the plurality of openings; The third type of contact hole among the multiple contact holes exposes part of the second metal layer, the second type of contact hole or the third type of contact hole is arranged in the second type of opening, and the aperture of the third type of contact hole is smaller than the aperture of the second type of contact hole and smaller than the aperture of the first type of contact hole.
6. The array substrate according to claim 5, characterized in that: The color resist layer further includes at least one connecting groove, and the first type of openings are connected with the second type of openings through the connecting groove.
7. The array substrate according to claim 5, characterized in that: The array substrate also includes a first support member arranged on a side of the flat layer away from the substrate, the first support member is located in an edge area of the second type of opening and close to the contact hole in the second type of opening, and the orthographic projection of the first support member on the substrate at least partially overlaps with the orthographic projection of the color resist layer on the substrate.
8. The array substrate according to claim 7, characterized in that: The third type contact hole is disposed in each of two adjacent second type openings, and part of the first support member is located between the two adjacent third type contact holes.
9. The array substrate according to claim 7, characterized in that: The array substrate further comprises a second support member arranged on a side of the planar layer away from the substrate, wherein in the thickness direction of the array substrate, the height of the second support member is greater than the height of the first support member, and the height of the first support member is greater than the height of the guide member.
10. The array substrate according to claim 7, characterized in that: A boundary of the first support member facing the contact hole coincides with a portion of a boundary of the contact hole.
11. The array substrate according to claim 6, characterized in that: The color resist layer comprises a first color resist block, a second color resist block and a third color resist block which are arranged adjacent to each other in sequence, the third color resist block is provided with one first-type opening and two second-type openings, and the first color resist block and the second color resist block are both provided with three second-type openings; Among them, each of the two second-type openings on the third color resist block has a third-type contact hole; among the three second-type openings on the first color resist block and the second color resist block, one of the second-type openings has a second-type contact hole, and the other two second-type openings have a third-type contact hole.
12. The array substrate according to claim 11, characterized in that: The first color resist is a red color resist, the second color resist is a green color resist, and the third color resist is a blue color resist.
13. The array substrate according to claim 11, characterized in that: The array substrate further comprises a transparent conductive layer disposed on a side of the flat layer away from the substrate, the transparent conductive layer comprises a plurality of pixel electrodes disposed at intervals, each of the pixel electrodes corresponds to a color resist block, the pixel electrodes comprise a primary pixel electrode and a secondary pixel electrode disposed at intervals, and the first type of opening and the second type of opening are both located between the primary pixel electrode and the secondary pixel electrode; The transparent conductive layer further includes a first bridge electrode located in the first contact hole, a second bridge electrode located in the second contact hole, a third bridge electrode located in the third contact hole, and a connecting wire connecting the first bridge electrode and the second bridge electrode, wherein the orthographic projection of the connecting wire on the substrate is located within the orthographic projection of the flow guide on the substrate; The driving circuit layer also includes a first transistor, a second transistor and a third transistor arranged between the main pixel electrode and the sub-pixel electrode, the main pixel electrode is connected to the first transistor through one of the third bridge electrodes, the sub-pixel electrode is connected to the second transistor through another of the third bridge electrodes, and the second transistor is connected to the third transistor.
14. The array substrate according to claim 13, characterized in that: The first metal layer is formed with a plurality of gate scanning lines and a common electrode line located between two adjacent gate scanning lines, the gate scanning line is located between the primary pixel electrode and the secondary pixel electrode, the common electrode line includes a first common wiring and a second common wiring connected to each other, the first common wiring is arranged around the primary pixel electrode, and the second common wiring is arranged around the secondary pixel electrode, and the second metal layer is formed with a source and a drain of the first transistor, a source and a drain of the second transistor, and a source of the third transistor; Among them, the main pixel electrode is connected to the drain of the first transistor through one of the third bridge electrodes, the sub-pixel electrode is connected to the drain of the second transistor through another of the third bridge electrodes, the source of the third transistor is connected to the first common wiring through the second bridge electrode, and the first bridge electrode is connected to the second common wiring.
15. A display panel, characterized in that: include: an opposing substrate; The array substrate according to any one of claims 1 to 14, wherein the array substrate is arranged opposite to the counter substrate.