Driving circuit

Abstract

A drive circuit uses a two-level trigger scheme. The driving circuit includes a P stage in which a transistor configured to receive a start signal is a P-channel transistor and an N stage in which a transistor configured to receive a start signal is an N-channel transistor, where each of the P stage and the N stage includes a first transistor, a second transistor, an inverter, a pull-down transistor, and a pull-up transistor, and wherein the N stages are arranged at specific intervals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0182946, filed on December 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a driving circuit and a display device including the driving circuit. Background Art

[0004] The driving circuit includes a plurality of stages connected to a signal line. In response to a signal received from a controller, the plurality of stages supply an output signal to the signal line connected to the plurality of stages. Summary of the Invention

[0005] One or more embodiments include a driving circuit having a small size and configured to stably output an output signal, and a display device including the driving circuit. Technical aspects achieved by the present disclosure are not limited to the above aspects, and other technical aspects not mentioned herein will be clearly understood by those skilled in the art from the description of the present disclosure.

[0006] Additional aspects will be partially described below, and will be partially apparent from the description, or may be learned by practicing the presented embodiments of the present disclosure.

[0007] According to one or more embodiments, a driving circuit includes: a pair of first stages and a pair of second stages alternately arranged, wherein each of the pair of first stages and the pair of second stages includes: a first transistor connected between a first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; an inverter connected between the second terminal and a third terminal to which a second voltage is supplied, the inverter being configured to control the voltage of a third node to become a voltage obtained by inverting the voltage level of the first node or the voltage level of the second node; a pull-down transistor connected between an output terminal and the second terminal, the pull-down transistor including a gate connected to the second node; and a pull-up transistor connected between the third terminal and the output terminal, the pull-up transistor including a gate connected to the third node. The first transistor of each of the pair of first stages is a P-channel transistor, and the first transistor of each of the pair of second stages is an N-channel transistor.

[0008] In an embodiment, the second voltage may be greater than the first voltage.

[0009] In an embodiment, the clock signal may include a first clock signal and a second clock signal. The first clock signal may be input to the clock terminals of the odd-numbered first stages among the pair of first stages and the clock terminals of the odd-numbered second stages among the pair of second stages. The second clock signal may be input to the clock terminals of the even-numbered first stages among the pair of first stages and the clock terminals of the even-numbered second stages among the pair of second stages, and the second clock signal may be phase-shifted by 1 / 4 of a cycle with respect to the first clock signal.

[0010] In an embodiment, the inverter of each stage among the pair of first stages and the pair of second stages may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node.

[0011] In an embodiment, the inverter of each stage among the pair of first stages may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the first node.

[0012] In an embodiment, the fourth transistor of each stage among the pair of first stages may further include a back gate connected to the second node.

[0013] In an embodiment, each stage among the pair of first stages may further include a fifth transistor connected between the third terminal and the first node, the fifth transistor including a gate connected to a reset terminal.

[0014] In an embodiment, the inverter of each stage among the pair of second stages may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the second node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node.

[0015] In an embodiment, the first transistor of each stage among the pair of second stages may include a pair of serially connected sub-transistors.

[0016] In an embodiment, the pair of serially-connected sub-transistors may include a first sub-transistor and a second sub-transistor. The first sub-transistor may further include a back gate configured to receive the voltage of the second node of the previous stage, and the second sub-transistor may further include a back gate configured to receive the voltage of the second node of the current stage.

[0017] In an embodiment, the inverter of each stage of the pair of second stages may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node, and the first transistor of each stage of the pair of second stages may include a pair of serially-connected sub-transistors.

[0018] In an embodiment, the pair of serially-connected sub-transistors may include a first sub-transistor and a second sub-transistor. The first sub-transistor may further include a back gate configured to receive the voltage of the second node of the previous stage, and the second sub-transistor may further include a back gate configured to receive the voltage of the second node of the current stage.

[0019] According to one or more embodiments, a driving circuit includes: a first stage and a second stage arranged alternately, wherein each of the first stage and the second stage includes: a first transistor connected between a first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; an inverter connected between the second terminal and a third terminal to which a second voltage is supplied, the inverter being configured to control the voltage of a third node to be a voltage obtained by inverting the voltage level of the first node or the voltage level of the second node; a pull-down transistor connected between an output terminal and the second terminal, the pull-down transistor including a gate connected to the second node; and a pull-up transistor connected between the third terminal and the output terminal, the pull-up transistor including a gate connected to the third node. The first transistor of the first stage is a P-channel transistor, and the first transistor of the second stage is an N-channel transistor.

[0020] In an embodiment, the second voltage may be greater than the first voltage.

[0021] In an embodiment, the drive circuit may be configured to repeat a first stage group and a second stage group. Each of the first stage group and the second stage group may include an odd-numbered first stage and an even-numbered second stage. The clock signal may include a first clock signal and a second clock signal. The first clock signal may be input to the clock terminals of the odd-numbered first stages in the first stage group and the clock terminals of the even-numbered second stages in the first stage group. The second clock signal may be input to the clock terminals of the odd-numbered first stages in the second stage group and the clock terminals of the even-numbered second stages in the second stage group, and the second clock signal may be phase-shifted by 1 / 2 a cycle relative to the first clock signal.

[0022] In an embodiment, the inverter of each of the first stage and the second stage may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node.

[0023] In an embodiment, the inverter of the first stage may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the first node.

[0024] In an embodiment, the fourth transistor of the first stage may further include a back gate connected to the second node.

[0025] In an embodiment, the first stage may further include a fifth transistor connected between the third terminal and the first node, the fifth transistor including a gate connected to a reset terminal.

[0026] In an embodiment, the inverter of the second stage may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the second node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node.

[0027] In an embodiment, the first transistor of the second stage may include a pair of serially connected sub-transistors.

[0028] In an embodiment, the pair of serially-connected sub-transistors may include a first sub-transistor and a second sub-transistor. The first sub-transistor may further include a back gate configured to receive the voltage of the second node of a previous stage, and the second sub-transistor may further include a back gate configured to receive the voltage of the second node of the current stage.

[0029] In an embodiment, the inverter of the second stage may include: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node, and the first transistor of the second stage includes a pair of serially-connected sub-transistors.

[0030] In an embodiment, the pair of serially-connected sub-transistors may include a first sub-transistor and a second sub-transistor. The first sub-transistor may further include a back gate configured to receive the voltage of the second node of a previous stage, and the second sub-transistor may further include a back gate configured to receive the voltage of the second node of the current stage.

[0031] In an embodiment, the clock signal input to the clock terminal of the first stage and the clock signal input to the clock terminal of the second stage may be the same as each other.

[0032] According to one or more embodiments, a driving circuit includes a plurality of stages. Among them, the first stage of the plurality of stages includes: a first transistor connected between a first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a first clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; a third transistor connected between a third node and a third terminal to which a second voltage higher than the first voltage is supplied, the third transistor including a gate connected to the first node; a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the first node; a fifth transistor connected between a first output terminal and the second terminal, the fifth transistor including a gate connected to the second node; a sixth transistor connected between the third terminal and the first output terminal, the sixth transistor including a gate connected to the third node; and a seventh transistor connected between the third terminal and the first node, the seventh transistor including a gate connected to a reset terminal. The third transistor is a P-channel transistor, and the fourth transistor is an N-channel transistor.

[0033] In an embodiment, among the plurality of stages, a second stage sequentially connected to the first stage may include: an eighth transistor connected between a fourth node and a fourth terminal to which an output signal output from the first stage is input, the eighth transistor including a gate connected to a second clock terminal to which a clock signal is input; a ninth transistor connected between the fourth node and a fifth node, the ninth transistor including a gate connected to a fifth terminal to which the first voltage is supplied; a tenth transistor connected between a sixth node and a sixth terminal to which the second voltage is supplied, the tenth transistor including a gate connected to the fifth node; an eleventh transistor connected between the sixth node and the fifth terminal, the eleventh transistor including a gate connected to the fifth node; a twelfth transistor connected between a second output terminal and the fifth terminal, the twelfth transistor including a gate connected to the fifth node; and a thirteenth transistor connected between the sixth terminal and the second output terminal, the thirteenth transistor including a gate connected to the sixth node. The tenth transistor may be a P-channel transistor, and the eleventh transistor may be an N-channel transistor.

[0034] In an embodiment, the eighth transistor may include a pair of serially connected sub-transistors, the pair of serially connected sub-transistors may include a first sub-transistor and a second sub-transistor, the first sub-transistor may further include a back gate configured to receive a voltage of the second node of the first stage, and the second sub-transistor may further include a back gate configured to receive a voltage of the fifth node of the second stage.

[0035] In an embodiment, the first stage may further include: a first capacitor connected between the second node and the first output terminal; and a second capacitor connected between the third terminal and the third node. The second stage may further include: a third capacitor connected between the fifth node and the second output terminal; and a fourth capacitor connected between the sixth terminal and the sixth node.

[0036] In an embodiment, the first transistor may be a P-channel transistor, and the eighth transistor may be an N-channel transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects, features, and advantages of embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a schematic diagram of a driving circuit according to an embodiment;

[0039] Figure 2Schematic diagram (timing diagram) of the input signal and output signal of the drive circuit according to an embodiment;

[0040] Figure 3 is Figure 1 Diagram of any stage group among multiple stages included in the drive circuit of;

[0041] Figure 4 Shows Figure 3 Circuit diagram of an example of the P stage among the stage groups in;

[0042] Figure 5 Shows Figure 3 Circuit diagram of an example of the N stage among the stage groups in;

[0043] Figure 6 Is used to describe Figure 3 Timing diagram of the drive of the stage group of;

[0044] Figure 7 Diagram of the P stage according to another embodiment;

[0045] Figures 8 to 10 Diagram of the N stage according to other embodiments;

[0046] Figures 11 to 25 Diagram of the stage group of the drive circuit according to other embodiments;

[0047] Fig.26 Schematic diagram of the drive circuit according to another embodiment;

[0048] Fig. 27 is Fig.26 Diagram of any stage group among multiple stages included in the drive circuit of;

[0049] Fig.28 Shows Fig. 27 Circuit diagram of an example of the P stage among the stage groups in;

[0050] Fig.29 and Fig.30 Shows Fig. 27 Circuit diagram of an example of the N stage among the stage groups in;

[0051] Figure 31 to Figure 37 Diagram of the stage group of the drive circuit according to other embodiments;

[0052] Fig.38 Schematic diagram of the drive circuit according to yet another embodiment;

[0053] Fig.39 is Fig.38 Diagram of any stage group among multiple stages included in the drive circuit of;

[0054] Fig.40is a timing diagram for describing the driving of Fig.39 a stage group;

[0055] Figures 41 to 55 is a diagram of a stage group of a driving circuit according to other embodiments;

[0056] Fig.56 is a schematic diagram of a driving circuit according to yet another embodiment;

[0057] Figure 57 to Figure 64 is Fig.56 a diagram of any stage group among multiple stages included in the driving circuit of

[0058] Fig.65 is a schematic diagram of a driving circuit according to yet another embodiment;

[0059] Fig.66 is Fig.65 a diagram of any stage group among multiple stages included in the driving circuit of

[0060] Fig.67 is a timing diagram for describing the driving of Fig.66 a stage group;

[0061] Figures 68 to 82 is a diagram of a stage group of a driving circuit according to other embodiments;

[0062] Fig.83 is a schematic diagram of a driving circuit according to yet another embodiment;

[0063] Figures 84 to 91 is Fig.83 a diagram of any stage group among multiple stages included in the driving circuit of

[0064] Fig.92 is a diagram of a clock signal according to an embodiment; and

[0065] Fig.93 is a schematic diagram of a display device according to an embodiment. DETAILED DESCRIPTION

[0066] Now, embodiments will be described in detail with reference to examples shown in the accompanying drawings, in which like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described only by referring to the accompanying drawings to illustrate aspects of the present specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0067] Since various modifications can be applied and one or more embodiments can be implemented, specific embodiments will be shown in the drawings and described in the detailed description. The effects and features, as well as the methods for achieving these effects and features, will be clarified with reference to the embodiments described in detail below with reference to the drawings. However, the embodiments can have different forms and should not be construed as limited to the descriptions set forth herein.

[0068] It will be understood that although the terms "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms, and these terms are only used to distinguish one element from another.

[0069] In the following embodiments, unless the context clearly indicates otherwise, the singular forms include the plural forms.

[0070] It will be understood that the terms "comprising", "including" and "having" used herein indicate the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0071] For ease of description, the dimensions of the elements in the drawings may be exaggerated. In addition, since the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0072] The expression "A and / or B" used herein means A, B, or A and B. Additionally, the expression "at least one (kind / type / party) of A and B" means A, B, or A and B.

[0073] In the following embodiments, when X and Y are connected to each other, this can include the case where X and Y are physically connected to each other, the case where X and Y are functionally connected to each other, and the case where X and Y are electrically connected to each other. Additionally, when X and Y are connected to each other, this can include the case where X and Y are directly connected to each other, and the case where X and Y are indirectly connected and another element is interposed between X and Y. In this regard, X and Y can be elements (such as, for example, devices, components, circuits, wirings, electrodes, terminals, films, layers, or regions, etc.).

[0074] For example, when X and Y are electrically connected to each other, this can include the case where X and Y are directly electrically connected to each other and / or the case where X and Y are indirectly electrically connected and another element is interposed between X and Y. When X and Y are indirectly electrically connected, this can include the case where one or more elements (such as, for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) capable of achieving the electrical connection between X and Y are connected between X and Y. Therefore, this is not limited to certain connection relationships (such as the connection relationships shown in the drawings or in the detailed description), and can also include connection relationships other than those shown in the drawings or in the detailed description.

[0075] In the following embodiments, the term "ON" used in relation to the state of an element may refer to the activated state of the element, and "OFF" may refer to the disabled state of the element. The term "ON" used in relation to a signal received by an element may refer to a signal that activates the element, and "OFF" may refer to a signal that disables the element. An element may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-channel and N-channel transistors are at opposite (low-to-high) voltage levels. Hereinafter, the voltage that activates (turns on) a transistor is referred to as the gate turn-on voltage, and the voltage that disables (turns off) the transistor is referred to as the gate turn-off voltage.

[0076] Figure 1 is a schematic diagram of a drive circuit DRV according to an embodiment. Figure 2 is a schematic diagram (timing diagram) of input and output signals of a drive circuit according to an embodiment. Figure 3 is Figure 1 a diagram of any group of stages among the multiple stages included in the drive circuit DRV of Figure 4 is a diagram showing Figure 3 an example of a P-stage PST among the groups of stages in Figure 5 is a diagram showing Figure 3 an example of an N-stage NST among the groups of stages in Figure 6 is for describing Figure 3 the driving of a group of stages in

[0077] Referring to Figures 1 to 6 and also referring to Fig.93 according to an embodiment, the drive circuit DRV may include multiple stages ST1 to STn. The multiple stages ST1 to STn may be configured to sequentially output output signals OUT[1], ……, OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k], ……, and OUT[n] to signal lines, respectively.

[0078] The stages ST1 to STn may be respectively connected to the signal lines. Each of the stages ST1 to STn may be configured to: receive at least one clock signal and at least one voltage signal, generate an output signal OUT, and output the output signal OUT to the connected signal line.

[0079] Multiple stages ST1 to STn can be configured to output output signals OUT[1], ……, OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k], ……, and OUT[n] respectively in response to a start signal STV. For example, the nth stage STn can be configured to output the nth output signal OUT[n] to the nth signal line. An external signal FLM of the start signal STV for controlling the timing of the first output signal OUT[1] can be supplied to the first stage ST1.

[0080] The stages ST1 to STn can each include a plurality of terminals, and a plurality of signals are input to the plurality of terminals. The plurality of signals can include a clock signal and a voltage signal. The plurality of terminals can include an input terminal IN, a first voltage input terminal V1, a second voltage input terminal V2, a clock terminal CK, and an output terminal GOUT.

[0081] The start signal STV can be input (supplied) to the input terminal IN. The start signal STV can include an external signal FLM or carry signals CR[1], ……, CR[k - 3], CR[k - 2], CR[k - 1], CR[k], ……, or CR[n - 1]. In an embodiment, the carry signals CR[1], ……, CR[k - 3], CR[k - 2], CR[k - 1], CR[k], ……, or CR[n - 1] can be output signals from a previous stage (hereinafter referred to as previous output signals). The external signal FLM can be input as the start signal STV to the input terminal IN of the first stage ST1, and the previous output signal can be input as the start signal STV to the input terminal IN of each of the second to nth stages STn. The previous stage can be a stage located at least one stage before the current stage. Figure 1 An example is shown where the previous stage is located immediately before the current stage. For example, as the start signal STV (such as the carry signal CR), the (k - 3)th output signal OUT[k - 3] (hereinafter referred to as the output signal OUT[k - 3]) output from the (k - 3)th stage STk - 3 can be input to the input terminal IN of the (k - 2)th stage STk - 2.

[0082] The first voltage VGH can be input to the first voltage input terminal V1, and the second voltage VGL can be input to the second voltage input terminal V2. The second voltage VGL can have a lower voltage level than the first voltage VGH.

[0083] The clock signal CLK can be input to the clock terminal CK. The clock signal CLK can include a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 or the second clock signal CLK2 can be input to the clock terminal CK. The first clock signal CLK1 can be input to the clock terminals CK of the odd-numbered stages (such as the first stage ST1, the third stage, and...). The second clock signal CLK2 can be input to the clock terminals CK of the even-numbered stages (such as the second stage, the fourth stage, and...).

[0084] As Figure 2 shown, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals that repeat a high-level voltage and a low-level voltage. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals that repeat a first voltage VGH and a second voltage VGL. The first clock signal CLK1 and the second clock signal CLK2 can be signals having the same waveform and a phase shift. In an embodiment, for example, the second clock signal CLK2 can have the same waveform as the first clock signal CLK1 and can be input by being phase-shifted (phase-delayed) at a specific interval. The second clock signal CLK2 can be shifted by 1 / 4 of a cycle with respect to the first clock signal CLK1. In the first clock signal CLK1 and the second clock signal CLK2, the period during which the high-level voltage is maintained and the period during which the low-level voltage is maintained for one cycle can be the same.

[0085] The output signal OUT can be output from the output terminal GOUT. As Figure 2 shown, the output signals OUT[1],..., OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k],..., and OUT[n] output from the output terminals GOUT of the stages ST1 to STn can be sequentially shifted by a specific period, where n is a positive integer. In an embodiment, the stages ST1 to STn can be configured to shift the output signals OUT[1],..., OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k],..., and OUT[n] having a high-level voltage by 1 / 4 of a cycle of the clock signal CLK and sequentially output the output signals OUT[1],..., OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k],..., and OUT[n]. In an embodiment, the high-level voltage and the low-level voltage of the output signal OUT can be the first voltage VGH and the second voltage VGL, respectively.

[0086] Each of the stages ST1 to STn can be a P-stage PST or an N-stage NST. As Figure 3As shown, in an embodiment, the driving circuit DRV may be a shift register in which a pair of P-stage PSTs and a pair of N-stage NSTs are alternately arranged and cascaded. When a pair of adjacent P-stage PSTs and a pair of N-stage NSTs are referred to as a stage group, the driving circuit DRV may include stage groups arranged repeatedly in one direction (e.g., the y direction).

[0087] The stage group may include a first stage group and a second stage group arranged continuously with the first stage group. The first stage group may include a pair of adjacent P-stage PSTs. The second stage group may include a pair of adjacent N-stage NSTs.

[0088] Figure 3 A stage group including the (k - 3)-th stage STk-3 to the k-th stage STk among the stages ST1 to STn is shown. In this case, k may be an integer greater than 0 and less than or equal to n, and k may be a multiple of 4. The (k - 3)-th stage STk-3 and the (k - 2)-th stage STk-2 may be P-stage PSTs, and the (k - 1)-th stage STk-1 and the k-th stage STk may be N-stage NSTs. The (k - 3)-th stage STk-3 and the (k - 1)-th stage STk-1 may be odd-numbered stages, and the first clock signal CLK1 may be input to the clock terminal CK. The (k - 2)-th stage STk-2 and the k-th stage STk may be even-numbered stages, and the second clock signal CLK2 may be input to the clock terminal CK.

[0089] The output signal OUT[k - 4] of the (k - 4)-th stage may be input to the input terminal IN of the (k - 3)-th stage STk-3. The output signal OUT[k - 3] of the (k - 3)-th stage STk-3 may be input to the input terminal IN of the (k - 2)-th stage STk-2. The output signal OUT[k - 2] of the (k - 2)-th stage STk-2 may be input to the input terminal IN of the (k - 1)-th stage STk-1. The output signal OUT[k - 1] of the (k - 1)-th stage STk-1 may be input to the input terminal IN of the k-th stage STk.

[0090] As Figure 4 and Figure 5As shown, each of the P-stage PST and the N-stage NST may include a control circuit 131 and an output circuit 135. Each of the control circuit 131 and the output circuit 135 may include at least one transistor. The at least one transistor may include an N-channel transistor and / or a P-channel transistor. In an embodiment, for example, the fourth transistor T4 of the P-stage PST may be an N-channel transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 of the P-stage PST may be P-channel transistors. Additionally, the first transistor T1 and the fourth transistor T4 of the N-stage NST may be N-channel transistors, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 of the N-stage NST may be P-channel transistors.

[0091] The P-channel transistor may include a P-channel silicon transistor. The silicon transistor may include a silicon semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. In an embodiment, for example, the silicon transistor may include a low-temperature polycrystalline silicon (“LTPS”) thin-film transistor.

[0092] The N-channel transistor may include an N-channel oxide transistor. The oxide transistor may include an oxide semiconductor, and the oxide semiconductor is a zinc oxide (Zn)-based material and may include Zn oxide, indium (In)-Zn oxide, or indium (In)-gallium (Ga)-zinc (Zn) oxide, etc. In some embodiments, the oxide semiconductor may include indium-gallium-zinc-oxygen (“IGZO”) semiconductor. In some embodiments, the oxide semiconductor may include indium-tin (Sn)-gallium-zinc-oxide (“ITGZO”) semiconductor. In an embodiment, for example, the oxide transistor may include a low-temperature polycrystalline oxide (“LTPO”) thin-film transistor.

[0093] The gate turn-on voltage of the P-channel transistor may be a low-level voltage, and the gate turn-off voltage of the P-channel transistor may be a high-level voltage. The gate turn-on voltage of the N-channel transistor may be a high-level voltage, and the gate turn-off voltage of the N-channel transistor may be a low-level voltage.

[0094] The control circuit 131 of each of the P-stage PST and the N-stage NST may be configured to control the voltages of the first node A, the second node Q, and the third node QB in response to a signal input to the input terminal IN. In an embodiment, for example, the control circuit 131 may be configured to respond to a start signal STV (e.g., an external signal FLM (see Figure 1 ) or a carry signal CR (see Figure 1)) to control the voltages of the first node A, the second node Q, and the third node QB. In an embodiment, the carry signal CR may be a previous output signal. The control circuit 131 may include a first transistor T1 to a fourth transistor T4.

[0095] The first transistor T1 of the P-stage PST is a P-channel transistor, the first transistor T1 of the N-stage NST is an N-channel transistor, and the other configurations of the P-stage PST and the N-stage NST are the same.

[0096] The first transistor T1 may be connected between the input terminal IN and the first node A. The gate of the first transistor T1 may be connected to the clock terminal CK. The first transistor T1 of the P-stage PST may be turned on when the clock signal CLK input to the clock terminal CK is at a low level, and may be configured to transmit the start signal STV input to the input terminal IN to the first node A. The first transistor T1 of the N-stage NST may be turned on when the clock signal CLK input to the clock terminal CK is at a high level, and may be configured to transmit the start signal STV input to the input terminal IN to the first node A. The clock signal CLK may be the first clock signal CLK1 or the second clock signal CLK2.

[0097] In an embodiment, the first clock signal CLK1 may be input to the clock terminals CK of the odd-numbered P-stage PSTs and the odd-numbered N-stage NSTs, and the second clock signal CLK2 may be input to the clock terminals CK of the even-numbered P-stage PSTs and the even-numbered N-stage NSTs. In another embodiment, the second clock signal CLK2 may be input to the clock terminals CK of the odd-numbered P-stage PSTs and the odd-numbered N-stage NSTs, and the first clock signal CLK1 may be input to the clock terminals CK of the even-numbered P-stage PSTs and the even-numbered N-stage NSTs.

[0098] The second transistor T2 can be connected between the first node A and the second node Q. The gate of the second transistor T2 can be connected to the second voltage input terminal V2. The second transistor T2 can be turned on in response to the second voltage VGL input to the second voltage input terminal V2, and can be configured to transmit the start signal STV transmitted through the first transistor T1 to the second node Q. The second transistor T2 can be turned on substantially all the time. In a stage where the second transistor T2 is omitted and only the first transistor T1 is provided, the stress on the first transistor T1 may increase due to the long-term low level of the voltage of the second node Q or the voltage of the first node A. Since the second transistor T2 is provided, the first transistor T1 and the second transistor T2 share the stress caused by the voltage of the second node Q or the voltage of the first node A being at a low level for a long time, and thus, the stress on the first transistor T1 can be reduced. Additionally, when the first transistor T1 is turned off, the line voltage drop between the input terminal IN and the first node A can be prevented by the second transistor T2.

[0099] The third transistor T3 can be connected between the first voltage input terminal V1 and the third node QB. The gate of the third transistor T3 can be connected to the first node A. The third transistor T3 can be turned on when the start signal STV transmitted to the first node A is at a low level, and can be configured to transmit the first voltage VGH input to the first voltage input terminal V1 to the third node QB. Due to the third transistor T3, the voltage of the third node QB can be at a voltage level obtained by inverting the voltage level of the first node A. In other words, when the voltage of the first node A is at a low level, the voltage of the third node QB can become high due to the third transistor T3.

[0100] The fourth transistor T4 can be connected between the third node QB and the second voltage input terminal V2. The gate of the fourth transistor T4 can be connected to the second node Q. The fourth transistor T4 can be turned on when the start signal STV transmitted to the second node Q is at a high level, and can be configured to transmit the second voltage VGL input to the second voltage input terminal V2 to the third node QB. Due to the fourth transistor T4, the voltage of the third node QB can be at a voltage level obtained by inverting the voltage level of the second node Q. In other words, when the voltage of the second node Q is at a high level, the voltage of the third node QB can become low due to the fourth transistor T4.

[0101] The third transistor T3 and the fourth transistor T4 can be configured to control the voltage level of the third node QB according to the voltage level of the first node A or the second node Q, and thus can be used as an "inverter" or a level shifter.

[0102] The output circuit 135 can be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The output circuit 135 can be configured to output an output signal OUT having a high-level voltage or a low-level voltage according to the voltage levels of the second node Q and the third node QB. The output circuit 135 can include a fifth transistor T5 and a sixth transistor T6. The output circuit 135 can further include a first capacitor C1 and a second capacitor C2.

[0103] The fifth transistor T5 can be connected between the output terminal GOUT and the second voltage input terminal V2. The gate of the fifth transistor T5 can be connected to the second node Q. The fifth transistor T5 can be a "pull-down transistor" configured to transmit a low-level voltage to the output terminal GOUT. The fifth transistor T5 can be turned on when the voltage at the second node Q is at a low level, and can be configured to transmit the second voltage VGL, which is the low-level voltage input to the second voltage input terminal V2, to the output terminal GOUT.

[0104] The sixth transistor T6 can be connected between the first voltage input terminal V1 and the output terminal GOUT. The gate of the sixth transistor T6 can be connected to the third node QB. The sixth transistor T6 can be a "pull-up transistor" configured to transmit a high-level voltage to the output terminal GOUT. The sixth transistor T6 can be turned on when the voltage at the third node QB is at a low level, and can be configured to transmit the first voltage VGH, which is the high-level voltage input to the first voltage input terminal V1, to the output terminal GOUT.

[0105] The first capacitor C1 can be connected between the output terminal GOUT and the second node Q. The second capacitor C2 can be connected between the first voltage input terminal V1 and the third node QB. The first capacitor C1 can be configured to maintain the voltage of the second node Q, and the second capacitor C2 can be configured to maintain the voltage of the third node QB.

[0106] Hereinafter, reference will be made to Figure 6 the description Figure 3 of the operation of the stage group shown in

[0107] Figure 6Shows the first clock signal CLK1, the second clock signal CLK2, the output signals OUT[k - 3], OUT[k - 2], OUT[k - 1], and OUT[k] of the (k - 3)-th stage STk - 3 to the k-th stage STk, the previous output signal OUT[k - 4] as the start signal of the (k - 3)-th stage STk - 3, and the voltages VQ[k - 3], VQ[k - 2], VQ[k - 1], and VQ[k] of the second node Q and the voltages VQB[k - 3], VQB[k - 2], VQB[k - 1], and VQB[k] of the third node QB of the (k - 3)-th stage STk - 3 to the k-th stage STk. The previous output signal OUT[k - 4] of the (k - 3)-th stage STk - 3 can be the output signal of the (k - 4)-th stage.

[0108] During the first period P1 to the eighth period P8, the previous output signal OUT[k - 4] at a high level as the start signal can be supplied to the input terminal IN of the (k - 3)-th stage STk - 3.

[0109] In the first period P1, the high-level first clock signal CLK1 can be supplied to the clock terminal CK of the odd-numbered stages, and the high-level second clock signal CLK2 can be supplied to the clock terminal CK of the even-numbered stages.

[0110] Due to the high-level first clock signal CLK1, the first transistor T1 of the (k - 3)-th stage STk - 3 can remain cut off, the first node A and the second node Q can maintain the same low-level voltage as in the previous period, and the low-level (k - 3) output signal OUT[k - 3] can be output through the fifth transistor T5. Due to the conducting third transistor T3, the voltage of the third node QB can be a high-level voltage.

[0111] In the second period P2, the low-level first clock signal CLK1 can be supplied to the clock terminal CK of the odd-numbered stages, and the high-level second clock signal CLK2 can be supplied to the clock terminal CK of the even-numbered stages.

[0112] The first transistor T1 of the (k-3)-th stage STk-3 can be turned on by a low-level first clock signal CLK1. The second transistor T2 can be in a state of being turned on by a low-level second voltage VGL. Due to the turned-on first transistor T1 and second transistor T2, a high-level previous output signal OUT[k-4] can be transmitted to the first node A and the second node Q of the (k-3)-th stage STk-3, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off and the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and thus, the voltage of the third node QB can be the low-level second voltage VGL. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and a high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0113] In the third period P3, a low-level first clock signal CLK1 can be supplied to the clock terminals CK of the odd-numbered stages, and a low-level second clock signal CLK2 can be supplied to the clock terminals CK of the even-numbered stages.

[0114] The first transistor T1 of the (k-3)-th stage STk-3 can be kept turned on by a low-level first clock signal CLK1. Due to the turned-on first transistor T1 and second transistor T2, a high-level previous output signal OUT[k-4] can be transmitted to the first node A and the second node Q of the (k-3)-th stage STk-3, and the fifth transistor T5 can be kept turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and a low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and a high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0115] In the fourth period P4, a high-level first clock signal CLK1 can be supplied to the clock terminals CK of the odd-numbered stages, and a low-level second clock signal CLK2 can be supplied to the clock terminals CK of the even-numbered stages.

[0116] The first transistor T1 of the (k-3)-th stage STk-3 can be turned off by the high-level first clock signal CLK1. The second transistor T2 can be in a conducting state through the low-level second voltage VGL. Since the first node A and the second node Q of the (k-3)-th stage STk-3 maintain a high-level voltage in the third period P3 through the first capacitor C1, the fifth transistor T5 can remain turned off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0117] In the fifth period P5, the high-level first clock signal CLK1 can be supplied to the clock terminal CK of the odd-numbered stages, and the high-level second clock signal CLK2 can be supplied to the clock terminal CK of the even-numbered stages.

[0118] The first transistor T1 of the (k-3)-th stage STk-3 can be turned off by the high-level first clock signal CLK1. The second transistor T2 can be in a conducting state through the low-level second voltage VGL. Since the first node A and the second node Q of the (k-3)-th stage STk-3 maintain a high-level voltage in the fourth period P4 through the first capacitor C1, the fifth transistor T5 can remain turned off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0119] In the sixth period P6, the seventh period P7, and the eighth period P8, the (k-3)-th stage STk-3 can operate in the same manner as in the second period P2, the third period P3, and the fourth period P4, and a high-level output signal OUT[k-3] can be output from the output terminal GOUT.

[0120] In the ninth period P9, the previous output signal OUT[k-4] can be converted from high level to low level and supplied to the input terminal IN of the (k-3)-th stage STk-3. The high-level first clock signal CLK1 can be supplied to the clock terminal CK of the odd-numbered stages, and the high-level second clock signal CLK2 can be supplied to the clock terminal CK of the even-numbered stages.

[0121] In the ninth period P9, the start signal transitions from high level to low level, but the first clock signal CLK1 of high level is input to the clock terminal CK of the (k - 3)-th stage STk-3, causing the first transistor T1 to turn off. Therefore, regardless of the voltage level of the start signal, the operation of the (k - 3)-th stage STk-3 can be the same as its operation during the fifth period P5. Thus, an output signal OUT[k - 3] of high level can be output from the output terminal GOUT of the (k - 3)-th stage STk-3.

[0122] In the tenth period P10, the previous output signal OUT[k - 4] of low level can be supplied to the input terminal IN of the (k - 3)-th stage STk-3. The first clock signal CLK1 of low level can be supplied to the clock terminals CK of the odd-numbered stages, and the second clock signal CLK2 of high level can be supplied to the clock terminals CK of the even-numbered stages.

[0123] The first transistor T1 of the (k - 3)-th stage STk-3 can be turned on by the first clock signal CLK1 of low level. The second transistor T2 can be in a state of being turned on by the second voltage VGL of low level. Due to the turned-on first transistor T1 and second transistor T2, the previous output signal OUT[k - 4] of low level can be transmitted to the first node A and the second node Q of the (k - 3)-th stage STk-3, and the voltages of the first node A and the second node Q are low-level voltages, enabling the fifth transistor T5 to be turned on. Thus, the second voltage VGL of low level can be output from the output terminal GOUT of the (k - 3)-th stage STk-3 as the output signal OUT[k - 3]. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be turned off, and the first voltage VGH of high level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned off.

[0124] During the second period P2 to the ninth period P9, the previous output signal OUT[k - 3] of high level as the start signal from the (k - 3)-th stage STk-3 can be supplied to the input terminal IN of the (k - 2)-th stage STk-2.

[0125] In the second period P2, the second clock signal CLK2 at a high level is input to the clock terminal CK of the (k-2)-th stage STk-2. Therefore, the first transistor T1 of the (k-2)-th stage STk-2 remains cut off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 is turned on. Thus, the second voltage VGL at a low level can be output from the output terminal GOUT as the (k-2)-th output signal OUT[k-2] (hereinafter referred to as the output signal OUT[k-2]). The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0126] In the third period P3 and the fourth period P4, the second clock signal CLK2 at a low level is input to the clock terminal CK of the (k-2)-th stage STk-2. Therefore, the first transistor T1 can be turned on. Due to the turned-on first transistor T1 and the second transistor T2, the previous output signal OUT[k-3] at a high level can be transmitted to the first node A and the second node Q of the (k-2)-th stage STk-2, and the fifth transistor T5 can be cut off. The third transistor T3 whose gate is connected to the first node A can be cut off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the second voltage VGL at a low level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the first voltage VGH at a high level can be transmitted to the output terminal GOUT. Thus, the output signal OUT[k-2] at a high level can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0127] Since the operation of the (k-2)-th stage STk-2 during the fifth period P5 to the eleventh period P11 is the same as the operation of the (k-3)-th stage STk-3 during the fourth period P4 to the tenth period P10, its detailed description is omitted.

[0128] During the third period P3 to the tenth period P10, the previous output signal OUT[k-2] at a high level as a start signal from the (k-2)-th stage STk-2 can be supplied to the input terminal IN of the (k-1)-th stage STk-1.

[0129] In the third period P3, the first clock signal CLK1 at a low level is input to the clock terminal CK of the (k-1)-th stage STk-1. Therefore, the first transistor T1 of the (k-1)-th stage STk-1 remains cut off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 is turned on. Therefore, the second voltage VGL at a low level can be output from the output terminal GOUT as the (k-1)-th output signal OUT[k-1] (hereinafter referred to as the output signal OUT[k-1]). The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0130] In the fourth period P4 and the fifth period P5, the first clock signal CLK1 at a high level is input to the clock terminal CK of the (k-1)-th stage STk-1. Therefore, the first transistor T1 can be turned on. Due to the turned-on first transistor T1 and the second transistor T2, the previous output signal OUT[k-2] at a high level can be transmitted to the first node A and the second node Q of the (k-1)-th stage STk-1, and the fifth transistor T5 can be cut off. The third transistor T3 whose gate is connected to the first node A can be cut off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the second voltage VGL at a low level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the first voltage VGH at a high level can be transmitted to the output terminal GOUT. Therefore, the output signal OUT[k-1] at a high level can be output from the output terminal GOUT of the (k-1)-th stage STk-1.

[0131] In the sixth period P6 and the seventh period P7, the first clock signal CLK1 at a low level is input to the clock terminal CK of the (k-1)-th stage STk-1. Therefore, the first transistor T1 can be cut off. Since the first node A and the second node Q maintain the high-level voltage in the fifth period P5 through the first capacitor C1, the fifth transistor T5 can remain cut off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the second voltage VGL at a low level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the first voltage VGH at a high level can be transmitted to the output terminal GOUT. Therefore, the output signal OUT[k-1] at a high level can be output from the output terminal GOUT of the (k-1)-th stage STk-1.

[0132] In the eighth period P8, the ninth period P9, and the tenth period P10, the (k-1)-th stage STk-1 can operate in the same manner as in the fourth period P4, the fifth period P5, and the sixth period P6, and the output signal OUT[k-1] at a high level can be output from the output terminal GOUT.

[0133] In the eleventh time period P11, the previous output signal OUT[k-2] transitions from a high level to a low level and is supplied to the input terminal IN of the (k-1)-th stage STk-1. However, the first clock signal CLK1 at a low level is input to the clock terminal CK of the (k-1)-th stage STk-1, causing the first transistor T1 to be cut off. Therefore, regardless of the voltage level of the start signal, the operation of the (k-1)-th stage STk-1 can be the same as its operation during the sixth time period P6. Therefore, an output signal OUT[k-1] at a high level can be output from the output terminal GOUT of the (k-1)-th stage STk-1.

[0134] In the twelfth time period P12, the previous output signal OUT[k-2] at a low level can be supplied to the input terminal IN of the (k-1)-th stage STk-1. The first transistor T1 of the (k-1)-th stage STk-1 can be turned on by the first clock signal CLK1 at a high level. The second transistor T2 can be in a state of being turned on by the second voltage VGL at a low level. Due to the turned-on first transistor T1 and second transistor T2, the previous output signal OUT[k-2] at a low level can be transmitted to the first node A and the second node Q of the (k-1)-th stage STk-1, and the fifth transistor T5 can be turned on. Therefore, the second voltage VGL at a low level can be output from the output terminal GOUT of the (k-1)-th stage STk-1 as the output signal OUT[k-1]. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be cut off, and the first voltage VGH at a high level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be cut off.

[0135] During the fourth time period P4 to the eleventh time period P11, the previous output signal OUT[k-1] at a high level as the start signal from the (k-1)-th stage STk-1 can be supplied to the input terminal IN of the k-th stage STk.

[0136] In the fourth time period P4, the second clock signal CLK2 at a low level is input to the clock terminal CK of the k-th stage STk. Therefore, the first transistor T1 of the k-th stage STk remains cut off, the first node A and the second node Q maintain the same low-level voltage as in the previous time period, and the fifth transistor T5 is turned on. Therefore, the second voltage VGL at a low level can be output from the output terminal GOUT as the k-th output signal OUT[k] (hereinafter referred to as the output signal OUT[k]). The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0137] In the fifth period P5 and the sixth period P6, a high-level second clock signal CLK2 is input to the clock terminal CK of the k-th stage STk, and thus, the first transistor T1 can be turned on. Due to the turned-on first transistor T1 and second transistor T2, the high-level previous output signal OUT[k - 1] can be transmitted to the first node A and the second node Q of the k-th stage STk, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k] can be output from the output terminal GOUT of the k-th stage STk.

[0138] Since the operation of the k-th stage STk during the seventh period P7 to the thirteenth period P13 is the same as the operation of the (k - 1)-th stage STk-1 during the sixth period P6 to the twelfth period P12, its detailed description is omitted.

[0139] By alternately arranging a plurality of stages constituting the driving circuit DRV in a pair of P-stage PST and a pair of N-stage NST, errors in which adjacent stages in an arrangement where one P-stage PST and one N-stage NST are alternately arranged operate simultaneously can be significantly reduced.

[0140] The P-stage PST and N-stage NST according to one or more embodiments are not limited to Figure 4 and Figure 5 , and various modifications can be made. Hereinafter, various examples of the P-stage PST and N-stage NST will be mainly described focusing on the differences from the stages shown in Figures 3 to 5 .

[0141] Figure 7 FIG. is a diagram of a P-stage PST according to another embodiment.

[0142] Referring to Figure 7 , and also referring to Figure 1 , the fourth transistor T4 of the P-stage PST can be connected between the third node QB and the second voltage input terminal V2, and the gate of the fourth transistor T4 can be connected to the first node A. The fourth transistor T4 can be turned on when the start signal STV transmitted to the first node A is at a high level, and can be configured to transmit the second voltage VGL input to the second voltage input terminal V2 to the third node QB. In an embodiment, the fourth transistor T4 can be a double-gate transistor further including a back gate connected to the second node Q (refer to Fig. 22 ).

[0143] When the start signal STV is at a low level, due to the second transistor T2, the voltage of the second node Q can be lower than the voltage of the first node A. Therefore, compared with the cut-off reliability of the fourth transistor T4 when the gate of the fourth transistor T4 is connected to the second node Q, the cut-off reliability of the fourth transistor T4 when the gate of the fourth transistor T4 is connected to the first node A can be improved.

[0144] The P-stage PST may further include a seventh transistor T7 as a reset circuit. The seventh transistor T7 may be configured to reset the voltages of the first node A and the second node Q based on a reset signal ESR supplied to a reset terminal RS. The seventh transistor T7 may be connected between a first voltage input terminal V1 and the first node A, and the gate of the seventh transistor T7 may be connected to the reset terminal RS. The seventh transistor T7 may conduct when the reset signal ESR is supplied to the reset terminal RS at a low level, and may be configured to reset (initialize) the voltages of the first node A and the second node Q to a first voltage VGH.

[0145] In an embodiment, the reset signal ESR may be supplied to the first stage ST1 to the nth stage STn at a low level at a specific time point (timing). The reset signal ESR may be supplied in the form of a pulse having a low level of a second voltage VGL at a certain time point (timing), or may be supplied as the first voltage VGH at other time points (timing). In an embodiment, for example, when an operation error occurs in the device, the reset signal ESR may be supplied to initialize (reset) the voltages of the first node A and the second node Q.

[0146] In the P-stage PST, when a low-level start signal STV is input and a low-level clock signal CLK is supplied, the second transistor T2 may gradually turn off. As the voltage at the output terminal GOUT drops from a high level to a low level while the second transistor T2 is in the off state, due to the coupling of the first capacitor C1, the voltage of the second node Q may drop to a voltage lower than the second voltage VGL (for example, approximately -15V to approximately -20V, which is approximately 2×VGL (twice the second voltage VGL)). In contrast, due to the threshold voltage loss of the first transistor T1, the voltage of the first node A may be a voltage higher than the second voltage VGL (for example, approximately -8V to approximately -10V, which is approximately VGL + │Vth│). Here, Vth is the threshold voltage of the first transistor T1, and VGL represents the voltage value of the second voltage VGL. Compared with the embodiment in which the gate of the fourth transistor T4 is connected to the second node Q, in the embodiment in which the gate of the fourth transistor T4 is connected to the first node A, the gate cut-off bias of the N-channel transistor can be reduced, thereby improving device reliability.

[0147] Figure 7The configuration and operation of the P-stage PST shown, except for the fourth transistor T4 and the seventh transistor T7, are the same as those of the P-stage PST shown in Figure 4 In an embodiment, the seventh transistor T7 can be omitted from the P-stage PST shown in Figure 7 Figure

[0148] Figures 8 to 10 is a diagram of an N-stage NST according to other embodiments.

[0149] Referring to Figures 8 to 10 and also referring to Figure 1 , Figure 8 the N-stage NST shown in Figure 5 differs from the N-stage NST shown in Figure 8 in that the first transistor T1 has a structure in which a plurality of sub-transistors are connected in series, and Figure 5 the configuration and operation of the N-stage NST shown in

[0150] except for the above differences are the same as those of the N-stage NST shown in

[0151] Fig. 9 The N-stage NST shown in Figure 5 differs from the N-stage NST shown in Fig. 9 in that the gate of the third transistor T3 is connected to the second node Q, and Figure 5 the configuration and operation of the N-stage NST shown in

[0152] except for the above differences are the same as those of the N-stage NST shown in

[0153] Fig.10The N-stage NST shown in Fig. 9 differs from the N-stage NST shown in Fig.10 in that the first transistor T1 has a structure in which a plurality of sub-transistors are connected in series, and Fig. 9 the configuration and operation of the N-stage NST shown in

[0154] except for the above differences are the same as those of the N-stage NST shown in

[0155] Figure 1 The stage group of the drive circuit DRV shown in Figure 3 is not limited to the stage group shown in Figure 4 and Figure 7 In an embodiment, for example, the stage group of the drive circuit DRV may be composed of a combination of one of the P-stage PSTs shown in Figure 5 and Figures 8 to 10 and one of the N-stage NSTs shown in

[0156] Figures 11 to 25 is a diagram of the stage group of the drive circuit DRV according to other embodiments. Figures 11 to 25 The drive circuit DRV shown in

[0157] As Fig.11 shown, the stage group may include Figure 4 the P-stage PST shown in Figure 8 and the N-stage NST shown in

[0158] As Fig.12 shown, the stage group may include Figure 4 the P-stage PST shown in Fig. 9 and the N-stage NST shown in

[0159] As Fig.13 shown, the stage group may include Figure 4 the P-stage PST shown in Fig.10 The N-stage NST shown in

[0160] As Fig.14 shown, the stage group may include Figure 7 the P-stage PST shown in Figure 5 and the N-stage NST shown in

[0161] As Fig.15 shown, the stage group may include Figure 7 the P-stage PST shown in Figure 8 and the N-stage NST shown in

[0162] As Fig.16 shown, the stage group may include Figure 7 the P-stage PST shown in Fig. 9 and the N-stage NST shown in

[0163] As Fig.17 shown, the stage group may include Figure 7 the P-stage PST shown in Fig.10 and the N-stage NST shown in

[0164] In an embodiment, the transistors of the P-stage PST and the N-stage NST may each further include a back gate. The first transistor T1 to the sixth transistor T6 of the P-stage PST and the N-stage NST may each be a double-gate transistor including a first gate and a second gate, the first gate being a top gate disposed above the semiconductor, and the second gate being a bottom gate (back gate) disposed below the semiconductor. Figures 18 to 25 is one in which Figure 3 and Figures 11 to 17 the first transistor T1 to the seventh transistor T7 in are respectively the stage group of the drive circuit DRV that is a double-gate transistor.

[0165] In Figures 18 to 21 , for each of the first transistor T1 to the sixth transistor T6 of each of the P-stage PST and the N-stage NST, the first gate and the second gate may be electrically connected to each other and supplied with the same voltage. In Figure 22 to Figure 25 , also referring to Figure 7, the first gate and the second gate of each of the first transistor T1 to the sixth transistor T6 of the N-stage NST may be electrically connected to each other and supplied with the same voltage. The first gate and the second gate of the first transistor T1 may be connected to the clock terminal CK. The first gate and the second gate of the second transistor T2 may be connected to the second voltage input terminal V2. The first gate and the second gate of the third transistor T3 may be connected to the first node A. The first gate and the second gate of the fourth transistor T4 may be connected to the second node Q. The first gate and the second gate of the fifth transistor T5 may be connected to the second node Q. The first gate and the second gate of the sixth transistor T6 may be connected to the third node QB.

[0166] In Figure 22 to Figure 25 , the first gate and the second gate of each of the first transistor T1 to the third transistor T3 and the fifth transistor T5 to the seventh transistor T7 of the P-stage PST may be electrically connected to each other and supplied with the same voltage. The first gate and the second gate of the seventh transistor T7 may be connected to the reset terminal RS. The first gate and the second gate of the fourth transistor T4 may be connected to different nodes. The first gate of the fourth transistor T4 may be connected to the first node A, and the second gate of the fourth transistor T4 may be connected to the second node Q. Due to the second transistor T2, the voltage of the first node A and the voltage of the second node Q may be voltages at substantially the same level.

[0167] Fig.26 is a schematic diagram of a drive circuit DRV according to another embodiment. Fig. 27 is Fig.26 a diagram of any stage group among the multiple stages included in the drive circuit DRV of Fig.28 is a diagram showing Fig. 27 an example of the P-stage PST among the stage groups in Fig.29 and Fig.30 is a diagram showing Fig. 27 an example of the N-stage NST among the stage groups in Figure 31 to Figure 37 is a diagram of a stage group of a drive circuit DRV according to other embodiments. Hereinafter, the description will mainly focus on configurations different from those described with reference to Figures 3 to 6 the configuration described.

[0168] Referring to Figures 26 to 37 , the drive circuit DRV according to the embodiment may include multiple stages ST1 to STn. Fig.26 Each stage of the drive circuit DRV shown in Figure 3 differs from the stage shown in

[0169] Each of the multiple stages ST1 to STn can be configured to output an output signal OUT from an output terminal GOUT to a signal line in response to a start signal STV. The output signals OUT[1], ……, OUT[k-3], OUT[k-2], OUT[k-1], OUT[k], ……, and OUT[n-1] (not shown) can be start signals STV respectively input to input terminals IN of the second stage to the nth stage STn as subsequent stages. An external signal FLM can be input as the start signal STV to the input terminal IN of the first stage ST1.

[0170] Each of the multiple stages ST1 to STn can be configured to output the voltage of a second node Q as a second carry signal QCR through a node voltage output terminal QOUT.

[0171] As Fig. 27 shown, a stage group can include Fig.28 the P-stage PST shown in Fig.29 and the N-stage NST shown in Fig.28 The P-stage PST shown in Figure 4 differs from the P-stage PST shown in Fig.28 that the P-stage PST shown in Fig.29 includes a node voltage output terminal QOUT configured to output the voltage of the second node Q as the second carry signal QCR, and the other configurations and operations are the same. Figure 5 The N-stage NST shown in Fig.29 differs from the N-stage NST shown in

[0172] In Fig.29 the N-stage NST shown, the first transistor T1 can include a plurality of sub-transistors connected in series between an input terminal IN and a first node A. The plurality of sub-transistors can include a pair of a first sub-transistor T1-1 and a second sub-transistor T1-2. Each of the first sub-transistor T1-1 and the second sub-transistor T1-2 can be a double-gate transistor including a first gate and a second gate, where the first gate is a top gate disposed above the semiconductor, and the second gate is a bottom gate (back gate) disposed below the semiconductor. The first transistor T1 is implemented such that a plurality of N-type sub-transistors are connected in series and each sub-transistor is configured as a double-gate transistor, and thus, the leakage current can be significantly reduced.

[0173] The first gate of the first sub-transistor T1-1 may be connected to the clock terminal CK, and the second gate of the first sub-transistor T1-1 may be connected to the node voltage input terminal QIN. The first gate of the second sub-transistor T1-2 may be connected to the clock terminal CK, and the second gate of the second sub-transistor T1-2 may be connected to the second node Q.

[0174] The first sub-transistor T1-1 and the second sub-transistor T1-2 may be turned on when the clock signal CLK input to the clock terminal CK is at a high level, and may be configured to transmit the start signal STV input to the input terminal IN to the first node A.

[0175] When a (-) voltage is supplied to the bottom gate of the oxide transistor, the threshold voltage increases and may shift positively, and when a (+) voltage is supplied, the threshold voltage decreases and may shift negatively.

[0176] In an embodiment, for example, when a low-level previous output signal OUT' is input to the input terminal IN of any N-stage NST (or "current stage") and a low-level output signal OUT is output, the voltage VQ' of the low-level second node Q of the previous stage (or "previous second node voltage VQ'") may be input to the second gate of the first sub-transistor T1-1, and the voltage VQ of the low-level second node Q of the current stage may be input to the second gate of the second sub-transistor T1-2. In this case, the threshold voltages of the first sub-transistor T1-1 and the second sub-transistor T1-2 shift positively, so that the leakage current can be reduced.

[0177] In addition, when a high-level previous output signal OUT' is input to the input terminal IN of the current stage and a high-level output signal OUT is output, the high-level previous second node voltage VQ' may be input to the second gate of the first sub-transistor T1-1, and the voltage VQ of the high-level second node Q of the current stage may be input to the second gate of the second sub-transistor T1-2. In this case, the threshold voltages of the first sub-transistor T1-1 and the second sub-transistor T1-2 shift negatively, so that the current transmitted through the first transistor T1 can be increased, thereby improving the charging ability of the second node Q.

[0178] Furthermore, in period ①, when a high-level previous output signal OUT' is input to the input terminal IN of the current stage and a low-level output signal OUT is output, the high-level previous second node voltage VQ' may be input to the second gate of the first sub-transistor T1-1, and the voltage VQ of the low-level second node Q of the current stage may be input to the second gate of the second sub-transistor T1-2. In this case, the threshold voltage of the first sub-transistor T1-1 may shift negatively, and the threshold voltage of the second sub-transistor T1-2 may shift positively.

[0179] In addition, in period ②, when the previous output signal OUT' at a low level is input to the input terminal IN of the current stage and the output signal OUT at a high level is output, the previous second node voltage VQ' at a low level can be input to the second gate of the first sub-transistor T1-1, and the voltage VQ of the second node Q at a high level of the current stage can be input to the second gate of the second sub-transistor T1-2. In this case, the threshold voltage of the first sub-transistor T1-1 can be positively shifted, and the threshold voltage of the second sub-transistor T1-2 can be negatively shifted.

[0180] In periods ① and ②, voltages of different levels are input to the second gate of the first sub-transistor T1-1 and the second gate of the second sub-transistor T1-2, and thus, the leakage current can be reduced.

[0181] As Fig.30 and Fig.31 shown, in the N-stage NST, the gate of the third transistor T3 can be connected to the second node Q. The third transistor T3 can be turned on when the voltage of the second node Q is at a low level, and can be configured to transmit the first voltage VGH to the third node QB.

[0182] Only some of the second carry signals QCR[1], ……, QCR[k-3], QCR[k-2], QCR[k-1], QCR[k], ……, and QCR[n] output from the multiple stages ST1 to STn can be input to the subsequent stage. In an embodiment, for example, only the N-stage NST among the multiple stages ST1 to STn can include a node voltage input terminal QIN, and be configured to receive the previous second node voltage VQ' as the second carry signal QCR.

[0183] Figures 27 to 31 The stage groups shown in each of [] can operate according to Figure 6 the timing diagram shown in [].

[0184] In an embodiment, the transistors in each of the P-stage PST and the N-stage NST can each be a double-gate transistor including a first gate and a second gate, where the first gate is a top gate disposed above the semiconductor, and the second gate is a bottom gate (back gate) disposed below the semiconductor. Fig.32 and Fig.33 are diagrams of stage groups of the drive circuit DRV in which the transistors in [] and [] are double-gate transistors respectively. Fig. 27 and Fig.31 The stage group of the drive circuit DRV shown in [] is not limited to

[0185] Fig.26 The stage group of the drive circuit DRV shown in [] is not limited to Fig. 27 and Figure 31 to Figure 33The stage group shown in. In an embodiment, for example, as Figure 34 to Figure 37 shown, the stage group of the drive circuit DRV may include Figure 7 the P stage PST shown in.

[0186] Fig.38 is a schematic diagram of a drive circuit DRV according to another embodiment. Fig.39 is Fig.38 a diagram of any stage group among the multiple stages included in the drive circuit DRV of. Fig.40 is for describing Fig.39 the driving of the stage group of. In the following, the description will mainly focus on configurations different from those described in the above embodiments.

[0187] Referring to Figures 38 to 40 , the drive circuit DRV according to an embodiment may include multiple stages ST1 to STn. As Fig.39 shown, Fig.38 the drive circuit DRV shown in may be one in which Figure 4 the P stage PST shown in and Figure 5 the N stage NST shown in are alternately arranged and cascaded shift registers.

[0188] The stage group may include a first stage group and a second stage group arranged continuously with the first stage group. The first stage group and the second stage group may each include odd-numbered P stage PSTs and even-numbered N stage NSTs.

[0189] By alternately arranging the multiple stages constituting the drive circuit DRV as P stage PSTs and N stage NSTs, the clock frequency can be reduced compared to a drive circuit including only P stage PSTs, thereby reducing power consumption.

[0190] The first clock signal CLK1 or the second clock signal CLK2 may be input to the clock terminal CK of each of the multiple stages ST1 to STn. The first clock signal CLK1 or the second clock signal CLK2 may be input to the clock terminals CK of consecutive odd-numbered and even-numbered stages in the stage group. In an embodiment, for example, the first clock signal CLK1 may be input to the clock terminals CK of the first P stage PST and the second N stage NST, and the second clock signal CLK2 may be input to the clock terminals CK of the third P stage PST and the fourth N stage NST.

[0191] As Fig.40As shown, the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals that repeat a high-level voltage and a low-level voltage. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals that repeat a first voltage VGH and a second voltage VGL. The first clock signal CLK1 and the second clock signal CLK2 may be signals having the same waveform and a phase shift. In an embodiment, for example, the second clock signal CLK2 may have the same waveform as the first clock signal CLK1 and may be input by being phase-shifted (phase-delayed) at a specific interval. The second clock signal CLK2 may be shifted by 1 / 2 a cycle from the first clock signal CLK1. In the first clock signal CLK1 and the second clock signal CLK2, the period during which the high-level voltage is maintained may be longer than the period during which the low-level voltage is maintained.

[0192] The stages ST1 to STn may be configured to shift the output signals OUT[1], ……, OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k], ……, and OUT[n] having a high-level voltage by 1 / 4 of a cycle of the clock signal and sequentially output the output signals OUT[1], ……, OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k], ……, and OUT[n].

[0193] Hereinafter, reference will be made to Fig.40 describe Fig.39 the operation of the stage group shown in

[0194] During the first period P1 to the eighth period P8, the previous output signal OUT[k - 4] at a high level, which is a start signal, may be supplied to the input terminal IN of the (k - 3)th stage STk - 3.

[0195] In the first period P1, the high-level first clock signal CLK1 is input to the clock terminal CK of the (k - 3)th stage STk - 3. Therefore, the first transistor T1 of the (k - 3)th stage STk - 3 remains cut off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 is turned on. Accordingly, the low-level second voltage VGL may be output from the output terminal GOUT as the (k - 3)th output signal OUT[k - 3]. The voltage of the third node QB may be at a high-level voltage due to the turned-on third transistor T3.

[0196] In the second period P2, a low-level first clock signal CLK1 is input to the clock terminal CK of the (k - 3)-th stage STk-3, and thus, the first transistor T1 of the (k - 3)-th stage STk-3 can be turned on. Due to the turned-on first transistor T1 and second transistor T2, a high-level previous output signal OUT[k - 4] can be transmitted to the first node A and the second node Q of the (k - 3)-th stage STk-3, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and a low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and a high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k - 3] can be output from the output terminal GOUT of the (k - 3)-th stage STk-3.

[0197] In the third period P3, fourth period P4, and fifth period P5, a high-level first clock signal CLK1 is input to the clock terminal CK of the (k - 3)-th stage STk-3, and thus, the first transistor T1 can be turned off. Since the first node A and the second node Q maintain the high-level voltage in the second period P2 through the first capacitor C1, the fifth transistor T5 can remain turned off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and a low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and a high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k - 3] can be output from the output terminal GOUT of the (k - 3)-th stage STk-3.

[0198] Since the operation of the (k - 3)-th stage STk-3 during the sixth period P6 to the ninth period P9 is the same as the operation of the (k - 3)-th stage STk-3 during the second period P2 to the fifth period P5, its detailed description is omitted.

[0199] In the ninth period P9, the previous output signal OUT[k - 4] transitions from high level to low level and is supplied to the input terminal IN of the (k - 3)-th stage STk-3, but a high-level first clock signal CLK1 is input to the clock terminal CK of the (k - 3)-th stage STk-3, causing the first transistor T1 to turn off. Therefore, regardless of the voltage level of the start signal, the operation of the (k - 3)-th stage STk-3 can be the same as the operation of the (k - 3)-th stage STk-3 during the fifth period P5. Therefore, a high-level output signal OUT[k - 3] can be output from the output terminal GOUT of the (k - 3)-th stage STk-3.

[0200] In the tenth period P10, the previous output signal OUT[k-4] at a low level can be supplied to the input terminal IN of the (k-3)-th stage STk-3. The first transistor T1 of the (k-3)-th stage STk-3 can be turned on by the first clock signal CLK1 at a low level. The second transistor T2 can be in a state of being turned on by the second voltage VGL at a low level. Due to the turned-on first transistor T1 and second transistor T2, the previous output signal OUT[k-4] at a low level can be transmitted to the first node A and the second node Q of the (k-3)-th stage STk-3, and the fifth transistor T5 can be turned on. Therefore, the second voltage VGL at a low level can be output as the output signal OUT[k-3] from the output terminal GOUT of the (k-3)-th stage STk-3. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be turned off, and the first voltage VGH at a high level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned off.

[0201] During the second period P2 to the ninth period P9, the previous output signal OUT[k-3] at a high level as a start signal from the (k-3)-th stage STk-3 can be supplied to the input terminal IN of the (k-2)-th stage STk-2.

[0202] In the second period P2, the first clock signal CLK1 at a low level is input to the clock terminal CK of the (k-2)-th stage STk-2, and thus, the first transistor T1 is turned off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 is turned on. Therefore, the second voltage VGL at a low level can be output as the (k-2)-th output signal OUT[k-2] from the output terminal GOUT. The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0203] In the third period P3, fourth period P4, and fifth period P5, a high-level first clock signal CLK1 is input to the clock terminal CK of the (k-2)-th stage STk-2, and thus, the first transistor T1 can be turned on. Due to the turned-on first transistor T1 and second transistor T2, the high-level previous output signal OUT[k-3] can be transmitted to the first node A and second node Q of the (k-2)-th stage STk-2, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0204] In the sixth period P6, a low-level first clock signal CLK1 is input to the clock terminal CK of the (k-2)-th stage STk-2, and thus, the first transistor T1 can be turned off. Since the first node A and second node Q maintain the high-level voltage in the fifth period P5 through the first capacitor C1, the fifth transistor T5 can remain turned off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0205] Since the operation of the (k-2)-th stage STk-2 during the seventh period P7 to ninth period P9 is the same as the operation of the (k-2)-th stage STk-2 during the third period P3 to fifth period P5, its detailed description is omitted.

[0206] In the tenth period P10, the previous output signal OUT[k-3] changes from high level to low level and is supplied to the input terminal IN of the (k-2)-th stage STk-2, but a low-level first clock signal CLK1 is input to the clock terminal CK of the (k-2)-th stage STk-2, causing the first transistor T1 to turn off. Therefore, regardless of the voltage level of the start signal, the operation of the (k-2)-th stage STk-2 can be the same as the operation of the (k-2)-th stage STk-2 during the sixth period P6. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0207] In the eleventh period P11, the previous output signal OUT[k-3] at a low level can be supplied to the input terminal IN of the (k-2)-th stage STk-2, and the first clock signal CLK1 at a high level can be input to the clock terminal CK. Due to the first clock signal CLK1 at a high level, the first transistor T1 can be turned on, and due to the turned-on first transistor T1 and the second transistor T2, the previous output signal OUT[k-3] at a low level can be transmitted to the first node A and the second node Q of the (k-2)-th stage STk-2, and the fifth transistor T5 can be turned on. Therefore, the second voltage VGL at a low level can be output as the output signal OUT[k-2] from the output terminal GOUT of the (k-2)-th stage STk-2. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be turned off, and the first voltage VGH at a high level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned off.

[0208] During the third period P3 to the tenth period P10, the previous output signal OUT[k-2] at a high level as a start signal from the (k-2)-th stage STk-2 can be supplied to the input terminal IN of the (k-1)-th stage STk-1. Since the operation of the (k-1)-th stage STk-1 during the third period P3 to the twelfth period P12 is the same as the operation of the (k-3)-th stage STk-3 during the first period P1 to the tenth period P10, its detailed description is omitted.

[0209] During the fourth period P4 to the eleventh period P11, the previous output signal OUT[k-1] at a high level as a start signal from the (k-1)-th stage STk-1 can be supplied to the input terminal IN of the k-th stage STk. Since the operation of the k-th stage STk during the fourth period P4 to the thirteenth period P13 is the same as the operation of the (k-2)-th stage STk-2 during the second period P2 to the eleventh period P11, its detailed description is omitted.

[0210] Fig.38 The stage group of the drive circuit DRV shown in Fig.39 is not limited to the stage group shown in Fig.38 In an embodiment, for example, the stage group of the drive circuit DRV shown in Figure 4 and Figure 7 in the P-stage PST shown in Figure 5 and Figures 8 to 10 in the N-stage NST shown in

[0211] Figures 41 to 55 is a diagram of the stage group of the drive circuit DRV according to other embodiments. Figures 41 to 55The drive circuit DRV shown in the figure may have a structure in which a group of stages in which P-stage PSTs and N-stage NSTs are alternately arranged is repeatedly arranged.

[0212] As Fig.41 shown, the group of stages may include Figure 4 the P-stage PST shown in Fig. 9 and the N-stage NST shown in

[0213] As Fig.42 shown, the group of stages may include Figure 4 the P-stage PST shown in Figure 8 and the N-stage NST shown in

[0214] As Fig.43 shown, the group of stages may include Figure 4 the P-stage PST shown in Fig.10 and the N-stage NST shown in

[0215] As Fig.44 shown, the group of stages may include Figure 7 the P-stage PST shown in Figure 5 and the N-stage NST shown in

[0216] As Fig.45 shown, the group of stages may include Figure 7 the P-stage PST shown in Figure 8 and the N-stage NST shown in

[0217] As Fig.46 shown, the group of stages may include Figure 7 the P-stage PST shown in Fig. 9 and the N-stage NST shown in

[0218] As Fig.47 shown, the group of stages may include Figure 7 the P-stage PST shown in Fig.10 and the N-stage NST shown in

[0219] Figures 48 to 55 is a diagram of a group of stages of the drive circuit DRV in which Fig.39 and Figure 41 to Figure 47 the transistors in are dual-gate transistors respectively.

[0220] Fig.56 is a schematic diagram of the drive circuit DRV according to another embodiment. Figure 57 to Figure 64 is Fig.56 a diagram of any group of stages among the multiple stages included in the drive circuit DRV of.

[0221] Fig.56 The drive circuit DRV shown in Fig.38The difference in the drive circuit DRV shown is that each stage further includes a node voltage output terminal QOUT configured to output the voltage of the second node Q (see Fig.57 ) as a corresponding one of the second carry signals QCR[1] to QCR[n], and the other configurations are the same.

[0222] In an embodiment, for example, Fig.56 the stage group of the drive circuit DRV shown in Figure 4 and Figure 7 can be composed of a combination of one of the P-stage PSTs shown in Fig.29 and Fig.30 and one of the N-stage NSTs shown in

[0223] As shown in Fig.57 the stage group may include Figure 4 the P-stage PST shown in Fig.29 and the N-stage NST shown in

[0224] As shown in Fig.58 the stage group may include Figure 4 the P-stage PST shown in Fig.30 and the N-stage NST shown in

[0225] As shown in Fig.59 the stage group may include Figure 7 the P-stage PST shown in Fig.29 and the N-stage NST shown in

[0226] As shown in Fig.60 the stage group may include Figure 7 the P-stage PST shown in Fig.30 and the N-stage NST shown in

[0227] In an embodiment, the transistors of the P-stage PST and the N-stage NST of the stage group may each be double-gate transistors including a first gate and a second gate, the first gate being a top gate disposed above the semiconductor, and the second gate being a bottom gate (back gate) disposed below the semiconductor. Figure 61 to Figure 64 is a diagram of a stage group of the drive circuit DRV in which Figures 57 to 60 the transistors are respectively double-gate transistors.

[0228] Fig.65 is a schematic diagram of the drive circuit DRV according to another embodiment. Fig.66 is Fig.65 a diagram of any stage group among the multiple stages included in the drive circuit DRV of Fig.67 is for describing Fig.66Timing diagram of driving of the stage group. Hereinafter, the description will mainly focus on configurations different from those described in the above embodiments.

[0229] Referring to Figure 65 to Figure 67 , the driving circuit DRV according to the embodiment may include a plurality of stages ST1 to STn. As Fig.66 shown in Fig.65 , the driving circuit DRV shown in Figure 4 may be a shift register in which the P-stage PST shown in Figure 5 and the N-stage NST shown in

[0230] are alternately arranged and cascaded. The clock signal CLK may be input to the clock terminal CK of each of the plurality of stages ST1 to STn. As Fig.67 shown in Fig.67 , the clock signal CLK may be a square wave signal that repeats a high-level voltage and a low-level voltage. In the embodiment, the clock signal CLK may be a square wave signal that repeats the first voltage VGH and the second voltage VGL. Fig.40 The frequency of the clock signal CLK shown in Fig.65 may be twice the frequency of the clock signal (such as the first clock signal CLK1 or the second clock signal CLK2) shown in

[0231] . In the clock signal CLK, the period during which the low-level voltage is maintained and the period during which the high-level voltage is maintained for one cycle may be the same. Compared with the above embodiment,

[0232] the driving circuit DRV shown in Fig.67 can reduce the number of wirings by using only one clock signal CLK, thereby reducing the wiring layout area. Fig.66 The stages ST1 to STn may be configured to shift the output signals OUT[1],..., OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k],..., and OUT[n] having a high-level voltage by 1 / 2 of a cycle of the clock signal CLK and sequentially output the output signals OUT[1],..., OUT[k - 3], OUT[k - 2], OUT[k - 1], OUT[k],..., and OUT[n].

[0233] During the first period P1 to the eighth period P8, the previous output signal OUT[k - 4] having a high level as a start signal may be supplied to the input terminal IN of the (k - 3)th stage STk - 3.

[0234] In the first period P1, a high-level clock signal CLK is input to the clock terminal CK of the (k-3)-th stage STk-3. Therefore, the first transistor T1 of the (k-3)-th stage STk-3 remains cut off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 is turned on. Therefore, a low-level second voltage VGL can be output from the output terminal GOUT as the (k-3)-th output signal OUT[k-3]. The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0235] In the second period P2, a low-level clock signal CLK is input to the clock terminal CK of the (k-3)-th stage STk-3. Therefore, the first transistor T1 of the (k-3)-th stage STk-3 can be turned on. Due to the turned-on first transistor T1 and second transistor T2, the high-level previous output signal OUT[k-4] can be transmitted to the first node A and the second node Q of the (k-3)-th stage STk-3, and the fifth transistor T5 can be cut off. The third transistor T3 whose gate is connected to the first node A can be cut off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0236] In the third period P3, a high-level clock signal CLK is input to the clock terminal CK of the (k-3)-th stage STk-3. Therefore, the first transistor T1 can be cut off. Since the first node A and the second node Q maintain the high-level voltage in the second period P2 through the first capacitor C1, the fifth transistor T5 can remain cut off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-3] can be output from the output terminal GOUT of the (k-3)-th stage STk-3.

[0237] Since the operation of the (k-3)-th stage STk-3 during the fourth period P4 to the ninth period P9 is the same as the repetition of the operation of the (k-3)-th stage STk-3 during the second period P2 and the third period P3, its detailed description is omitted.

[0238] In the ninth period P9, the previous output signal OUT[k - 4] transitions from a high level to a low level and is supplied to the input terminal IN of the (k - 3)-th stage STk-3. However, a high-level clock signal CLK is input to the clock terminal CK of the (k - 3)-th stage STk-3, causing the first transistor T1 to turn off. Therefore, regardless of the voltage level of the start signal, the operation of the (k - 3)-th stage STk-3 can be the same as its operation during the third period P3. Thus, a high-level output signal OUT[k - 3] can be output from the output terminal GOUT of the (k - 3)-th stage STk-3.

[0239] In the tenth period P10, the low-level previous output signal OUT[k - 4] can be supplied to the input terminal IN of the (k - 3)-th stage STk-3. The first transistor T1 of the (k - 3)-th stage STk-3 can be turned on by the low-level clock signal CLK. The second transistor T2 can be in a state of being turned on by the low-level second voltage VGL. Due to the turned-on first transistor T1 and second transistor T2, the low-level previous output signal OUT[k - 4] can be transmitted to the first node A and the second node Q of the (k - 3)-th stage STk-3, and the fifth transistor T5 can be turned on. Thus, a low-level second voltage VGL can be output from the output terminal GOUT of the (k - 3)-th stage STk-3 as the output signal OUT[k - 3]. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be turned off, and a high-level first voltage VGH can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned off.

[0240] During the second period P2 to the ninth period P9, the high-level previous output signal OUT[k - 3] from the (k - 3)-th stage STk-3, which serves as the start signal, can be supplied to the input terminal IN of the (k - 2)-th stage STk-2.

[0241] In the second period P2, a low-level clock signal CLK is input to the clock terminal CK of the (k - 2)-th stage STk-2. Therefore, the first transistor T1 turns off, the first node A and the second node Q maintain the same low-level voltage as in the previous period, and the fifth transistor T5 turns on. Thus, a low-level second voltage VGL can be output from the output terminal GOUT as the (k - 2) output signal OUT[k - 2]. The voltage of the third node QB can be a high-level voltage due to the turned-on third transistor T3.

[0242] In the third period P3, a high-level clock signal CLK is input to the clock terminal CK of the (k-2)-th stage STk-2, and thus, the first transistor T1 can be turned on. Due to the turned-on first transistor T1 and second transistor T2, the high-level previous output signal OUT[k-3] can be transmitted to the first node A and the second node Q of the (k-2)-th stage STk-2, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0243] In the fourth period P4, a low-level clock signal CLK is input to the clock terminal CK of the (k-2)-th stage STk-2, and thus, the first transistor T1 can be turned off. Since the first node A and the second node Q maintain the high-level voltage in the third period P3 through the first capacitor C1, the fifth transistor T5 can remain turned off. The fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0244] Since the operation of the (k-2)-th stage STk-2 during the fifth period P5 to the tenth period P10 is the same as the repetition of the operation of the (k-2)-th stage STk-2 during the third period P3 and the fourth period P4, its detailed description is omitted.

[0245] In the tenth period P10, the previous output signal OUT[k-3] changes from high level to low level and is supplied to the input terminal IN of the (k-2)-th stage STk-2, but a low-level clock signal CLK is input to the clock terminal CK of the (k-2)-th stage STk-2, causing the first transistor T1 to be turned off. Therefore, regardless of the voltage level of the start signal, the operation of the (k-2)-th stage STk-2 can be the same as the operation of the (k-2)-th stage STk-2 during the fourth period P4. Therefore, a high-level output signal OUT[k-2] can be output from the output terminal GOUT of the (k-2)-th stage STk-2.

[0246] In the eleventh period P11, the previous output signal OUT[k - 3] at a low level can be supplied to the input terminal IN of the (k - 2)-th stage STk - 2, and the clock signal CLK at a high level can be input to the clock terminal CK. Due to the clock signal CLK at a high level, the first transistor T1 can be turned on, and due to the turned-on first transistor T1 and the second transistor T2, the previous output signal OUT[k - 3] at a low level can be transmitted to the first node A and the second node Q of the (k - 2)-th stage STk - 2, and the fifth transistor T5 can be turned on. Therefore, the second voltage VGL at a low level can be output as the output signal OUT[k - 2] from the output terminal GOUT of the (k - 2)-th stage STk - 2. The third transistor T3 whose gate is connected to the first node A can be turned on, the fourth transistor T4 whose gate is connected to the second node Q can be turned off, and the first voltage VGH at a high level can be transmitted to the third node QB. The sixth transistor T6 whose gate is connected to the third node QB can be turned off.

[0247] During the third period P3 to the tenth period P10, the previous output signal OUT[k - 2] at a high level as a start signal from the (k - 2)-th stage STk - 2 can be supplied to the input terminal IN of the (k - 1)-th stage STk - 1. Since the operation of the (k - 1)-th stage STk - 1 during the third period P3 to the twelfth period P12 is the same as the operation of the (k - 3)-th stage STk - 3 during the first period P1 to the tenth period P10, its detailed description is omitted.

[0248] During the fourth period P4 to the eleventh period P11, the previous output signal OUT[k - 1] at a high level as a start signal from the (k - 1)-th stage STk - 1 can be supplied to the input terminal IN of the k-th stage STk. Since the operation of the k-th stage STk during the fourth period P4 to the thirteenth period P13 is the same as the operation of the (k - 2)-th stage STk - 2 during the second period P2 to the eleventh period P11, its detailed description is omitted.

[0249] Fig.65 The group of stages of the driving circuit DRV shown in Fig.66 is not limited to the group of stages shown in Fig.65 In an embodiment, for example, the group of stages of the driving circuit DRV shown in Figure 4 and Figure 7 can be composed of one of the P-stage PSTs shown in Figure 5 and Figures 8 to 10 and one of the N-stage NSTs shown in

[0250] Figures 68 to 82 is a diagram of a group of stages of the driving circuit DRV according to other embodiments. Figures 68 to 74The drive circuit DRV shown in [description] may have a structure in which a group of stages in which P-stage PSTs and N-stage NSTs are alternately arranged is repeatedly arranged.

[0251] As Fig.68 shown, the group of stages may include Figure 4 the P-stage PST shown in [description] and Fig. 9 the N-stage NST shown in [description].

[0252] As Fig.69 shown, the group of stages may include Figure 4 the P-stage PST shown in [description] and Figure 8 the N-stage NST shown in [description].

[0253] As Fig.70 shown, the group of stages may include Figure 4 the P-stage PST shown in [description] and Fig.10 the N-stage NST shown in [description].

[0254] As Fig.71 shown, the group of stages may include Figure 7 the P-stage PST shown in [description] and Figure 5 the N-stage NST shown in [description].

[0255] As Fig.72 shown, the group of stages may include Figure 7 the P-stage PST shown in [description] and Figure 8 the N-stage NST shown in [description].

[0256] As Fig.73 shown, the group of stages may include Figure 7 the P-stage PST shown in [description] and Fig. 9 the N-stage NST shown in [description].

[0257] As Fig.74 shown, the group of stages may include Figure 7 the P-stage PST shown in [description] and Fig.10 the N-stage NST shown in [description].

[0258] Figures 75 to 82 is a diagram of a group of stages of the drive circuit DRV in which Fig.66 and Figures 68 to 74 the transistors in [description] are dual-gate transistors respectively.

[0259] Fig.83 is a schematic diagram of the drive circuit DRV according to another embodiment. Figures 84 to 91 is Fig.83 a diagram of any group of stages included among the multiple stages included in the drive circuit DRV of [description].

[0260] Fig.83 The drive circuit DRV shown in [description] and Fig.65The difference in the drive circuit DRV shown is that each stage further includes a node voltage output terminal QOUT configured to output the voltage of the second node Q (see Fig.84 ) as a corresponding one of the second carry signals QCR[1] to QCR[n], and the other configurations are the same.

[0261] In an embodiment, for example, Fig.83 the stage group of the drive circuit DRV shown in Figure 4 and Figure 7 can be composed of a combination of one of the P-stage PSTs shown in Fig.29 and Fig.30 and one of the N-stage NSTs shown in

[0262] As shown in Fig.84 , the stage group may include Figure 4 the P-stage PST shown in Fig.29 and the N-stage NST shown in

[0263] As shown in Fig.85 , the stage group may include Figure 4 the P-stage PST shown in Fig.30 and the N-stage NST shown in

[0264] As shown in Fig.86 , the stage group may include Figure 7 the P-stage PST shown in Fig.29 and the N-stage NST shown in

[0265] As shown in Fig.87 , the stage group may include Figure 7 the P-stage PST shown in Fig.30 and the N-stage NST shown in

[0266] In an embodiment, the transistors of the P-stage PST and the N-stage NST of the stage group may each be double-gate transistors including a first gate and a second gate, where the first gate is a top gate disposed above the semiconductor, and the second gate is a bottom gate (back gate) disposed below the semiconductor. Figures 88 to 91 is a diagram of the stage group of the drive circuit DRV in which Figure 84 to Figure 87 the transistors are double-gate transistors respectively.

[0267] Fig.92 is a diagram of the clock signal CLK (see Fig.91 ) according to an embodiment.

[0268] As shown in Fig.92 , it is possible to control the input to the drive circuit DRV (see Fig.91) The transition rate of the clock signal CLK. By controlling the transition rate, the slopes of the rising edge and the falling edge of the clock signal CLK can be controlled within the control period SP.

[0269] Fig.93 is a schematic diagram of the display device 10 according to an embodiment.

[0270] Referring to Fig.93 , the display device 10 according to an embodiment may include a pixel region 110, a gate driving circuit 130, a data driving circuit 150, and a controller 170.

[0271] A plurality of pixels PX and signal lines may be arranged in the pixel region 110, and electrical signals may be input to the plurality of pixels PX via the signal lines.

[0272] The plurality of pixels PX may be repeatedly arranged in a first direction (e.g., the x-direction or the row direction) and a second direction (e.g., the y-direction or the column direction). The plurality of pixels PX may be arranged in various forms such as a stripe arrangement, an arrangement, a diamond arrangement, and a mosaic arrangement to generate an image. Each of the plurality of pixels PX includes an organic light-emitting diode as a display element, and the organic light-emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor.

[0273] In an embodiment, the plurality of transistors included in the pixel circuit may be N-type oxide transistors. The oxide transistors may include an oxide semiconductor, and the oxide semiconductor is a material based on zinc oxide and may include zinc oxide, indium (In)-zinc oxide, or indium (In)-gallium (Ga)-zinc oxide, etc. In some embodiments, the oxide semiconductor may include an IGZO semiconductor. In some embodiments, the oxide semiconductor may include an ITGZO semiconductor. In an embodiment, for example, the oxide transistors may include LTPO thin-film transistors.

[0274] In another embodiment, some of the plurality of transistors included in the pixel circuit may be N-type oxide transistors, and the other transistors of the plurality of transistors may be P-type silicon transistors. The silicon transistors may include a silicon semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. In an embodiment, for example, the silicon transistors may include LTPS thin-film transistors.

[0275] The signal lines through which electrical signals can be input to the plurality of pixels PX may include a plurality of gate lines GL1, GL2, ……, and GLn extending in a first direction and a plurality of data lines DL1, DL2, ……, and DLm extending in a second direction, where n is a positive integer and m is a positive integer. The plurality of gate lines GL1 to GLn may be arranged to be spaced apart in the second direction and may be configured to transmit gate signals to the pixels PX. The plurality of data lines DL1 to DLm may be arranged to be spaced apart in the first direction and may be configured to transmit data signals to the pixels PX. Each of the plurality of pixels PX may be connected to at least one corresponding gate line among the plurality of gate lines GL1 to GLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each pixel PX may be configured to receive a data signal from the corresponding data line when a gate signal is supplied through the corresponding gate line.

[0276] The gate driving circuit 130 may be connected to the plurality of gate lines GL1 to GLn and may be configured to generate a gate signal in response to a gate driving control signal GCS from the controller 170 and sequentially supply the gate signal to the gate lines GL1 to GLn. The gate lines GL1 to GLn may be connected to the gates of the transistors included in the pixels PX, and the gate signal may be a gate control signal for controlling the on and off of the transistors to which the gate lines are connected. The gate signal may include a gate on voltage that can turn on the transistor and a gate off voltage that can turn off the transistor.

[0277] The data driving circuit 150 may be connected to the plurality of data lines DL1 to DLm and may be configured to supply data signals to the data lines DL1 to DLm in response to a data driving control signal DCS from the controller 170. The data signals supplied to the data lines DL1 to DLm may be supplied to the pixels PX to which the gate signals are supplied.

[0278] When the display device 10 is an organic light emitting display device, a first power voltage ELVDD and a second power voltage ELVSS may be supplied to the pixels PX in the pixel region 110. The first power voltage ELVDD may be a high level voltage provided to one terminal of a driving transistor connected to a first electrode (e.g., a pixel electrode or an anode) of an organic light emitting diode of each pixel PX. The second power voltage ELVSS may be a low level voltage provided to a second electrode (e.g., a counter electrode or a cathode) of the organic light emitting diode connected to the other terminal of the driving transistor. The first power voltage ELVDD and the second power voltage ELVSS may be driving voltages for causing the plurality of pixels PX to emit light.

[0279] The controller 170 may be configured to generate a gate drive control signal GCS and a data drive control signal DCS based on a signal input from the outside. The controller 170 may be configured to supply the gate drive control signal GCS to the gate drive circuit 130 and supply the data drive control signal DCS to the data drive circuit 150.

[0280] In an embodiment, the gate drive circuit 130 may be implemented with Figures 1 to 91 the drive circuit DRV using a two-level triggering scheme shown in. In an embodiment, for example, the gate signal output by the gate drive circuit 130 to each gate line GL may correspond to the output signal OUT output by each of the multiple stages ST1 to STn of the drive circuit DRV shown in Figures 1 to 91 to the signal line. The number of stages constituting the gate drive circuit 130 to which the drive circuit DRV according to one or more embodiments is applied may be variously modified according to the number of rows (horizontal lines) provided in the pixel region 110.

[0281] Each of the stages ST1 to STn may be connected to the gate line arranged in the corresponding row of the pixel region 110. Each of the stages ST1 to STn may be configured to generate a gate signal and output the gate signal to the connected gate line GL. That is, each of the stages ST1 to STn may be configured to supply the gate signal to the gate line GL provided in the corresponding row.

[0282] The display device 10 according to an embodiment may include a display device such as an organic light emitting display device, an inorganic light emitting display device (or an inorganic electroluminescence (“EL”) display device), and a quantum dot light emitting display device.

[0283] By applying the drive circuit DRV using a two-level triggering scheme (which operates multiple stages by using P-channel transistors and N-channel transistors turned on by signals of different voltage levels) to the gate drive circuit 130, compared with a drive circuit including only P-stages, the clock frequency can be reduced to approximately 1 / 2, thereby reducing the power consumption of the display device 10.

[0284] In addition, by applying the drive circuit DRV in which multiple stages are alternately arranged in a pair of P-stages and a pair of N-stages to the gate drive circuit 130, an error in which adjacent stages in the arrangement where one P-stage and one N-stage are alternately arranged operate simultaneously can be significantly reduced.

[0285] Furthermore, when the drive circuit DRV in which P-stages and N-stages use one clock signal is applied to the gate drive circuit 130, the clock lines are reduced, so that the non-display area of the display device 10 can be reduced.

[0286] In addition, since the first transistor T1 of the N-th stage is implemented as a dual-gate transistor having a plurality of sub-transistors connected in series in the gate driving circuit 130, the low leakage current effect of the oxide transistor and the reliability of the low-frequency operation of the display device 10 can be ensured.

[0287] A display device according to some embodiments of the present disclosure may be a device that displays video or still images and may visually provide information to a user. The display device may be used as a display screen of various electronic devices (such as a television, a notebook computer, a monitor, a broadcast panel, and an Internet of Things (IoT) device) and portable electronic devices (such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC)). In addition, a display device according to an embodiment may be used in wearable electronic devices (such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD)). In addition, a display device according to an embodiment may be used as an electronic device, such as a central information display (CID) located on the dashboard of a vehicle or the central fascia or dashboard of a vehicle, an in-vehicle rearview mirror display that replaces a side rearview mirror of a vehicle, or a display provided on the back surface of a front seat of a vehicle as an entertainment device for a rear seat. In addition, the display device may be a flexible device.

[0288] As described above, one or more embodiments have been described with reference to the accompanying drawings, but these embodiments should be considered only in a descriptive sense. Those of ordinary skill in the art will understand that various modifications and changes can be made to the embodiments. Therefore, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

[0289] A display device to which a driving circuit according to one or more embodiments is applied can reduce power consumption while reducing the area of a non-display region. The effects of one or more embodiments are not limited to those described above and can be extended in various ways without departing from the spirit of one or more embodiments.

[0290] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of the features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes can be made in form and detail without departing from the spirit and scope as defined by the appended claims.

Claims

1. A driving circuit, comprising a pair of first stages and a pair of second stages arranged alternately, wherein: Each of the pair of first stages and the pair of second stages comprises: a first transistor connected between the first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; an inverter connected between the second terminal and a third terminal to which the second voltage is supplied, the inverter being configured to control the voltage of the third node to be a voltage obtained by inverting the voltage level of the first node or the voltage level of the second node; a pull-down transistor connected between the output terminal and the second terminal, the pull-down transistor including a gate connected to the second node; and a pull-up transistor connected between the third terminal and the output terminal, the pull-up transistor including a gate connected to the third node, wherein the first transistor of each of the pair of first stages is a P-channel transistor, and The first transistor of each of the pair of second stages is an N-channel transistor.

2. The driving circuit according to claim 1, wherein: The second voltage is greater than the first voltage.

3. The driving circuit according to claim 1, wherein: The clock signal includes a first clock signal and a second clock signal, the first clock signal is input to the clock terminal of the odd-numbered first stage among the pair of first stages and the clock terminal of the odd-numbered second stage among the pair of second stages, The second clock signal is input to the clock terminal of the even-numbered first stage among the pair of first stages and the clock terminal of the even-numbered second stage among the pair of second stages, and The second clock signal is phase-shifted by 1 / 4 cycle relative to the first clock signal.

4. The driving circuit according to claim 1, wherein: The inverter of each of the pair of first stages and the pair of second stages comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the second node.

5. The driving circuit according to claim 1, wherein: The inverter of each stage of the pair of first stages comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the first node.

6. The driving circuit according to claim 5, wherein: The fourth transistor of each of the pair of first stages further includes a back gate connected to the second node, Each of the pair of first stages further includes a fifth transistor connected between the third terminal and the first node, the fifth transistor including a gate connected to a reset terminal.

7. The driving circuit according to claim 1, wherein: The inverter of each stage of the pair of second stages comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the second node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the second node.

8. The driving circuit according to claim 7, wherein: The first transistor of each of the pair of second stages includes a pair of sub-transistors connected in series, The pair of sub-transistors connected in series includes a first sub-transistor and a second sub-transistor, The first sub-transistor further includes a back gate configured to receive a voltage of the second node of a previous stage, and The second sub-transistor further includes a back gate configured to receive a voltage of the second node of a current stage.

9. The driving circuit according to claim 1, wherein: The inverter of each stage of the pair of second stages comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node, and The first transistor of each of the pair of second stages includes a pair of sub-transistors connected in series.

10. The driving circuit according to claim 9, wherein: The pair of serially connected sub-transistors includes a first sub-transistor and a second sub-transistor, The first sub-transistor further includes a back gate configured to receive a voltage of the second node of a previous stage, and The second sub-transistor further includes a back gate configured to receive a voltage of the second node of a current stage.

11. A driving circuit, comprising a first stage and a second stage arranged alternately, wherein: Each of the first level and the second level comprises: a first transistor connected between the first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; an inverter connected between the second terminal and a third terminal to which the second voltage is supplied, the inverter being configured to control the voltage of the third node to be a voltage obtained by inverting the voltage level of the first node or the voltage level of the second node; a pull-down transistor connected between the output terminal and the second terminal, the pull-down transistor including a gate connected to the second node; and a pull-up transistor connected between the third terminal and the output terminal, the pull-up transistor including a gate connected to the third node, wherein the first transistor of the first stage is a P-channel transistor, and The first transistor of the second stage is an N-channel transistor.

12. The driving circuit according to claim 11, wherein: The second voltage is greater than the first voltage.

13. The driving circuit according to claim 11, wherein: The driving circuit is configured to repeat the first stage group and the second stage group, Each of the first stage group and the second stage group includes an odd-numbered first stage and an even-numbered second stage, The clock signal includes a first clock signal and a second clock signal, The first clock signal is input to the clock terminal of the odd-numbered first stage in the first stage group and the clock terminal of the even-numbered second stage in the first stage group, The second clock signal is input to the clock terminal of the odd-numbered first stage in the second stage group and the clock terminal of the even-numbered second stage in the second stage group, and The second clock signal is phase-shifted by 1 / 2 cycle relative to the first clock signal.

14. The driving circuit according to claim 11, wherein: The inverter of each of the first stage and the second stage comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the second node.

15. The driving circuit according to claim 11, wherein: The inverter of the first stage comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the first node.

16. The driving circuit according to claim 15, wherein: The fourth transistor of the first stage further includes a back gate connected to the second node, The first stage further includes a fifth transistor connected between the third terminal and the first node, and the fifth transistor includes a gate connected to a reset terminal.

17. The driving circuit according to claim 11, wherein: The inverter of the second stage comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the second node; and A fourth transistor is connected between the third node and the second terminal, and includes a gate connected to the second node.

18. The driving circuit according to claim 17, wherein: The first transistor of the second stage includes a pair of sub-transistors connected in series, The pair of sub-transistors connected in series includes a first sub-transistor and a second sub-transistor, The first sub-transistor further includes a back gate configured to receive a voltage of the second node of a previous stage, and The second sub-transistor further includes a back gate configured to receive a voltage of the second node of a current stage.

19. The driving circuit according to claim 11, wherein: The inverter of the second stage comprises: a third transistor connected between the third terminal and the third node, the third transistor including a gate connected to the first node; and a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the second node, and The first transistor of the second stage includes a pair of sub-transistors connected in series.

20. The driving circuit according to claim 19, wherein: The pair of serially connected sub-transistors includes a first sub-transistor and a second sub-transistor, The first sub-transistor further includes a back gate configured to receive a voltage of the second node of a previous stage, and The second sub-transistor further includes a back gate configured to receive a voltage of the second node of a current stage.

21. The driving circuit according to claim 11, wherein: A clock signal input to the clock terminal of the first stage and a clock signal input to the clock terminal of the second stage are identical to each other.

22. A driving circuit, the driving circuit comprising a plurality of stages, wherein: The first of the plurality of stages comprises: a first transistor connected between the first node and a first terminal to which a start signal is input, the first transistor including a gate connected to a first clock terminal to which a clock signal is input; a second transistor connected between the first node and a second node, the second transistor including a gate connected to a second terminal to which a first voltage is supplied; a third transistor connected between a third node and a third terminal to which a second voltage higher than the first voltage is supplied, the third transistor including a gate connected to the first node; a fourth transistor connected between the third node and the second terminal, the fourth transistor including a gate connected to the first node; a fifth transistor connected between the first output terminal and the second terminal, the fifth transistor including a gate connected to the second node; a sixth transistor connected between the third terminal and the first output terminal, the sixth transistor including a gate connected to the third node; and a seventh transistor connected between the third terminal and the first node, the seventh transistor including a gate connected to a reset terminal, wherein the third transistor is a P-channel transistor, and The fourth transistor is an N-channel transistor.

23. The driving circuit according to claim 22, wherein: Among the plurality of stages, a second stage sequentially connected to the first stage includes: an eighth transistor connected between the fourth node and a fourth terminal to which the output signal output from the first stage is input, the eighth transistor including a gate connected to a second clock terminal to which a clock signal is input; a ninth transistor connected between the fourth node and the fifth node, the ninth transistor including a gate connected to a fifth terminal to which the first voltage is supplied; a tenth transistor connected between the sixth node and a sixth terminal to which the second voltage is supplied, the tenth transistor including a gate connected to the fifth node; an eleventh transistor connected between the sixth node and the fifth terminal, the eleventh transistor including a gate connected to the fifth node; a twelfth transistor connected between the second output terminal and the fifth terminal, the twelfth transistor including a gate connected to the fifth node; and a thirteenth transistor connected between the sixth terminal and the second output terminal, the thirteenth transistor including a gate connected to the sixth node, wherein the tenth transistor is a P-channel transistor, and The eleventh transistor is an N-channel transistor.

24. The driving circuit according to claim 23, wherein: The eighth transistor includes a pair of sub-transistors connected in series, The pair of serially connected sub-transistors includes a first sub-transistor and a second sub-transistor, The first sub-transistor further includes a back gate configured to receive a voltage of the second node of the first stage, and The second sub-transistor further includes a back gate configured to receive a voltage of the fifth node of the second stage.

25. The driving circuit according to claim 23, wherein: The first level also includes: a first capacitor connected between the second node and the first output terminal; and a second capacitor connected between the third terminal and the third node, and The second level also includes: a third capacitor connected between the fifth node and the second output terminal; and a fourth capacitor connected between the sixth terminal and the sixth node, Wherein, the first transistor is a P-channel transistor, and the eighth transistor is an N-channel transistor.

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