Read circuit of SOT-MRAM memory

Abstract

The invention provides a read circuit of an SOT-MRAM memory, and the read circuit comprises a memory cell and a reference cell used for providing reference resistance or a reference cell array composed of a plurality of reference cells, the memory cell comprises a first SOT track layer and a first magnetic tunnel junction, the first magnetic tunnel junction comprises a first free layer, a first barrier layer and a first reference layer which are stacked in sequence, the magnetic moments of the first reference layer and the first free layer are parallel to the y direction of the x-y plane, the reference unit comprises a second SOT track layer and a second magnetic tunnel junction, and the second magnetic tunnel junction has the same thin film structure as the first magnetic tunnel junction. Comprising a second free layer, a second barrier layer and a second reference layer, the magnetic moment of the second reference layer is parallel to the y direction of the x-y plane, and the magnetic moment of the second free layer is parallel to the x direction of the x-y plane. According to the invention, adverse effects on the read window caused by temperature and process floating can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memory, and in particular to a read circuit of a SOT-MRAM memory. Background Art

[0002] Spin-Orbit-Torque Magnetoresistive Random Access Memory (SOT-MRAM) has the characteristics of high speed, low power consumption, and high reliability, and has strong application potential. The SOT-MRAM storage cell includes a SOT track layer that provides Spin-Orbit-Torque (SOT) and a Magnetic Tunnel Junction (MTJ). The MTJ free layer can be changed by means of a magnetic field or a current. When the magnetic moments on both sides of the barrier layer are parallel, it presents a low resistance state (R P ), and when the magnetic moments on both sides of the barrier layer are antiparallel, it presents a high resistance state (R AP ). The low resistance state and the high resistance state can respectively correspond to data 0 or 1.

[0003] When reading the data of the SOT-MRAM storage cell, a reference resistor R Ref is required. By comparing the resistance of the storage cell with the reference resistor R Ref , the data of the storage cell is obtained. The reference resistor R Ref generally takes a value around (R P + R AP ) / 2 to maximize the read window. The prior art generally uses a fixed resistor as the reference resistor. The fixed resistor has good stability, but it is greatly affected by process fluctuations. In addition to the influence of process fluctuations, as Figure 1 shows, the fixed resistor has the characteristic of increasing with the increase of temperature. When the magnetic moments of the MTJ free layer and the reference layer are antiparallel, the resistance value of R AP will decrease with the increase of temperature, resulting in a smaller read window or even a reading error. Therefore, how to design the reference resistor is crucial for data reading. Summary of the Invention

[0004] In view of this, the present invention provides a read circuit of a SOT-MRAM memory, which can reduce the adverse effects of temperature and process fluctuations on the read window.

[0005] The present invention provides a read circuit of a SOT-MRAM memory, including: a storage cell and a reference unit for providing a reference resistor or a reference unit array composed of a plurality of the reference units, wherein,

[0006] The storage unit includes a first SOT track layer and a first magnetic tunnel junction located on the first SOT track layer. The thin film structure of the first magnetic tunnel junction includes a first free layer, a first barrier layer, and a first reference layer stacked in sequence. The magnetic moment of the first reference layer is parallel to the y direction of the x-y plane, and the magnetic moment of the first free layer is parallel to the y direction of the x-y plane;

[0007] The reference unit includes a second SOT track layer and a second magnetic tunnel junction located on the second SOT track layer. The second magnetic tunnel junction has the same thin film structure as the first magnetic tunnel junction, including a second free layer, a second barrier layer, and a second reference layer stacked in sequence. The magnetic moment of the second reference layer is parallel to the y direction of the x-y plane, and the magnetic moment of the second free layer is parallel to the x direction of the x-y plane;

[0008] The x-y plane is parallel to the plane of each thin film layer of the first magnetic tunnel junction. The x direction is the direction in which a write current is applied in the first SOT track layer, and the y direction is perpendicular to the x direction.

[0009] Optionally, the reference unit array includes N columns * N rows of reference units. The N reference units in the same column are connected in series, and the N columns of reference units are connected in parallel, or the N reference units in the same row are connected in series, and the N rows of reference units are connected in parallel to provide a resistance value equivalent to that of one reference unit.

[0010] Optionally, the first magnetic tunnel junction and the second magnetic tunnel junction have shape anisotropy.

[0011] Optionally, the geometric shapes of the first magnetic tunnel junction and the second magnetic tunnel junction are both elliptical, and the ratio of the short axis to the long axis is between 1:2 and 1:5. The long axis direction of the first magnetic tunnel junction is parallel to the y direction, and the long axis direction of the second magnetic tunnel junction is parallel to the x direction.

[0012] Optionally, the geometric shapes of the first magnetic tunnel junction and the second magnetic tunnel junction are both rectangular, and the width-to-length ratio is between 1:2 and 1:5. The long side direction of the first magnetic tunnel junction is parallel to the y direction; the long side direction of the second magnetic tunnel junction is parallel to the x direction.

[0013] Optionally, the first magnetic tunnel junction further includes a first antiferromagnetic pinning layer located on the first reference layer for assisting in making the magnetic moment of the first reference layer parallel to the y direction of the x-y plane;

[0014] The second magnetic tunnel junction further includes a second antiferromagnetic pinning layer located on the second reference layer for assisting in making the magnetic moment of the second reference layer parallel to the y direction of the x-y plane.

[0015] Optionally, the materials of the first antiferromagnetic pinning layer and the second antiferromagnetic pinning layer are IrMn or PtMn.

[0016] Optionally, the storage unit is a three-terminal device, and the storage unit further includes a first top electrode located on the first reference layer, and a first bottom electrode and a second bottom electrode located at both ends below the first SOT track layer;

[0017] The reference unit is a three-terminal device, and the reference unit further includes a second top electrode located on the second reference layer, and a third bottom electrode and a fourth bottom electrode located at both ends below the second SOT track layer.

[0018] Optionally, the storage unit is a three-terminal device, and the storage unit further includes a third top electrode located on the first reference layer, and a fifth bottom electrode and a sixth bottom electrode located at both ends below the first SOT track layer;

[0019] The reference unit is a two-terminal device, and the reference unit further includes a fourth top electrode located on the second reference layer, and a seventh bottom electrode located below the second SOT track layer.

[0020] Optionally, the materials of the first SOT track layer and the second SOT track layer are materials with spin-orbit torque effect, selected from at least one of W, Ta, Pt, WTa, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe.

[0021] In the read circuit of the SOT-MRAM memory provided by the present invention, the magnetic moments of the free layer and the reference layer of the storage unit are arranged in parallel, and its resistance can be switched between the highest value R AP and the lowest value R P The balanced state of the reference unit is that the magnetic moments of the free layer and the reference layer are arranged perpendicular to each other, and the reference resistance provided by it is stably in the middle value of R AP and R P Moreover, the stacked structures of the reference unit and the storage unit are the same, so they are affected by process fluctuations in the same way and have the same temperature dependence. Therefore, the reference resistance provided by the reference unit can adaptively be in the middle value of the resistance, obtaining the best read window and reducing the adverse effects of temperature and process fluctuations on the read window. Description of the Drawings

[0022] Figure 1 It is a schematic diagram of the reduction of the read window caused by the increase of temperature in the prior art;

[0023] Figure 2 It is a schematic diagram of the overall structure of the read circuit of the SOT-MRAM memory according to an embodiment of the present invention;

[0024] Figure 3 Structural schematic diagram of a storage cell according to an embodiment of the present invention;

[0025] Figure 4 Structural schematic diagram of a reference cell according to an embodiment of the present invention;

[0026] Figure 5 Overall structural schematic diagram of a read circuit of an SOT - MRAM memory according to another embodiment of the present invention;

[0027] Figure 6 Schematic diagram showing the improvement of the read window of the embodiment of the present invention compared with the prior art;

[0028] Figure 7 Structural schematic diagram of the electrodes of a storage cell and a reference cell according to an embodiment of the present invention;

[0029] Figure 8 Structural schematic diagram of the electrodes of a storage cell and a reference cell according to another embodiment of the present invention. Detailed implementation manners

[0030] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above - mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so as to implement the embodiments of this application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0032] In this application, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe this application and its embodiments, and are not used to limit that the indicated device, element or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0033] Moreover, in addition to being used to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to the specific circumstances.

[0034] In addition, the terms "mounted", "arranged", "provided with", "connected", "coupled", "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there is an internal connection between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0035] The following will describe in detail some embodiments of the present invention with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] An embodiment of the present invention provides a read circuit for a SOT-MRAM memory. Refer to Figures 2 to 4 , Figure 2 which shows a schematic diagram of the overall structure of the read circuit. As Figure 2 shown, the read circuit includes a storage unit and a reference unit for providing a reference resistance. Of course, it also includes a read amplifier and other necessary circuit elements.

[0037] Figure 3 shows a schematic diagram of the storage unit structure. Figure 3 In (a) of Figure 3 is a schematic diagram of the stacked structure of the storage unit, and Figure 3As shown in (a) in [description], the storage unit includes a first SOT track layer 301 and a first magnetic tunnel junction 302 located on the first SOT track layer 301. The material of the first SOT track layer 301 is a material with spin-orbit torque effect, which can be selected from at least one of W, Ta, Pt, WTa, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe. The thin film structure of the first magnetic tunnel junction 302 includes a first free layer 3021, a first barrier layer 3022, and a first reference layer 3023 stacked in sequence. The first free layer 3021 and the first reference layer 3023 are magnetic thin films. The magnetic moment of the first reference layer 3023 is parallel to the y direction of the x-y plane, and the magnetic moment of the first free layer 3021 is parallel to the y direction of the x-y plane. Since the storage unit is readable and writable, the direction of the magnetic moment of the first free layer 3021 is variable, and the magnetic moments on both sides of the first barrier layer are arranged in parallel or antiparallel.

[0038] Figure 4 Fig. shows the structural schematic diagram of the reference unit. Figure 4 In (a) in [description], it is the schematic diagram of the stacked structure of the reference unit. Figure 4 In (b) in [description], it is the top view of the reference unit. As Figure 4 As shown in (a) in [description], the reference unit includes a second SOT track layer 401 and a second magnetic tunnel junction 402 located on the second SOT track layer 401. The material of the second SOT track layer 401 is a material with spin-orbit torque effect, which can be selected from at least one of W, Ta, Pt, WTa, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe. The second magnetic tunnel junction 402 has the same thin film structure as the first magnetic tunnel junction 302, including a second free layer 4021, a second barrier layer 4022, and a second reference layer 4023 stacked in sequence. The second free layer 4021 and the second reference layer 4023 are magnetic thin films. The magnetic moment of the second reference layer 4023 is parallel to the y direction of the x-y plane, and the magnetic moment of the second free layer 4021 is parallel to the x direction of the x-y plane. The reference unit is used to provide a reference resistance, and its resistance value should be kept stable and will not change after the magnetic moment direction is initialized.

[0039] In this embodiment, the x-y plane is the plane parallel to each layer of the thin film of the first magnetic tunnel junction. The x direction is the direction in which the write current is applied in the first SOT track layer during the write operation of the storage unit. It can also be considered that the x direction is the extending direction of the first SOT track layer. The y direction is perpendicular to the x direction, and the z direction is the direction perpendicular to the surface of the thin film.

[0040] In one embodiment, the first magnetic tunnel junction 302 and the second magnetic tunnel junction 402 have shape anisotropy. As Figure 3As shown in (b) therein, the first magnetic tunnel junction 302 is elliptical in shape, with the ratio of the minor axis to the major axis being between 1:2 and 1:5, and the major axis direction being parallel to the y direction.

[0041] As Figure 4 shown in (b) therein, the second magnetic tunnel junction 402 has the same shape as the first magnetic tunnel junction 302, which is also elliptical, with the ratio of the minor axis to the major axis being between 1:2 and 1:5. However, the major axis direction of the second magnetic tunnel junction 402 is parallel to the x direction.

[0042] Similarly, in another embodiment, the first magnetic tunnel junction is rectangular in shape, with the width-to-length ratio being between 1:2 and 1:5, and the long side direction being parallel to the y direction.

[0043] The second magnetic tunnel junction has the same shape as the first magnetic tunnel junction, which is also rectangular, with the width-to-length ratio being between 1:2 and 1:5. However, the long side direction of the second magnetic tunnel junction is parallel to the x direction.

[0044] Furthermore, in one embodiment, the first magnetic tunnel junction 302 of the storage unit further includes a first antiferromagnetic pinning layer (not shown in the figure), which is located on the first reference layer 3023 and is used to assist in making the magnetic moment of the first reference layer 3023 parallel to the y direction of the x-y plane. Specifically, the storage unit adopts an annealing method with a magnetic field during annealing, the annealing temperature is higher than the Blocking temperature of the first antiferromagnetic pinning layer, and the magnetic field direction is parallel to the y direction, so that the magnetic moment of the first reference layer is parallel to the y direction after annealing.

[0045] The second magnetic tunnel junction 402 of the reference unit further includes a second antiferromagnetic pinning layer (not shown in the figure), which is located on the second reference layer 4023 and is used to assist in making the magnetic moment of the second reference layer 4023 parallel to the y direction of the x-y plane. Specifically, the reference unit adopts an annealing method with a magnetic field during annealing, the annealing temperature is higher than the Blocking temperature of the second antiferromagnetic pinning layer, and the magnetic field direction is parallel to the y direction, so that the magnetic moment of the second reference layer is parallel to the y direction after annealing.

[0046] The materials of the first antiferromagnetic pinning layer and the second antiferromagnetic pinning layer are IrMn or PtMn.

[0047] As can be seen from the above, by utilizing the characteristics of shape anisotropy and antiferromagnetic pinning, the storage unit and the reference unit have the desired magnetic moment directions. The magnetic moments of the free layer and the reference layer of the reference unit are stably in a perpendicular arrangement, and no initialization operation is required. The resistance value of the reference unit remains at the optimal intermediate value.

[0048] To further avoid the influence on a single reference unit due to process fluctuations, as Figure 5As shown, a reference unit array can be used to provide a reference resistance. The reference unit array is composed of multiple reference units. For example, the reference unit array includes N columns * N rows of reference units. The N reference units located in the same column are connected in series, and the N columns of reference units are connected in parallel. Alternatively, the N reference units located in the same row are connected in series, and the N rows of reference units are connected in parallel to provide a resistance equivalent to that of one reference unit. Each reference unit can refer to the foregoing embodiments and will not be elaborated here.

[0049] In the read circuit of the SOT-MRAM memory provided by the embodiment of the present invention, the magnetic moments of the free layer and the reference layer of the storage unit are arranged in parallel, and its resistance can be at the highest value R AP and the lowest value R P to switch. The balanced state of the reference unit is that the magnetic moments of the free layer and the reference layer are arranged perpendicular to each other. According to existing theoretical derivations, the reference resistance provided by it is stably at the intermediate value between R AP and R P , that is, the resistance value is (R P +R AP ) / 2, meeting the requirements of the reference resistance. Moreover, the stack structure of the reference unit and the storage unit is the same, so they are affected by process fluctuations in the same way and have the same temperature dependence. Therefore, the reference resistance provided by the reference unit can adaptively be at the intermediate resistance value, obtaining the best read window and reducing the adverse effects of temperature and process fluctuations on the read window. As Figure 6 shown, when the temperature rises, the read window will not become smaller. By comparing the resistance values of the reference unit and the storage unit, the data of the storage unit is obtained.

[0050] Furthermore, considering the external connections of the storage unit and the reference unit, in one embodiment, as Figure 7 shown, the storage unit is a three-terminal device. On the basis of (a) in Figure 3 , the storage unit further includes a first top electrode 303 located on the first reference layer 3023 and first bottom electrodes 3001 and second bottom electrodes 3002 located at both ends below the first SOT track layer 301;

[0051] The reference unit is a three-terminal device. On the basis of (a) in Figure 4 , the reference unit further includes a second top electrode 403 located on the second reference layer 4023 and third bottom electrodes 4001 and fourth bottom electrodes 4002 located at both ends below the second SOT track layer 401.

[0052] In another embodiment, as Figure 8 shown, the storage unit is a three-terminal device. On the basis of Figure 3On the basis of (a) above, the storage unit further includes a third top electrode 310 located on the first reference layer 3023, and a fifth bottom electrode 3003 and a sixth bottom electrode 3004 located at both ends below the first SOT track layer 301;

[0053] The reference unit is an end-type device. On the basis of (a) in Figure 4 above, the reference unit further includes a fourth top electrode 410 located on the second reference layer 4023, and a seventh bottom electrode 4003 located below the second SOT track layer 401.

[0054] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A read circuit for a SOT-MRAM memory, characterized in that, Comprising: A storage unit and a reference unit for providing a reference resistance or a reference unit array composed of a plurality of the reference units, wherein the storage unit includes a first SOT track layer and a first magnetic tunnel junction located on the first SOT track layer, and the thin film structure of the first magnetic tunnel junction includes a first free layer, a first barrier layer, and a first reference layer stacked in sequence. The magnetic moment of the first reference layer is parallel to the y direction of the x-y plane, and the magnetic moment of the first free layer is parallel to the y direction of the x-y plane; the reference unit includes a second SOT track layer and a second magnetic tunnel junction located on the second SOT track layer. The second magnetic tunnel junction has the same thin film structure as the first magnetic tunnel junction, including a second free layer, a second barrier layer, and a second reference layer stacked in sequence. The magnetic moment of the second reference layer is parallel to the y direction of the x-y plane, and the magnetic moment of the second free layer is parallel to the x direction of the x-y plane; the x-y plane is a plane parallel to each thin film layer of the first magnetic tunnel junction, the x direction is the direction in which a write current is applied in the first SOT track layer, and the y direction is perpendicular to the x direction.

2. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The reference unit array includes N columns * N rows of reference units. The N reference units located in the same column are connected in series, and the N columns of reference units are connected in parallel, or the N reference units located in the same row are connected in series, and the N rows of reference units are connected in parallel to provide a resistance value equivalent to that of one reference unit.

3. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The first magnetic tunnel junction and the second magnetic tunnel junction have shape anisotropy.

4. The read circuit for a SOT-MRAM memory according to claim 3, characterized in that, The geometric shapes of the first magnetic tunnel junction and the second magnetic tunnel junction are both elliptical, and the ratio of the short axis to the long axis is between 1:2 and 1:

5. The long axis direction of the first magnetic tunnel junction is parallel to the y direction, and the long axis direction of the second magnetic tunnel junction is parallel to the x direction.

5. The read circuit for a SOT-MRAM memory according to claim 3, characterized in that, The geometric shapes of the first magnetic tunnel junction and the second magnetic tunnel junction are both rectangular, and the width-to-length ratio is between 1:2 and 1:

5. The long side direction of the first magnetic tunnel junction is parallel to the y direction; the long side direction of the second magnetic tunnel junction is parallel to the x direction.

6. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The first magnetic tunnel junction further includes a first antiferromagnetic pinning layer located on the first reference layer, which is used to assist in making the magnetic moment of the first reference layer parallel to the y direction of the x-y plane; The second magnetic tunnel junction further includes a second antiferromagnetic pinning layer located on the second reference layer, which is used to assist in making the magnetic moment of the second reference layer parallel to the y direction of the x-y plane.

7. The read circuit for a SOT-MRAM memory according to claim 6, characterized in that, The materials of the first antiferromagnetic pinning layer and the second antiferromagnetic pinning layer are IrMn or PtMn.

8. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The storage unit is a three-terminal device. The storage unit further includes a first top electrode located on the first reference layer and a first bottom electrode and a second bottom electrode located at both ends below the first SOT track layer; The reference unit is a three-terminal device. The reference unit further includes a second top electrode located on the second reference layer and a third bottom electrode and a fourth bottom electrode located at both ends below the second SOT track layer.

9. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The storage unit is a three-terminal device, and the storage unit further includes a third top electrode located on the first reference layer and a fifth bottom electrode and a sixth bottom electrode located at both ends below the first SOT track layer; The reference unit is a two-terminal device, and the reference unit further includes a fourth top electrode located on the second reference layer and a seventh bottom electrode located below the second SOT track layer.

10. The read circuit for a SOT-MRAM memory according to claim 1, characterized in that, The materials of the first SOT track layer and the second SOT track layer are materials with spin-orbit torque effect, selected from at least one of W, Ta, Pt, WTa, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe.

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