Method for forming semiconductor element and semiconductor element
By using HARP and HDP processes to deposit oxidized materials in the isolation area of semiconductor components, the problem of oxidized materials being recessed in the CMP process is solved, and the flushness of the isolation area and component reliability are improved.
Patent Information
- Application Number
- CN202311717327.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-13
- Publication Date
- 2025-06-17
AI Technical Summary
During the production process of semiconductor components, the oxidized materials in the isolation area are prone to depression in the CMP process, resulting in a decrease in the reliability of the isolation area and adversely affecting the subsequent process.
The first oxide material is deposited on the silicon substrate by the HARP process, filled the first trench, and a second oxide material of different hardness is deposited on the first oxidation material by the HDP process, and the thickness of the second oxidation material is reasonably designed to planarize the isolation area in the CMP process.
The depressed defects of the isolation area in the CMP process are effectively avoided, and the top surface of the isolation area is flush with the top surface of the stacked structure is ensured, which improves the reliability of the components and the stability of subsequent processes.
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Figure CN120164841A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a method for forming a semiconductor device and a semiconductor device. Background Art
[0002] In current semiconductor manufacturing processes, isolation regions are typically formed in a substrate to separate multiple active regions, thereby avoiding mutual interference between different active regions. During the formation of the isolation regions, a shallow trench is usually formed in the substrate, and then an insulating material (such as silicon oxide) is filled in the shallow trench to achieve isolation. In order to make the top surface of the oxidation material in the isolation region at the same horizontal level as the top surface of the substrate, a CMP (Chemical Mechanical Planarization) process is generally required. However, during the CMP process, depressions (such as the Figure 1 region A shown) are likely to occur on the surface of the oxidation material in the isolation region, reducing the reliability of the isolation region and also having an adverse impact on subsequent processes. Summary of the Invention
[0003] A first object of the present disclosure is to provide a method for forming a semiconductor device, which can at least partially solve the technical problems existing in the related art.
[0004] A second object of the present disclosure is to provide a semiconductor device formed by the method provided by the present disclosure.
[0005] To achieve the above objects, the present disclosure provides a method for forming a semiconductor device, including:
[0006] Step S10, providing a silicon substrate and forming a stacked structure on the top surface of the silicon substrate;
[0007] Step S20, sequentially etching the stacked structure and the silicon substrate through an STI etching process to form first trenches serving as isolation regions that are horizontally spaced apart;
[0008] Step S40, depositing a first oxidation material on the silicon substrate through a HARP process until the first oxidation material fills the first trenches; and
[0009] Step S50, depositing a second oxidation material on the first oxidation material through an HDP process, the hardness of the second oxidation material being different from the hardness of the first oxidation material, and the deposition thickness of the second oxidation material being such that after polishing the isolation region and the stacked structure through a CMP process, the top surface of the isolation region and the top surface of the stacked structure are flush.
[0010] Optionally, in step S40, a second trench is formed in the first oxidation material corresponding to the position of the first trench, and the bottom surface of the second trench is flush with the top surface of the stacked structure.
[0011] Optionally, in step S40, the distance L1 between the bottom surface of the second trench and the bottom surface of the first trench when depositing the first oxidation material is 2000 - 3000 angstroms.
[0012] Optionally, the method further includes annealing the first oxidation material in step S40.
[0013] Optionally, the hardness of the second oxidation material is greater than that of the first oxidation material. In step S50, the thickness of the second oxidation material at the top of the second trench is greater than the thickness of the second oxidation material in the area other than the second trench at the top of the first oxidation material.
[0014] Optionally, step S10 includes:
[0015] Step S11, depositing a pad oxide layer on the surface of the silicon substrate; and
[0016] Step S12, after step S110, depositing a silicon nitride layer on the pad oxide layer to form the stacked structure.
[0017] Optionally, the method includes performing an etch-back process in step S20 to partially cut the two side corners of the first trench.
[0018] Optionally, the method includes performing step S30 between step S20 and step S40 to form an oxide layer on the inner wall of the first trench.
[0019] Optionally, in step S30, the inner wall of the first trench is heat-treated by ISSG process to oxidize the surface layer of the inner wall of the first trench into SiO2 to form the oxide layer.
[0020] Optionally, the method further includes step S60 after step S50, performing a chemical mechanical polishing process to polish the second oxidation material and the second oxidation material until reaching the stacked structure to planarize the first oxidation material in the first trench.
[0021] In the second aspect of the present disclosure, a semiconductor device formed according to the method described above is provided.
[0022] Through the above technical solution, the HAPR process is first performed to fill the first trench with the first oxidation material, and then the HDP process is performed to deposit the second oxidation material with a hardness different from that of the first oxidation material on the top surface of the first oxidation material. The height differences of the topography are flattened by using the difference in polishing efficiency. By reasonably designing the thickness of the second oxidation material at each position, it is ensured that when the CMP process is subsequently performed, the polishing efficiency at each position of the first oxidation material is consistent, so that the top surface of the isolation region and the top surface of the stacked structure are flush, and no pit defects exist on the top of the stacked structure after the first trench is filled.
[0023] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. They are used to explain the present disclosure together with the following detailed description, but do not constitute a limitation to the present disclosure. In the accompanying drawings:
[0025] Figure 1 is a partial structural cross-sectional view of a semiconductor element provided in the related art;
[0026] Figures 2 - 5 is a partial structural cross-sectional view of a semiconductor element provided by an exemplary embodiment of the present disclosure;
[0027] Figure 6 is a flowchart of a method for forming a semiconductor element provided by an exemplary embodiment of the present disclosure.
[0028] DESCRIPTION OF THE REFERENCE NUMERALS
[0029] 10 - silicon substrate; 20 - stacked structure; 21 - pad oxide layer; 22 - silicon nitride layer; 31 - first trench; 31a - corner; 31b - oxide layer; 32 - second trench; 41 - first oxidation material; 42 - second oxidation material; 100 - isolation region. DETAILED DESCRIPTION
[0030] The following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining and understanding the present disclosure, and are not used to limit the present disclosure.
[0031] In the present disclosure, unless otherwise stated, the directional terms such as "inner" and "outer" are relative to the contour of the corresponding component itself; the directional terms such as "upper", "lower", "top", "bottom", "horizontal", and "vertical" are defined for convenience of description and in combination with the direction of the accompanying drawings. Specifically, reference may be made to Figure 5The illustrated drawing orientation. Terms such as "first" and "second" used in the present disclosure are for distinguishing one element from another and do not have an order or importance. In addition, in the following description when referring to the drawings, the same reference numerals in different drawings represent the same or similar elements.
[0032] Referring to Figures 2 - 6 , a method for forming a semiconductor device provided by the present disclosure may sequentially include steps S10, step S20, step S40, and step S60. Specifically, in step S10, a silicon substrate 10 may be provided, and a stacked structure 20 may be formed on the top surface of the silicon substrate 10. In step S20, the stacked structure 20 and the silicon substrate 10 are sequentially etched by an STI (Shallow Trench Isolation) etching process to form first trenches 31 spaced horizontally apart and serving as isolation regions 100. The first trenches 31 are formed by the STI etching process to more precisely control the size and position of the isolation regions according to requirements. In step S40, a first oxide material 41 is deposited on the silicon substrate 10 by a HARP (High Aspect Ratio Process) process until the first oxide material 41 at least fills the first trenches 31. In step S50, a second oxide material 42 is deposited on the first oxide material 41 by a HDP (High density plasma) process. The deposition thickness of the second oxide material 42 may be such that after polishing the isolation regions 100 and the stacked structure 20 by a CMP process, the top surfaces of the isolation regions 100 and the stacked structure 20 are flush.
[0033] Those skilled in the art understand that in step S50, the hardness of the second oxide material 42 and the first oxide material 41 is different. The hardness of the second oxide material 42 may be greater than that of the first oxide material 41, so that the polishing rate of the second oxide material 42 is lower than that of the first oxide material 41. The first oxide material 41 will form a second trench 32 mentioned below during the deposition process. Vertically, the height of the second oxide material 42 deposited at the second trench 32 should be higher than the height of the second oxide material 42 deposited in the region outside the second trench 32, thereby ensuring the consistency of the polishing efficiency and further improving the defect of depression generated during the CMP process.
[0034] Through the above technical solution, the HAPR process is first performed to fill the first trench 31 with the first oxidation material 41, and then the HDP process is performed to deposit the second oxidation material 42 with a hardness different from that of the first oxidation material 41 on the top surface of the first oxidation material 41. The height differences of the topography are flattened by utilizing the difference in polishing efficiency. By reasonably designing the thickness of each position of the second oxidation material 42, the overall polishing efficiency of each position of the first oxidation material 41 can be ensured to be consistent during the subsequent CMP process, so that the top surface of the isolation region 100 is flush with the top surface of the stacked structure, and no pit defects exist on the top of the stacked structure after the first trench 31 is filled.
[0035] Referring to Figure 3 and Figure 6 In step S40, a second trench 32 can be formed at the position of the first oxidation material 41 corresponding to the first trench 31, with the bottom surface flush with the top surface of the stacked structure 20, so that the first oxidation material 41 can just fill the second trench 32. At the same time, due to the formation of the second trench 32, when the subsequent step of depositing the second oxidation material 42 is performed, the second oxidation material 42 can first fill the position of the second trench 32 to reduce the height difference of the first oxidation material 41, thereby ensuring the consistency of polishing the first oxidation material 41 during the CMP process and effectively improving the defect of the depression in the isolation region 100. It should be noted that although new grooves may also be generated at the positions corresponding to the first trench and the second trench in the deposited layer when the second oxidation material 42 is deposited, by increasing the thickness of the deposited layer as a whole, the polishing rates at different positions can tend to be consistent during polishing.
[0036] Referring to Figure 3 and Figure 6 In step S40, the distance L1 between the bottom surface of the first oxidation material 41 deposited to the second trench 32 and the bottom surface of the first trench 31 can be 2000 - 3000 angstroms. In the related art, when the first oxidation material 41 is deposited, the deposition thickness of the first oxidation material 41 is 4000 - 5000 angstroms. In the embodiments provided by the present disclosure, the deposition thickness of the first oxidation material 41 can be 2500 angstroms, so that while ensuring that the first oxidation material 41 can just fill the first trench 31 and flatten the top surface of the stacked structure 20 after the CMP process, it can also avoid the excessive thickness of the oxidation material layer jointly formed by the second oxidation material 42 and the first oxidation material 41 after the subsequent HDP process.
[0037] According to some embodiments provided by the present disclosure. The method provided by the present disclosure may further include, in step S40, after depositing the first oxidation material 41, annealing the first oxidation material 41 to increase the density of the oxide layer formed by the first oxidation material 41 to further improve the depression defect.
[0038] Referring toFigure 4 and Figure 6 The hardness of the second oxide material 42 can be greater than that of the first oxide material 41, such that the polishing rate of the second oxide material 42 is slower than that of the first oxide material 41. In step S50, the thickness of the second oxide material 42 at the top of the second trench 32 is greater than the thickness of the second oxide material 42 in the region other than the second trench 32 at the top of the first oxide material 41, thereby reducing the polishing rate difference to improve the polishing consistency.
[0039] Referring to Figure 1 and Figure 6 Step S10 may sequentially include step S11 and step S12. In step S11, a pad oxide layer 21 is grown on the top surface of the silicon substrate 10 by dry oxidation. The pad oxide layer 21 may be made of SiO2 material to effectively reduce the stress between the silicon nitride layer 22 and the silicon substrate 10 mentioned below. In step S12, a silicon nitride layer 22 is deposited on the top surface of the pad oxide layer 21 to form a stacked structure 20. In the embodiments provided by the present disclosure, referring to Figure 5 and Figure 6 The method provided by the present disclosure further includes step S60 after step S50, performing a chemical mechanical polishing process, i.e., a CMP process, to polish the second oxide material 42 and the second oxide material 42 until reaching the stacked structure 20 (i.e., the silicon nitride layer 22), so as to planarize the first oxide material 41 in the first trench 31, thereby eliminating the depression.
[0040] Referring to Figure 3 The method in the present disclosure may further include performing an etch-back process (SiN pull-back process) in step S20 to partially cut the two side corners 31a of the first trench 31, thereby increasing the width of the top of the first trench 31 and avoiding the defect of STI divot (shallow trench isolation depression) during the execution of subsequent processes.
[0041] Referring to Figure 3 and Figure 6 The method provided by the present disclosure may further include performing step S30 between step S20 and step S40 to form an oxide layer 31b on the inner wall of the first trench 31, which can be used as an isolation layer to protect the subsequent active region from chemical contamination during the process of removing the nitride.
[0042] Further, the method may further include, in step S30, heat-treating the inner wall of the first trench 31 by an ISSG (In Situ Steam Generation) process to oxidize the surface layer (Si) of the inner wall of the first trench 31 into SiO2 and form an oxide layer 31b. Since the surface layer of the inner wall of the first trench 31 formed by the STI etching process is relatively rough, performing the ISSG process can oxidize the surface layer of the inner wall of the first trench 31 into SiO2, thereby repairing the surface layer to effectively improve the boundary isolation ability of the first trench 31.
[0043] In a second aspect provided by the present disclosure, there is provided a semiconductor device formed according to the above method. The semiconductor device has all the beneficial effects of the method provided by the present disclosure, which will not be elaborated here.
[0044] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0045] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure will not separately describe various possible combination manners.
[0046] In addition, any combination can be made between different embodiments of the present disclosure as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A method for forming a semiconductor device, characterized in that, Including: Step S10, providing a silicon substrate and forming a stacked structure on the top surface of the silicon substrate; Step S20, sequentially etching the stacked structure and the silicon substrate through a STI etching process to form first trenches serving as isolation regions spaced apart in the horizontal direction; Step S40, depositing a first oxidation material on the silicon substrate through a HARP process until the first oxidation material fills the first trenches; And Step S50, depositing a second oxidation material on the first oxidation material through a HDP process, the hardness of the second oxidation material being different from the hardness of the first oxidation material, the deposition thickness of the second oxidation material being such that after polishing the isolation region and the stacked structure through a CMP process, the top surface of the isolation region and the top surface of the stacked structure are flush.
2. The forming method according to claim 1, characterized in that, In the step S40, a second trench having a bottom surface flush with the top surface of the stacked structure is formed at a position of the first oxidation material corresponding to the first trench.
3. The forming method according to claim 2, characterized in that, In the step S40, the distance L1 between the bottom surface of the second trench and the bottom surface of the first trench when depositing the first oxidation material is 2000 - 3000 angstroms.
4. The forming method according to claim 2 or 3, characterized in that, The method further includes annealing the first oxidation material in the step S40.
5. The forming method according to claim 4, characterized in that, The hardness of the second oxidation material is greater than the hardness of the first oxidation material. In the step S50, the thickness of the second oxidation material at the top of the second trench is greater than the thickness of the second oxidation material in the region other than the second trench at the top of the first oxidation material.
6. The forming method according to claim 2, characterized in that, The step S10 includes: Step S11, depositing a pad oxide layer on the surface of the silicon substrate; and Step S12, depositing a silicon nitride layer on the pad oxide layer to form the stacked structure.
7. The forming method according to claim 6, characterized in that, The method includes performing a re-etch process in the step S20 to partially reduce the two side corners of the first trench.
8. The forming method according to claim 1, characterized in that, The method includes performing step S30 between step S20 and step S40 to form an oxide layer on the inner wall of the first trench.
9. The forming method according to claim 8, characterized in that, The method includes, in the step S30, heat-treating the inner wall of the first trench through an ISSG process to oxidize the surface layer of the inner wall of the first trench into SiO2 and form the oxide layer.
10. The forming method according to claim 1, characterized in that, The method further includes step S60 after step S50, performing a chemical mechanical polishing process to polish the second oxidation material and the second oxidation material until reaching the stacked structure to planarize the first oxidation material in the first trench.
11. A semiconductor device formed by the method according to any one of claims 1-10.