Si / SiC hybrid parallel device driving circuit with variable switching time sequence

Abstract

The invention discloses a Si / SiC hybrid parallel device driving circuit with a variable switching time sequence. The Si / SiC hybrid parallel device driving circuit comprises a time sequence switching signal generating circuit, a time delay switch and time sequence switching circuit and a push-pull output circuit. A driving signal is sent by a main control chip, two different driving signals are respectively generated through calculation of a time delay circuit and a plurality of logic gates, and a conventional driving time sequence of normal switching on and off of a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor), delayed switching-on of a Si IGBT (Insulated Gate Bipolar Transistor) and switching-off in advance can be adapted. And meanwhile, a timing sequence switching signal generation circuit detects and compares the conduction current of the SiC MOSFET so as to generate a timing sequence switching signal. And when the conduction current of the SiC MOSFET is in different regions, switching the switching time sequence of the Si / SiC hybrid parallel device. According to the invention, within the whole operation range of the Si / SiC hybrid parallel device, the lowest switching loss and conduction loss are ensured, and the reliability of the SiC MOSFET is greatly improved.

Description

Technical Field

[0001] The present invention relates to a driving circuit, and particularly to a driving circuit for a Si / SiC hybrid parallel device with variable switching timing. Background Art

[0002] Si IGBT is a device that combines the advantages of BJT and MOSFET, with advantages such as large current capacity, low on-state voltage drop, and relatively fast switching speed. However, as a bipolar device, it has tail current and large switching losses. SiC MOSFET, as a new type of third-generation wide-bandgap semiconductor, has an extremely low on-resistance, higher switching frequency and switching speed, and can greatly improve the power density of power electronic devices, etc. However, it is expensive, and the current-carrying capacity of a single SiC MOSFET is limited. Therefore, a large-capacity discrete Si IGBT and a small-capacity discrete SiC MOSFET are paralleled to form a new Si / SiC hybrid parallel device. This device combines the advantages of Si IGBT and SiC MOSFET and is a device with both large current tolerance and low switching losses.

[0003] The Si / SiC hybrid parallel device has a high degree of control freedom and there are various switching timings. The most commonly used switching timing at present is that the SiC MOSFET switches normally, and the Si IGBT turns on with a delay and turns off earlier compared to the SiC MOSFET. This timing can achieve zero-voltage switching of the Si IGBT and greatly reduce the switching losses of the Si / SiC hybrid parallel device. However, since the generally selected parallel SiC MOSFET has a relatively small rated on-state current, if the SiC MOSFET is still used as the main switching device under large current conditions, it will cause the SiC MOSFET to bear a large current alone, resulting in overcurrent of the SiC MOSFET and seriously affecting the reliability of the device. Therefore, when the on-state current is greater than the safe operating current of the SiC MOSFET, the switching timing of the Si IGBT switching normally and the SiC MOSFET turning on with a delay and turning off earlier compared to the Si IGBT should be adopted. During the conduction process, when the on-state current flowing through the SiC MOSFET has exceeded the maximum on-state current of the SiC MOSFET, if the SiC MOSFET is still turned on, it will cause overcurrent of the SiC MOSFET during the conduction process and seriously affect the reliability of the device. Therefore, the switching timing of only the Si IGBT switching should be adopted. On the one hand, it can ensure the reliability of the SiC MOSFET, and on the other hand, it can reduce the conduction loss.

[0004] Currently, the drive circuits for Si / SiC hybrid parallel devices are divided into two types: The first type uses independent drives, that is, each switching device is equipped with a drive circuit separately. In converters with a large number of switching transistors such as inverters, this type of drive method will seriously occupy the GPIO port resources of the main control chip and increase the control complexity; The second type uses a single drive circuit to control both Si IGBT and SiC MOSFET at the same time. Currently, there are few drive circuits in this area that can simultaneously have the functions of adjustable switching delay and adjustable switching timing. Most can only achieve normal switching of SiC MOSFET, and for the timing of Si IGBT turning on with a delay and turning off earlier compared to SiC MOSFET, this seriously affects the reliability of Si / SiC hybrid parallel devices. Summary of the Invention

[0005] Objective of the Invention: Aiming at the above-mentioned existing technologies, a drive circuit for Si / SiC hybrid parallel devices with variable switching timing is proposed to achieve the functions of adjustable switching delay time and variable switching timing, reduce the switching loss and conduction loss of the device, and improve the reliability of the device.

[0006] Technical Solution: A drive circuit for Si / SiC hybrid parallel devices with variable switching timing includes a Si / SiC hybrid parallel device, a timing switching signal generation circuit, a delay switch and timing switching circuit, and a push-pull output circuit;

[0007] The timing switching signal generation circuit samples the voltage across the precision sampling resistor through a differential amplifier circuit, and then sends this voltage and the preset reference voltage values V ref1 (when the conduction current of SiC MOSFET reaches the safe operating current) and V ref2 (when the conduction current of SiC MOSFET reaches the maximum conduction current) into comparators U3 and U4 for comparison respectively. If the conduction current of SiC MOSFET is less than the safe operating current at this time, both comparators U3 and U4 output 1. If the conduction current of SiC MOSFET is greater than the safe operating current but less than the maximum conduction current at this time, comparator U3 outputs 0 and comparator U4 outputs 1. If the conduction current of SiC MOSFET is greater than the maximum conduction current at this time, both comparators U3 and U4 output 0. The output signals V OUT1 and V OUT2 are used to make the Si / SiC hybrid parallel device switch among three switching timings: normal switching of SiC MOSFET, Si IGBT turning on with a delay and turning off earlier compared to SiC MOSFET, SiC MOSFET turning on with a delay and turning off earlier compared to Si IGBT, normal switching of Si IGBT, and SiC MOSFET turning off while Si IGBT is normally switched.

[0008] The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; PWM The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; PWM The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; OUT1 The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; OUT2 The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; PWM_SiCMOSFET The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; OUT1 The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT; PWM_SiIGBT The driving delay signal generation circuit delays the V signal sent by the main control chip through the delay circuit composed of R6 and C1 to form the signal of the delay switch. This signal, after passing through the OR gate and AND gate respectively with the original V signal, can generate a normal driving signal and a driving signal with delayed turn-on and early turn-off; the driving signal with delayed turn-on and early turn-off and V are ORed, and then ANDed with V. The output value is ANDed with the driving signal of the normal switch, and the output is V, which is used as the driving signal of the SiC MOSFET; at the same time, after inverting V, it is ANDed with the driving signal of the normal switch, and the output value is ORed with the driving signal with delayed turn-on and early turn-off, and the output is V, which is used as the driving signal of the Si IGBT;

[0009] The driving signal push-pull output circuit improves the driving ability by connecting V and V to the corresponding push-pull circuits respectively, and outputs the driving signals of +20V / -5V to drive the SiC MOSFET and +15V / -5V to drive the Si IGBT; PWM_SiCMOSFET The driving signal push-pull output circuit improves the driving ability by connecting V and V to the corresponding push-pull circuits respectively, and outputs the driving signals of +20V / -5V to drive the SiC MOSFET and +15V / -5V to drive the Si IGBT; PWM_SiIGBT The driving signal push-pull output circuit improves the driving ability by connecting V and V to the corresponding push-pull circuits respectively, and outputs the driving signals of +20V / -5V to drive the SiC MOSFET and +15V / -5V to drive the Si IGBT;

[0010] Beneficial effects: Since there are multiple switching timings for the Si / SiC hybrid parallel device, and the effects are different under different switching timings. Generally, the switching loss of the Si IGBT is large. Therefore, by adopting the switching timing of turning on the SiC MOSFET earlier and turning off later compared with the Si IGBT, the condition of zero-voltage switching is created for the Si IGBT during switching, so as to reduce the switching loss of the Si / SiC hybrid parallel device, thereby greatly improving the conversion efficiency of the converter using this device. When the conduction current is greater than the safe operating current of the SiC MOSFET, if the SiC MOSFET still turns on earlier and turns off later at this time, it will bear all the current during switching, which is likely to cause overcurrent in the SiC MOSFET. In severe cases, the SiC MOSFET may be directly damaged. Therefore, the switching timing needs to be switched to the Si IGBT turning on earlier and turning off later compared with the SiC MOSFET. When the conduction current of the SiC MOSFET is greater than the maximum conduction current of the SiC MOSFET, if the SiC MOSFET is still conducting at this time, it is easy to damage the SiC MOSFET. On the other hand, when the conduction current is large, the conduction loss of the Si IGBT is much smaller than that of the SiC MOSFET. Therefore, the turn-on of the SiC MOSFET will not only cause reliability problems but also increase the conduction loss. Therefore, the switching timing needs to be switched to only the Si IGBT switching. Currently, there are few drive circuits that can meet the requirements of the Si / SiC hybrid parallel device for delayed switching and timing switching, and they are not suitable for the actual use of the Si / SiC hybrid parallel device. In the present invention, a drive signal is sent by the main control chip, and then through the calculation of the RC delay circuit and multiple logic gates, two different drive signals are generated respectively, which can adapt to the conventional drive timing of the normal switching of the SiC MOSFET, the delayed turn-on of the Si IGBT, and the early turn-off. At the same time, the conduction current of the SiC MOSFET is detected and compared through the timing switching signal generation circuit to generate a timing switching signal. When the conduction current of the SiC MOSFET is in different regions, the switching timing of the Si / SiC hybrid parallel device is switched. In the entire operating range of the Si / SiC hybrid parallel device, the present invention not only ensures the lowest switching loss and conduction loss but also greatly improves the reliability of the SiC MOSFET. Description of the Drawings

[0011] Figure 1 is the topological structure diagram of the present invention;

[0012] Figure 2 is the circuit diagram of the timing switching signal generation circuit, where (a) corresponds to the SiC MOSFET conduction current detection circuit, (b) corresponds to the SiC MOSFET safe operating current comparison circuit; (c) corresponds to the SiC MOSFET maximum conduction current comparison circuit

[0013] Figure 3 It is a delay switch and a timing switching circuit, where (a) corresponds to an RC delay switch circuit, (b) corresponds to a SiCMOSFET timing selection circuit, and (c) corresponds to a Si IGBT timing selection circuit;

[0014] Figure 4 It is a push-pull output circuit, where (a) corresponds to a SiC MOSFET and (b) corresponds to a Si IGBT;

[0015] Figure 5 It is a waveform diagram of the SiC MOSFET switching timing under different conduction currents of the SiC MOSFET;

[0016] Figure 6 It is a waveform diagram of the Si IGBT switching timing under different conduction currents of the SiC MOSFET;

[0017] Figure 7 It is a simulation diagram of the drive signal of the Si / SiC hybrid parallel device, where (a) corresponds to the case where the conduction current of the SiC MOSFET is less than the safe operating current, (b) corresponds to the case where the conduction current of the SiC MOSFET is greater than the safe operating current but less than the maximum conduction current, and (c) corresponds to the case where the conduction current of the SiC MOSFET is greater than the maximum conduction current. Specific implementation mode

[0018] The present invention will be further explained below with reference to the accompanying drawings.

[0019] As Figure 1 shown, a drive circuit for a Si / SiC hybrid parallel device with variable switching timing includes a Si IGBT Q, a SiC MOSFET M, a timing switching signal generation circuit, a delay switch and a timing switching circuit, and a push-pull output circuit. In the main circuit, a precision sampling resistor R1 is connected in series to the drain of the SiC MOSFET.

[0020] The main control chip generates a PWM drive signal with an adjustable duty cycle. After passing through a delay circuit composed of a resistor R6 and a capacitor C1, a delayed PWM drive signal is formed. Then, this signal and the original PWM drive signal pass through an AND gate and an OR gate respectively to generate a drive signal with delayed turn-on and early turn-off and a normal switching drive signal.

[0021] At the same time, the timing switching signal generation circuit detects the drain current when the SiC MOSFET is conducting, converts it into a voltage signal through a differential amplifier circuit in the timing switching signal generation circuit, and then sends it to the inverting input terminals of comparators U3 and U4 respectively, and compares it with the voltage reference value V corresponding to the safe operating current of the SiC MOSFET. ref1The voltage reference value V corresponding to the maximum on-current of the SiC MOSFET ref2 is compared to generate a signal V for timing switching OUT1 and V OUT2 .

[0022] The drive signals for delayed turn-on and early turn-off are ORed with V OUT1 . After the output is ANDed with V OUT2 , the output value is ANDed with the drive signal of the normal switch, and then the output V PWM_SiCMOSFET is output as the drive signal for the SiC MOSFET; at the same time, after inverting V OUT1 and ANDing it with the drive signal of the normal switch, the output value is ORed with the drive signals for delayed turn-on and early turn-off, and then the output V PWM_SiIGBT is output as the drive signal for the Si IGBT

[0023] The two drive signals are respectively sent to the corresponding push-pull output circuits to increase the drive capability, and finally the outputs v g_MOSFET and v g_IGBT are obtained and then connected to the gates of the SiC MOSFET and the Si IGBT respectively to drive the switching transistors Q and M to work according to the corresponding delay time and switching timing

[0024] As shown in (a) of Figure 2 , the SiC MOSFET on-current detection circuit includes an isolation amplifier U1, an operational amplifier U2, and resistors R2 to R5; the positive input terminal of the isolation amplifier U1 is connected to the upper end of the precision sampling resistor R1 in the main circuit, and the negative input terminal is connected to the lower end of the precision sampling resistor R1; one end of the resistor R2 is connected to the positive output terminal of the isolation amplifier U1, and the other end is connected to the non-inverting input terminal of the operational amplifier U2 and one end of the resistor R4, and the other end of the resistor R4 is grounded; one end of the resistor R3 is connected to the negative output terminal of the isolation amplifier U1, and the other end is connected to the inverting input terminal of the operational amplifier U2 and one end of the resistor R5, and the other end of the resistor R5 is connected to the output terminal of the operational amplifier U2, and the output V Id_MOS is obtained; the isolated front-end power supply terminals of the isolation amplifier U1 are respectively connected to the positive voltage V cc1 and the negative voltage V2, and the isolated back-end power supply terminals are respectively connected to the positive voltage V cc2 and ground; the power supply terminals of the operational amplifier U2 are respectively connected to the positive voltage V cc and the negative voltage V ss ;

[0025] As shown in (b) of Figure 2 , the SiC MOSFET safe operating current comparison circuit includes a comparator U3; the non-inverting input terminal of the comparator U3 is connected to the reference voltage value V ref1 ; the inverting input terminal of the comparator U3 is connected to V Id_MOS ; the output terminal of the comparator U3 outputs VOUT1 ; The power supply terminals of the comparator U3 are respectively connected to the positive voltage V cc and the negative voltage V ss ;

[0026] As shown in (c) of Figure 2 , the SiC MOSFET maximum conduction current comparison circuit includes a comparator U4; the non-inverting input terminal of the comparator U4 is connected to the reference voltage value V ref2 ; the inverting input terminal of the comparator U4 is connected to V Id_MOS ; the output terminal of the comparator U4 outputs V OUT2 ; the power supply terminals of the comparator U4 are respectively connected to the positive voltage V cc and the negative voltage V ss ;

[0027] As shown in (a) of Figure 3 , the RC delay switch circuit includes a resistor R6, a capacitor C1, an AND gate AND1, and an OR gate OR1; one end of the resistor R6 is simultaneously connected to the drive signal V PWM issued by the main control chip, the input terminal 1 of the OR gate OR1, and the input terminal 2 of the AND gate AND1, and the other end is connected to the input terminal 2 of the OR gate OR1, the input terminal 1 of the AND gate AND1, and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the output terminal of the OR gate OR1 outputs V OUTOR1 ; the output terminal of the AND gate AND1 outputs V OUTAND1 ;

[0028] As shown in (b) of Figure 3 , the SiC MOSFET timing switching circuit includes AND gates AND3 to AND4 and an OR gate OR2; the input terminal 1 of the OR gate OR2 is connected to V OUT1 , the input terminal 2 of the OR gate OR2 is connected to V OUTAND1 , and the output terminal is connected to the input terminal 1 of the AND gate AND3; the input terminal 2 of the AND gate AND3 is connected to V OUT2 , and the output terminal is connected to the input terminal 1 of the AND gate AND4; the input terminal 2 of the AND gate AND4 is connected to V OUTOR1 , and the output terminal outputs V PWM_SiCMOSFET , as the SiC MOSFET drive signal;

[0029] As shown in (c) of Figure 3 , the Si IGBT timing switching circuit includes an AND gate AND2, an OR gate OR3, and a NOT gate NOT1; the input terminal of the NOT gate NOT1 is connected to V OUT1 , and the output terminal is connected to the input terminal 2 of the AND gate AND2; the input terminal 1 of the AND gate AND2 is connected to V OUTOR1 , and the output terminal is connected to the input terminal 2 of the OR gate OR3; the input terminal 1 of the OR gate OR3 is connected to V OUTAND1 , and the output terminal outputs V PWM_SiIGBT , as the Si IGBT drive signal.

[0030] As shown in Figure 4 (a) of, the SiC MOSFET push - pull output circuit includes transistors Q1 - Q2 and resistor R g_SiCMOSFET ; The base of transistor Q1 is connected to V PWM_SiCMOSFET and the base of transistor Q2, the collector is connected to + 20V, the emitter is connected to resistor R g_SiCMOSFET and the emitter of transistor Q2, the collector of transistor Q2 is connected to - 5V, the other end of resistor R g_SiCMOSFET outputs v g_MOSFET , which is fed into the gate of the SiC MOSFET, and the source of the SiC MOSFET is grounded.

[0031] As shown in Figure 4 (b) of, the Si IGBT push - pull output circuit includes transistors Q3 - Q4 and resistor R g_SiIGBT ; The base of transistor Q3 is connected to V PWM_SiIGBT and the base of transistor Q4, the collector is connected to + 15V, the emitter is connected to resistor R g_SiIGBT and the emitter of transistor Q4, the collector of transistor Q4 is connected to - 5V, the other end of resistor R g_SiIGBT outputs v g_IGBT , which is fed into the gate of the Si IGBT, and the emitter of the Si IGBT is grounded.

[0032] To analyze the working principle of the circuit, the following definitions are made: V Id_MOS is the output of operational amplifier U2 in the SiC MOSFET conduction current detection circuit; V ref1 ~V ref2 are the reference values of the SiC MOSFET safe operating current comparison circuit and the SiC MOSFET maximum conduction current comparison circuit respectively; I SOA_MOSFET is the SiC MSOFET safe operating voltage; I MAX_MOSFET is the SiC MOSFET maximum conduction current; V OUT1 is the output of comparator U3 in the SiC MOSFET safe operating current comparison circuit; V OUT2 is the output of comparator U4 in the SiC MOSFET maximum conduction current comparison circuit; The output of AND gate AND1 is V OUTAND1 , and the output of OR gate OR1 is V OUTOR1 ; V PWM is the drive signal sent by the main control chip; V delay is the delayed PWM signal of V PWM after passing through the delay circuit.

[0033] As shown in Figure 2 , the timing switching signal generation circuit, which consists of a differential amplifier circuit formed by an operational amplifier and a comparison circuit formed by a comparator. As shown in Figure 2The SiC MOSFET conduction current detection circuit shown in (a) takes the difference between the voltages V1 and V2 across the precision sampling resistor R1 connected in series to the drain of the SiC MOSFET, and outputs the voltage value after the conduction current of the SiC MOSFET flows through the resistor, as shown in the following equation:

[0034]

[0035] Generally, taking R2 = R3 and R4 = R5, the above equation can be simplified as:

[0036]

[0037] As Figure 2 shown in (b) of the SiC MOSFET safe operating current comparison circuit, it compares the output value V Id_MOS of the SiC MOSFET conduction current detection circuit with the voltage value V ref1 reflected on the precision sampling resistor R1 when the Si MOSFET is at the safe operating current. V ref1 is as shown in the following equation:

[0038] V ref1 = I SOA_MOSFET R1 (3)

[0039] The output V OUT1 of the comparator U3 in the SiC MOSFET safe operating current comparison circuit is as shown in the following equation:

[0040]

[0041] As Figure 2 shown in (c) of the SiC MOSFET maximum conduction current comparison circuit, it compares the output value V Id_MOS of the SiC MOSFET conduction current detection circuit with the voltage value V ref2 reflected on the precision sampling resistor when the Si MOSFET is at the maximum conduction current. V ref2 is as shown in the following equation:

[0042] V ref2 = I MAX_MOSFET R1 (5)

[0043] The output V OUT2 of the comparator U4 in the SiC MOSFET maximum conduction current comparison circuit is as shown in the following equation:

[0044]

[0045] As Figure 3The shown delay switch and timing switching circuit first realizes the delay of the PWM signal through the delay circuit, then separates and extracts the normal switch, delayed turn-on, and early turn-off signals through logic gates, and finally realizes the selection of timing switching through multiple logic gates. As Figure 3 As shown in (a) of

[0046]

[0047] where, V PWM (t) is the PWM signal that changes with time t.

[0048] As Figure 5 shown, the SiC MOSFET switch timing waveform diagram under different conduction currents. The OR gate OR1 and the AND gate AND1 continuously output the normal switch signal and the switch signal of turn-on after and turn-off before according to the switch frequency set by the main control chip. When the conduction current of the SiC MOSFET is less than the safe operating current, that is, [0 - t1], V OUT1 and V OUT2 outputs are both 1. Therefore, the output of the OR gate OR2 is 1. After sending this output value to the AND gate AND3, the output of the AND gate AND3 is also 1. After sending this output value to the AND gate AND4, the output of the AND gate AND4 is the normal switch timing waveform. At this time, the SiC MOSFET works according to the normal switch timing; when the conduction current of the SiC MOSFET is greater than the safe operating current and less than the maximum conduction current, that is, [t1 - t2], V OUT1 output becomes 0, and V OUT2 output remains 1. Therefore, the output of the OR gate OR2 is the switch signal of delayed turn-on and early turn-off. After sending this output value to the AND gate AND3, the output of the AND gate AND3 is also the switch signal of delayed turn-on and early turn-off. After sending this output value to the AND gate AND4, the output of the AND gate AND4 is still the switch signal of delayed turn-on and early turn-off. At this time, the SiC MOSFET works according to the timing of delayed turn-on and early turn-off; when the conduction current of the SiC MOSFET is greater than the maximum conduction current, that is, [t2 - t3], V OUT1 output becomes 0, and V OUT2 output also becomes 0. Therefore, the output of the OR gate OR2 is the switch signal of delayed turn-on and early turn-off. After sending this output value to the AND gate AND3, the output of the AND gate AND3 becomes 0. After sending this output value to the AND gate AND4, the output of the AND gate AND4 becomes 0. At this time, the SiC MOSFET does not work.

[0049] As Figure 6The shown SiC MOSFET is in the Si IGBT switching timing waveform diagram under different conduction currents. The OR gate OR1 and the AND gate AND1 continuously output normal switching signals and late turn-on and early turn-off switching signals respectively according to the switching frequency set by the master chip. When the conduction current of the SiC MOSFET is less than the safe operating current, i.e., [0 - t1], V OUT1 The output is 1. Therefore, the output of the NOT gate NOT1 is 0. After sending this output value to the AND gate AND2, the output of the AND gate AND2 is also 0. Sending this output value to the OR gate OR3, the output of the OR gate OR3 is the timing waveform of delayed turn-on and early turn-off. At this time, the Si IGBT works according to the timing of delayed turn-on and early turn-off; when the conduction current of the SiC MOSFET is greater than the safe operating current and less than the maximum conduction current, i.e., [t1 - t2], V OUT1 The output becomes 0. Therefore, the output of the NOT gate NOT1 becomes 1. After sending this output value to the AND gate AND2, the output of the AND gate AND2 is the normal switching waveform. Sending this output value to the OR gate OR3, the output of the OR gate OR3 is the normal switching timing waveform. At this time, the Si IGBT works according to the normal switching timing; when the conduction current of the SiC MOSFET is greater than the maximum conduction current, i.e., [t2 - t3], V OUT1 The output is still 0. Therefore, the output of the NOT gate NOT1 is still 1. After sending this output value to the AND gate AND2, the output of the AND gate AND2 is the normal switching waveform. Sending this output value to the OR gate OR3, the output of the OR gate OR3 is the normal switching timing waveform. At this time, the Si IGBT still works according to the normal switching timing.

[0050] The present invention mainly aims at the problems that there are delayed switching and various switching timings when Si IGBT and SiC MOSFET are in parallel, and the switching timing needs to be switched in different current ranges. To better illustrate the working principle of this circuit, in one switching cycle, it is assumed that the conduction current of the SiC MOSFET is greater than the safe operating current and less than the maximum conduction current.

[0051] State 1: The master chip sends a PWM signal, which is sent into the delay circuit. After delay, the output is V delay . This signal passes through the OR gate OR1 to output a normal switching PWM signal, and passes through the AND gate AND1 to output a PWM signal of delayed turn-on and early turn-off. At the same time, the conduction current of the SiC MOSFET detects the current conduction current of the SiC MOSFET, and sends them into the SiC MSOFET safe operating current comparator and the SiC MOSFET maximum conduction current comparator respectively. The output of the comparator U3 is V OUT1 is 0, and the output of the comparator U4 is V OUT2 is 1.

[0052] State 2: The output signal of the AND gate AND1 and VOUT1 It is sent to the OR gate OR2 in the SiC MOSFET timing switching circuit, and the output of the OR gate OR2 is a PWM signal with delayed turn-on and early turn-off. At the same time, V OUT1 It is sent to the NOT gate NOT1 in the Si IGBT timing switching circuit, and the output of the NOT gate NOT1 is 1.

[0053] State three: The output of the OR gate OR2 and V OUT2 It is sent to the AND gate AND3 in the SiC MOSFET timing switching circuit, and the output of the AND gate AND3 is a PWM signal with delayed turn-on and early turn-off. At the same time, the output of the NOT gate NOT1 and the output signal of the OR gate OR1 are sent to the AND gate AND2 in the Si IGBT timing switching circuit, and the output of the AND gate AND2 is a PWM signal for normal switching.

[0054] State four: The output of the AND gate AND3 and the output of the OR gate OR1 are sent to the AND gate AND4 in the SiC MOSFET timing switching circuit, and the output of the AND gate AND4 is a PWM signal with delayed turn-on and early turn-off, serving as the switching signal V of the SiC MOSFET in the current period PWM_SiCMOSFET At the same time, the output of the AND gate AND2 and the output of the AND gate AND1 are sent to the OR gate OR3 in the Si IGBT timing switching circuit, and the output of the OR gate OR3 is a PWM signal for normal switching, serving as the switching signal V of the Si IGBT in the current period PWM_SiIGBT 。

[0055] State five: The SiC MOSFET switching signal V PWM_SiCMOSFET and the Si IGBT switching signal V PWM_SiIGBT are respectively sent to the corresponding push-pull output circuits to increase the driving ability. Finally, the output driving voltage is +20V / -5V, and the driving timing is a driving signal v with later turn-on and earlier turn-off g_MOSFET , which is connected to the gate of the SiC MOSFET to drive the SiC MOSFET to switch. At the same time, the output driving voltage is +15V / -5V, and the driving timing is a driving signal v for normal switching g_IGBT , which is connected to the gate of the Si IGBT to drive the Si IGBT to switch.

[0056] Figure 7 (a), (b), and (c) respectively show the schematic diagrams of the driving signals of the SiC MOSFET and the Si IGBT when the conduction current of the SiC MOSFET is below the safe operating current, greater than the safe operating current but less than the maximum conduction current, and greater than the maximum conduction current. From Figure 7From (a) to (b), it can be found that for the timing switching signal generation circuit proposed by the present invention, after the conduction current of the SiC MOSFET reaches the safe operating current, the switching timing of the SiC MOSFET can be accurately switched to turn on later and turn off first, while the switching timing of the Si IGBT is switched to the normal switching, so that the SiC MOSFET is prevented from bearing the large current during the switching process, ensuring the reliability of the SiC MOSFET. Therefore, this circuit has obvious effects. From Figure 7 From (b) to (c), it can be found that for the timing switching signal generation circuit proposed by the present invention, after the conduction current of the SiC MOSFET reaches the maximum conduction current, the SiC MOSFET can be accurately turned off, while the switching timing of the Si IGBT remains at the normal switching, so that the SiC MOSFET is prevented from having a conduction current exceeding the maximum current it can withstand, ensuring the reliability of the SiC MOSFET. This circuit has obvious effects.

[0057] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A Si / SiC hybrid parallel device driving circuit with variable switching timing, wherein the main circuit comprises parallel Si IGBT and SiC MOSFET devices, characterized in that: The driving circuit includes a timing switching signal generating circuit, a delay switch and timing switching circuit, and a push-pull output circuit; In the timing switching signal generating circuit, the voltage across the sampling resistor connected in series to the drain of the SiC MOSFET is sampled by a differential amplifier circuit, and the voltage is compared with the voltage reference value corresponding to the safe working current of the SiC MOSFET. V ref1 Voltage reference value corresponding to the maximum on-current of SiC MOSFET V ref2 Compare and generate timing switching signals respectively V OUT1 and V OUT2 ; In the delay switch and timing switching circuit, the PWM signal generated by the main control chip is generated through a delay circuit to generate a delayed PWM signal, and then a normal switch driving signal is generated through a logic gate. V OUTOR1 And a driving signal for delayed opening and early closing V OUTAND1 ; Drive signal V OUTAND1 and signal V OUT1 After phase OR, the output and signal V OUT2 Perform phase AND, output value and drive signal V OUTOR1 After performing phase AND, the drive signal of SiC MOSFET is output V PWM_SiC MOSFET ; Simultaneous signal V OUT1 After inversion, and the drive signal V OUTOR1 Perform phase AND, and then output value and drive signal V OUTAND1 After phase OR, the drive signal of Si IGBT is output V PWM_Si IGBT ; Drive signal V PWM_SiC MOSFET and drive signal V PWM_Si IGBT After passing through the push-pull output circuit, the power is input into the SiCMOSFET gate and the Si IGBT gate.

2. The Si / SiC hybrid parallel device driving circuit with variable switching timing according to claim 1, characterized in that: In the timing switching signal generating circuit, if the SiC MOSFET conduction current is less than the safe operating current, the signal V OUT1 and V OUT2 If the SiC MOSFET on-current is greater than the safe operating current but less than the maximum on-current, the signal V OUT1 is 0, signal V OUT2 is 1; if the SiC MOSFET on-current is greater than the maximum on-current, the signal V OUT1 and V OUT2 are all 0; correspondingly, the signal V OUT1 and V OUT2 It is used to switch the Si / SiC hybrid parallel device between three switching timings: normal switching of SiC MOSFET, delayed turn-on and early shut-down of Si IGBT compared with SiC MOSFET; delayed turn-on and early shut-down of SiC MOSFET compared with Si IGBT, and normal switching of SiIGBT; and SiC MOSFET shut-off and normal switching of Si IGBT.

3. The Si / SiC hybrid parallel device driving circuit with variable switching timing according to claim 1, characterized in that: The timing switching signal generating circuit includes an isolation amplifier U1, an operational amplifier U2, comparators U3-U4 and resistors R 2~ R 5. The positive input terminal of the isolation amplifier U1 is connected to the sampling resistor in the main circuit. R 1 upper end, negative input end connected to sampling resistor R 1 lower end; resistance R 2 One end is connected to the positive output of the isolation amplifier U1, and the other end is connected to the non-inverting input of the operational amplifier U2 and the resistor R 4 one end, resistor R 4The other end is grounded; the resistor R 3 One end is connected to the negative output terminal of the isolation amplifier U1, and the other end is connected to the inverting input terminal of the operational amplifier U2 and the resistor R 5 one end, resistor R 5The other end is connected to the output of operational amplifier U2 and the inverting input of comparators U3 and U4; the positive input of comparators U3 and U4 are connected to the reference voltage value V ref1 and V ref2 , the output signal of the comparator U2 is V OUT1 , the output signal of the comparator U3 output V OUT2 .

4. The Si / SiC hybrid parallel device driving circuit with variable switching timing according to claim 1, characterized in that: The delay switch and timing switching circuit include a resistor R 6. Capacitor C 1. AND gates AND1~AND4, OR gates OR1~OR3 and NOT gate NOT1; resistors R 6. One end is connected to the drive signal at the same time V PWM , OR gate OR1 input terminal 1 and AND gate AND1 input terminal 2, and the other end is connected to OR gate OR1 input terminal 2, AND gate AND1 input terminal 1 and capacitor C 1 one end, capacitor C 1The other end is grounded; the output of OR gate OR1 is connected to the input 1 of AND gate AND2 and the input 2 of AND gate AND4; the output of AND gate AND1 is connected to the input 2 of OR gate OR2 and the input 1 of OR gate OR3; the input 1 of OR gate OR2 is connected to V OUT1 , the output end is connected to the input end 1 of AND gate AND3; the input end 2 of AND gate AND3 is connected to V OUT2 , the output end is connected to the input end 1 of AND gate AND4; the output end of AND gate AND4 outputs the driving signal V PWM_SiC MOSFET ; NOT gate NOT1 input connection V OUT1 , the output end is connected to the input end 2 of AND gate AND2; the output end of AND gate AND2 is connected to the input end 2 of OR gate OR3; the output end of OR gate OR3 outputs the driving signal V PWM_Si IGBT .

5. The Si / SiC hybrid parallel device driving circuit with variable switching timing according to claim 1, characterized in that: The push-pull output circuit includes transistors Q1-Q4, resistors R g_SiC MOSFET and resistor R g_Si IGBT ; Transistor Q1 base connection V PWM_SiC MOSFET The base of transistor Q2, the collector is connected to +20V, and the emitter is connected to the resistor R g_SiC MOSFET Connect the emitter of transistor Q2 and the collector of transistor Q2 to -5V, and the resistor R g_SiC MOSFET The other end output v g_MOSFET , fed into the SiC MOSFET gate, the SiC MOSFET source is grounded; the base of transistor Q3 is connected V PWM_Si IGBT The base of transistor Q4, the collector is connected to +15V, and the emitter is connected to the resistor R g_Si IGBT Connect the emitter of transistor Q4 and the collector of transistor Q4 to -5V, and the resistor R g_Si IGBT The other end output v g_IGBT , sent to the Si IGBT gate, and the Si IGBT emitter is grounded.

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