Transformer coupled input buffer for frequency synthesis

Abstract

The invention relates to a transformer coupled input buffer for frequency synthesis. A frequency synthesis circuit includes a first inductor (356) coupled to receive a first input signal at an input frequency, and a second inductor (366) coupled to receive a second input signal at the input frequency and out of phase with respect to the first input signal. The circuit has a first transistor (350) and a second transistor (360) whose control terminals are coupled to the first inductor and the second inductor, respectively. A first resonant tank circuit (351) of an inductor (352) in parallel with a capacitor (354) is coupled between a power supply terminal and the first transistor. A second resonant tank (361) of an inductor (362) in parallel with a capacitor (364) is coupled between the power supply terminal and the second transistor. The first resonant tank and the second resonant tank are tuned to selected harmonics of the input frequency. An injection locked oscillator (210) has an input coupled to the first transistor and the second transistor.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 610,522, filed Dec. 15, 2023, which is incorporated herein by reference. Field of the Invention

[0003] This application relates to a transformer-coupled input buffer for frequency synthesis. Background of the Invention

[0004] This specification relates to frequency synthesis circuits and, more particularly, to frequency synthesis circuits based on injection-locked oscillators.

[0005] Frequency synthesis circuits (also referred to as clock generator circuits) are commonly used in many electronic systems to generate stable periodic signals, such as clock signals. The clock signals generated by the frequency synthesis circuits are used to time data converter circuits (e.g., analog-to-digital converters and digital-to-analog converters), and are used as reference clocks in test and measurement systems, as system clocks in digital processing circuits, and so on. Some wireless and wired communication transceivers include a frequency synthesis circuit in the form of a local oscillator that generates clock signals used in the down-conversion of received signals and the up-conversion of signals to be transmitted. Summary of the Invention

[0006] According to one example, a frequency synthesis circuit includes: a first transistor having a first conduction terminal, a second conduction terminal coupled to a common potential, and a control terminal; and a second transistor having a first conduction terminal, a second conduction terminal coupled to a common potential, and a control terminal. A first tank inductor and a first tank capacitor each have a first terminal coupled to a power supply terminal and a second terminal coupled to the first conduction terminal of the first transistor. A second tank inductor and a second tank capacitor each have a first terminal coupled to the power supply terminal and a second terminal coupled to the first conduction terminal of the second transistor. A first inductor is coupled between a first input and the control terminal of the first transistor, and a second inductor is coupled between a second input and the control terminal of the second transistor. An injection-locked oscillator has a first injection input coupled to the first conduction terminal of the second transistor and a second injection input coupled to the first conduction terminal of the first transistor.

[0007] According to another example, a frequency synthesis circuit includes a first inductor coupled to receive a first input signal at an input frequency, and a second inductor coupled to receive a second input signal at the input frequency and out of phase with respect to the first input signal. The circuit has a first transistor and a second transistor, whose control terminals are coupled to the first inductor and the second inductor respectively. A first resonant tank of an inductor in parallel with a capacitor is coupled between a power supply terminal and the first transistor. A second resonant tank of an inductor in parallel with a capacitor is coupled between the power supply terminal and the second transistor. The first resonant tank and the second resonant tank are tuned to a selected harmonic of the input frequency. An injection-locked oscillator has an input coupled to the first transistor and the second transistor.

[0008] According to another example, an input buffer circuit includes a first transistor and a second transistor, each having a first conduction terminal, a second conduction terminal coupled to a common potential, and a control terminal. A first tank inductor and a first tank capacitor each have a first terminal coupled to a power supply terminal and a second terminal coupled to the first conduction terminal of the first transistor, and a second tank inductor and a second tank capacitor each have a first terminal coupled to the power supply terminal and a second terminal coupled to the first conduction terminal of the second transistor. A first inductor is coupled between a first input and the control terminal of the first transistor, and a second inductor is coupled between a second input and the control terminal of the second transistor.

[0009] Example technical advantages implemented by one or more of these examples include using regenerative feedback in a transformer-coupled input buffer to enhance the injection current with strong harmonic components to an injection-locked oscillator. This enhancement of the injection current from regenerative feedback avoids increasing the bias current to the injection-locked oscillator, which may burden the resonant tank in the oscillator. Reduced out-of-band phase noise can be exhibited by a frequency multiplier that includes an input buffer and an injection-locked oscillator to provide frequency multiplication with a high jitter tracking bandwidth. Good sub-harmonic rejection ratio (SHRR) performance is also achieved.

[0010] Those of ordinary skill in the art will appreciate other example technical advantages achieved by the disclosed examples after referring to the following description and its drawings. Description of the Drawings

[0011] Figure 1 is an electrical diagram of an example frequency synthesis circuit in block diagram form.

[0012] Figure 2 is in block diagram form Figure 1 of an example frequency multiplier in a frequency synthesis circuit.

[0013] Figure 3A is in schematic formFigure 2 Electrical diagram of an injection-locked oscillator in a multiplier of

[0014] Figure 3B in schematic form Figure 2 Electrical diagram of an example input buffer in a multiplier of

[0015] Figure 4 in schematic form showing Figure 3B the operation of an example input buffer of

[0016] Figure 5 in schematic form Figure 2 Electrical diagram of an example multiplier of

[0017] Figure 6 is a flowchart showing an example frequency synthesis method.

[0018] The same reference numerals or other reference indicators are used in the figures to denote the same or similar features (functionally and / or structurally). Detailed Description

[0019] The frequency synthesis circuit can be embedded within a larger scale integrated circuit such as an "analog front end" circuit for, e.g., a radio frequency (RF) transceiver, or can be implemented as a stand-alone synthesizer integrated circuit. Examples of stand-alone synthesizer integrated circuits include the LMX1204 and LMX2820 synthesizer integrated circuits available from Texas Instruments Incorporated. According to one architecture, the frequency synthesis circuit can include an on-chip multiplier for multiplying the frequency of a lower frequency clock signal by an integer multiple (e.g., 2 or 3 times) to an intermediate frequency for up-conversion and down-conversion. This architecture is particularly useful in high frequency applications such as modern communication transceivers and high rate data converters operating in, e.g., the GHz range, because the higher frequency output clock can be based on a low jitter clock signal that is easier to generate at a lower frequency.

[0020] Examples of multipliers include a phase locked loop (PLL), an open-loop frequency multiplier based on an unbalanced source-coupled or emitter-coupled transistor pair, and an injection-locked oscillator (ILO). More specifically, the ILO includes an oscillator, such as a cross-coupled transistor having a resonant tank load, which is tuned to a selected harmonic of an input reference frequency applied at an injection transistor, e.g., the third harmonic. The injection transistor is biased to facilitate non-linear conduction. The combination of this non-linear conduction and the tuned resonant tank injects current at the harmonic frequency into the oscillator. The oscillator locks at the harmonic frequency, thereby generating an output periodic signal at a multiple of the reference frequency.

[0021] Figure 1FIG. 100 shows an example frequency synthesis circuit 100. The frequency synthesis circuit 100 may alternatively be referred to as a clock generator or a timing signal generator, among other terms. The frequency synthesis circuit 100 includes a clock generator / buffer 110 and a multiplier 120.

[0022] The clock generator / buffer 110 may be configured as a clock generator circuit that generates a periodic output signal at a selected frequency, e.g., based on the frequency of an external crystal oscillator coupled to terminal CLK ext or the like. Alternatively, the clock generator / buffer 110 may be configured as a buffer that receives an exogenous periodic signal at terminal CLK ext In either case, the clock generator / buffer 110 generates a periodic signal (e.g., a sinusoidal signal waveform) at a selected reference frequency f0 at conductors VIP, VIN. In this example, the periodic signals at conductors VIP, VIN are 180° out of phase with each other; alternatively, the clock generator / buffer 110 may output a single-ended periodic signal. In one example, the clock generator / buffer 110 generates its output periodic signal with a very low deviation from the reference frequency f0, which deviation is referred to as “jitter”. For example, the reference frequency f0 generated by the clock generator / buffer 110 may be about 2 GHz, with a root mean square jitter of about 50 fsec.

[0023] The multiplier 120 has inputs that receive the inverted reference frequency signals at conductors VIP, VIN, and has one or more outputs RFOUT. The multiplier 120 is configured to present at the output RFOUT one or more periodic signals having a frequency that is m times the input reference frequency f0. In this example, m is an integer multiple, e.g., m = 3. Similar to the input signals at conductors VIP, VIN, the multiplier 120 may provide at its output RFOUT a pair of signals that are 180° out of phase with each other.

[0024] Various circuits have been used as multipliers. One type of multiplier is a phase-locked loop (PLL), where a frequency divider in the feedback loop determines the multiplier m. However, it has proven difficult for a PLL to achieve suitable phase noise or jitter performance at the gigahertz (e.g., mm-wavelength) frequencies required in modern communication and other systems. It has been observed that the PLL components of a phase-frequency detector, charge pump, and loop filter elements add significant in-band noise, especially at higher frequencies. The power consumption in a PLL may also be unacceptably large.

[0025] Another type of frequency multiplier is, for example, an open-loop multiplier based on an unbalanced source-coupled or emitter-coupled pair of transistors. However, it has been observed that open-loop multiplier implementations exhibit noise degradation due to the multiple filters incorporated in this approach and also suffer from undesirably high power consumption. This approach may also exhibit difficulty in compromising between output noise and the sub-harmonic rejection ratio (SHRR).

[0026] The examples described herein arise in this context.

[0027] Figure 2 The architecture of a frequency multiplier 120 according to an example is shown. The frequency multiplier 120 includes a transformer-coupled input buffer 200, an injection-locked oscillator 210, and an output buffer 220.

[0028] The input buffer 200 has an input coupled to conductors VIP, VIN to receive an input periodic signal at a reference frequency f0 from a clock generator / buffer 110 ( Figure 1 ). In this example, the input buffer 200 also has one or more inputs receiving a DC bias voltage VB at a level suitable for a particular circuit configuration. The input buffer 200 has an output coupled to conductors VOUTP, VOUTN, which in this example provides a periodic signal at a frequency that is m times the reference frequency f0. In Figure 2 the example, the frequency multiple m is 3. Similar to the input periodic signal at conductors VIP, VIN, the signals at conductors VOUTP, VOUTN can be 180° out of phase with respect to each other.

[0029] The conductors VOUTP, VOUTN are coupled to the input of the injection-locked oscillator 210. In this example, as discussed below, the periodic signals at conductors VOUTP, VOUTN supply an injection current into the injection-locked oscillator 210 at the frequency 3f0 to which the injection-locked oscillator 210 is locked. The injection-locked oscillator 210 also has one or more inputs receiving a DC bias voltage VBIAS as required for a particular circuit configuration. The injection-locked oscillator 210 has an output coupled to conductors VOP, VON, which in this example provides periodic signals that are 180° out of phase with respect to each other and have a reference frequency multiple of 3f0.

[0030] The output buffer 220 has an input coupled to conductors VOP, VON and has an output RFOUT. The output buffer 220 generates an output RF signal at a reference frequency multiple of 3f0 and with a drive strength suitable for the downstream circuitry of the system. Depending on the system application, such downstream circuitry may include, for example, mixers in an RF transceiver, clock inputs for data converters, etc.

[0031] Figure 3AShows the configuration of an injection-locked oscillator 210 according to an example. In this example where the frequency multiplication factor m = 3, the injection-locked oscillator 210 can be referred to as an injection-locked tripler (ILT) 210. Figure 3A The ILT 210 includes injection transistors 304, 314, input capacitors 301, 311, and input resistors 303, 313. The ILT 210 further includes resonant tank circuits 302, 312, transistors 321, 331, capacitors 323, 333, resistor network 340, and resistor-capacitor (RC) networks 342, 344. The resonant tank circuit 302 includes an inductor 305, a variable capacitor 306, and a resistor 307 connected in parallel between the power supply terminal V DD and the terminal of transistor 321. The resonant tank circuit 312 includes an inductor 315, a variable capacitor 316, and a resistor 317 connected in parallel between the power supply terminal V DD and the terminal of transistor 331. The resonant tank circuits 302, 312 can also be referred to as resonant loops.

[0032] In the ILT 210 according to this example, transistors 321 and 331 are cross-coupled bipolar junction transistors (BJTs, or bipolar transistors). Although transistors 321, 331 (and transistors 304, 314) are shown as n-p-n BJTs in Figure 3A , p-n-p devices can be used alternatively. The base of transistor 321 is coupled to the collector of transistor 331 via capacitor 323, and similarly, the base of transistor 331 is coupled to the collector of transistor 321 via capacitor 333. The emitters of the transistors are coupled to a terminal at a common potential at the ground of the circuit via emitter resistors 325, 335 respectively, and are commonly coupled via the RC network 342. The bases of transistors 321, 331 are biased to a bias voltage VBIAS via corresponding resistors in the resistor network 340. Alternatively, network 340 may include an inductor instead of a resistor for biasing the bases of transistors 321, 331.

[0033] Although the transistors 304, 314, 321, 331 of the ILT 210 are implemented as bipolar junction transistors in this example, the ILT 210 can be implemented alternatively using field effect transistors (FETs) such as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors).

[0034] The collector of transistor 321 is coupled to the power supply terminal V via the resonant tank circuit 302 DD , and the collector of transistor 331 is coupled to the power supply terminal V via the resonant tank circuit 312 DD。The variable capacitors 306, 316 in the resonant tank circuits 302, 312 allow tuning of the resonant frequencies of their respective resonant tank circuits 302, 312. In this instance where the ILT 210 is a frequency tripler, the resonant tank circuits 302, 312 are tuned to the third harmonic of the input reference frequency f0. The nodes VOP, VON at the collectors of the transistors 321, 331 form the output nodes of the ILT 210. The variable capacitors 306, 316 can be configured as switched capacitor networks or in other programmable or adjustable forms.

[0035] The injection transistors 304, 414 are bipolar transistors each having an emitter coupled to a ground circuit terminal via an RC network 344. The collector of the injection transistor 304 is coupled to the collector of the corresponding transistor 321, and the collector of the injection transistor 304 is coupled to the collector of its corresponding transistor 331. A capacitor 301 is coupled between the base of the injection transistor 304 and the conductor VOUTP. A resistor 303 is coupled between the base of the injection transistor 304 and the conductor VB_INJ that receives a DC bias voltage. Similarly, a capacitor 311 is coupled between the base of the injection transistor 314 and the conductor VOUTN. A resistor 313 is coupled between the base of the injection transistor 314 and the conductor VB_INJ that receives a DC bias voltage.

[0036] In operation, periodic signals of opposite phases are applied from the conductors VOUTP, VOUTN to the bases of the injection transistors 304, 314. The DC bias voltage at the conductor VB_INJ biases the injection transistors 304, 314 at a desired operating point, such as class-C bias, which can increase the non-linearity of their collector currents. The oscillator transistors 321, 331 can also be class-C biased from a DC voltage VBIAS, which also favors non-linear conduction. The combination of the non-linear conduction of the transistors 321, 331 and the injection transistors 304, 314 with the tuning of the resonant tank circuits 302, 312 at the third harmonic frequency 3f0 causes the ILT 210 to oscillate at the third harmonic frequency 3f0. Then, output periodic signals of opposite phases at the frequency 3f0 appear at the collector nodes VOP, VON.

[0037] Injection-locked oscillators may suffer from a relatively narrow locking frequency range. When applied in a frequency synthesis circuit, this narrow locking range is reflected in a low jitter tracking bandwidth, which corresponds to a lower corner frequency in the phase noise characteristics of the circuit. The locking range of the ILT can be increased by increasing the bias current of the injection transistor. However, implementations that increase this injection bias current have shown an eventual reduction in the impedance presented to the resonant tank circuit by the higher injection transistor conduction. This reduced impedance burdens the resonant tank circuit, degrading the LC quality factor (Q), and thus degrading the phase noise characteristics of the ILT.

[0038] Figure 3B Shows the configuration of a transformer-coupled input buffer 200 according to an example. The input buffer 200 includes bipolar transistors 350, 360, resonant tanks 351, 361, inductors 356, 366, capacitors 357, 367, and resistors 358, 368, and 370. The resonant tank 351 includes an inductor 352, a variable capacitor 354, and a resistor 355. The resonant tank 361 includes an inductor 362, a variable capacitor 364, and a resistor 365.

[0039] In this example of the transformer-coupled input buffer 200, the transistors 350 and 360 are n-p-n BJTs. The resistor 358 is connected between the base of the transistor 350 and the conductor VB. The capacitor 357 and the inductor 356 connected in series are coupled between the base of the transistor 350 and the conductor VIP. Similarly, the resistor 368 is coupled between the base of the transistor 360 and the conductor VB. The capacitor 367 and the inductor 366 connected in series are coupled between the base of the transistor 360 and the conductor VIN. The emitters of the transistors 350 and 360 are coupled to a terminal at a common potential (e.g., the ground of the circuit) via a tail resistor 370.

[0040] The collector of the transistor 350 is coupled to the resonant tank 351. Each of the inductor 352, the variable capacitor 354, and the resistor 355 in the resonant tank 351 is coupled between the collector of the transistor 350 and the power supply terminal V DD therebetween. Similarly, the collector of the transistor 360 is coupled to the resonant tank 361. Each of the inductor 362, the variable capacitor 364, and the resistor 365 in the resonant tank 361 is coupled between the collector of the transistor 360 and the power supply terminal V DD therebetween. The variable capacitors 354, 364 allow the resonant frequencies of their respective resonant tanks 351, 361 to be tuned to, for example, odd harmonics of the same input reference frequency f0 as that of an injection-locked oscillator coupled to the collector nodes VOUTP, VOUTN. In this example where the ILT 210 is configured as a frequency tripler, the resonant tanks 351, 361 are also tuned to the third harmonic of the input reference frequency f0. The variable capacitors 354, 364 can be configured as switched-capacitor networks or in other programmable or adjustable forms.

[0041] In Figure 3BIn an example, an inductor 356 that couples a conductor VIP to the base of a transistor 350 is inductively coupled to an inductor 362 in a resonant tank circuit 361 at the collector of the transistor 360. Similarly, an inductor 366 that couples a conductor VIN to the base of the transistor 360 is inductively coupled to an inductor 352 in a resonant tank circuit 351 at the collector of the transistor 350. The mutual inductance k of the inductors 356 and 362 and the inductors 366 and 352 can vary according to the implementation. In one example, the mutual inductance k is about 0.6. Alternatively, the inductors 356 and 362 and the inductors 366 and 352 may not be inductively coupled, in which case the mutual inductance k≈0.

[0042] Nodes VOUTP and VOUTN at the collectors of transistors 360 and 350 respectively form the output nodes of the transformer-coupled input buffer 200. As described above with respect to Figure 3A These nodes VOUTP and VOUTN are coupled to the inputs of the ILT 210, for example to the bases of transistors 304 and 314, via respective capacitors 301 and 311.

[0043] Although the transistors 350 and 360 of the input buffer 200 are implemented as BJTs in this example, the transistors 350 and 360 can alternatively be implemented as FETs, such as MOS transistors.

[0044] In operation, periodic signals at an input reference frequency f0 are applied at the conductors VIP and VIN. The signals at the conductors VIP and VIN are 180° out of phase with each other. The conductor VB applies a DC bias voltage to the bases of the transistors 350 and 360 via resistors 358 and 368 respectively. In this example, this bias voltage at the conductor VB is slightly lower than the threshold voltages of the transistors 350 and 360 to enhance the non-linear operation of these devices, particularly at the desired harmonics (such as the third harmonic) of the reference frequency f0. In one example, the bias voltage at the conductor VB is selected to bias the transistors 350 and 360 in class AB.

[0045] Figure 4 An example of the operation of the transformer-coupled input buffer 200 with reference to the transistor 350 and the resonant tank circuit 351 is shown. The transistor 360 and the resonant tank circuit 361 operate in a similar manner. The base of the transistor 350 is biased in class AB by a DC voltage at the conductor VB. Initially, the DC voltage at the conductor VB and the reference frequency f0 signal at the conductor VIP are applied to the base of the transistor 350. The voltage V at the harmonic frequency 3f0 across the inductor GN is initially zero but increases over time as described below.

[0046] In this example, the collector current I of the transistor 350 D1Can be expressed as:

[0047] I D1 (f) = I0 + g m1 V bp (f0) + g m2 V bp (2f0) + g m3 V bp (3f0) + … (1)

[0049] Where I0 is the DC collector current, and V bp is the base voltage of transistor 350, and where g m factor is the transconductance of transistor 350 at the indicated harmonic frequency. The corresponding current Q·I D1 flows through inductor 352, where Q is the quality factor of the resonant tank 351. This current Q·I D1 contains a component at the resonant frequency of the resonant tank 351, which is 3f0 in this example.

[0050] The harmonic current Q·I D1 (3f0) across inductor 366 generates a corresponding voltage V GP due to the regenerative feedback of the inductive coupling k between inductor 352 and inductor 366. This voltage V GP 's third harmonic component corresponds to:

[0051] V GP (3f0) = [Q·I D1 (3f0)]·k·j6πf0 (2)

[0053] The voltage V GP across inductor 366 also contains a component at the harmonic frequency 3f0, and adds constructively to the reference frequency f0 signal applied from conductor VIN. The voltage V bn at the base of transistor 360 can be expressed as:

[0054] V bn = V IN (f0) + V GP (3f0) (3)

[0056] Where V IN (f0) represents the voltage at conductor VIN.

[0057] The third harmonic component induced in the base voltage V bn generated by inductors 352 and 366 is effectively multiplied by the first-order transconductance (g m1 ) of transistor 360, thereby strengthening its collector current ID2 The third harmonic 3f0 of. The collector current I D2 The third harmonic 3f0 component of contributes to the 3f0 current conducted by the inductor 362 in the resonant tank circuit 361. This current is regeneratively fed back into the base of the transistor 350 through the inductive coupling from the inductor 362 to the inductor 356, thereby establishing the voltage V GN (3f0), which voltage is added in series with the voltage V IP (at the reference frequency f0), and appears as the third harmonic 3f0 component of the base voltage V bp of the transistor 350. The 3f0 component of the base voltage V bp is similarly multiplied by the first-order transconductance g m1 of the transistor 350 to strengthen its collector current I D1 's 3f0 component.

[0058] The magnitude of the third harmonic transconductance of the transistor 350, the magnitude G M3 can be derived as:

[0059]

[0060] where L 352 and L 366 are the inductances of the inductors 352 and 366 respectively. Assuming inductance matching on its side of the input buffer 200, the same value of the third harmonic transconductance magnitude G M3 applies to the transistor 360. For the stability of the input buffer 200, the quantity should be kept below unity.

[0061] Due to the strong third harmonic conduction in the transformer-coupled input buffer 200, the voltages at the conductors VOUTP, VOUTN also have strong third harmonic 3f0 components. These voltages are provided to the input of the ILT 210 at the bases of the injection transistors 304, 314, as described above with respect to Figure 3A and 3B . The third harmonics at the conductors VOUTP, VOUTN enhance the similar harmonic conduction in the ILT 210. According to this example, this enhancement of harmonic conduction is achieved without a corresponding increase in the bias currents of the injection transistors 304, 314 of the ILT 210, and thus without a significant reduction in the impedance presented to the resonant tank circuits 302, 312 by those injection transistors. Therefore, according to this example, the input buffer 200 facilitates the generation of a strong output signal at three times the frequency 3f0 from the ILT.

[0062] As mentioned above, transistors 350 and 360 are biased in class AB mode by the DC voltage at conductor VB. This biasing mode provides short conduction angles within the period of the reference frequency f0, thereby adding at most minimal noise at the output of input buffer 200 and thus at the output of ILT210.

[0063] The value of the transformer coupling coefficient k determines the amount of harmonic conduction in input buffer 200. Simulations have shown that even without coupling (e.g., k = 0), strong third harmonic components 3f0 are generated. However, it has been observed that the inductive coupling of inductors 352 and 366 and inductors 362 and 356 further increases the collector currents I D1 and I D2 in the third harmonics. In one example, it has been observed that an inductive coupling k = 0.58 multiplies the collector currents I D1 and I D2 by a factor of 2.1 in simulations relative to the case without inductive coupling (k = 0).

[0064] Figure 5 An example interconnection of the transformer-coupled input buffer 200 with ILT 210 and output buffer 220 within multiplier 120 is shown. For clarity, Figure 5 input buffer 200 and ILT 210 are shown in a slightly simplified form relative to the form described above using Figure 3A and 3B .

[0065] Output buffer 220 in multiplier 120 includes buffers 502 and 504. Buffer 502 has an input coupled to conductor VOP from the output of ILT 210, and buffer 504 has an input coupled to conductor VON from the output of ILT 210. The outputs of buffers 502 and 504 constitute the output RFOUT from multiplier 120, also as Figure 2 shown. In this example, the outputs of buffers 502 and 504 are 180° out of phase with each other, corresponding to opposite phase signals at conductors VOP, VON.

[0066] As Figure 5 shown, a periodic signal at the reference frequency f0 is presented to the transformer-coupled input buffer 200 on conductors VIP, VIN. At Figure 1In the frequency synthesizer circuit 100, these reference frequency signals are generated by the clock generator / buffer 110. The input signals at the conductors VIP and VIN have opposite phases (e.g., 180° out of phase with each other). The output of the transformer-coupled input buffer 200 drives the conductors VOUTP and VOUTN with a periodic signal that includes components at selected harmonics of the reference frequency f0, which is the third harmonic 3f0 in the above example. The signals at the conductors VOUTP and VOUTN have opposite phases.

[0067] The conductors VOUTP and VOUTN apply the periodic signal including the third harmonic frequency 3f0 component to the bases of the injection transistors 304 and 314 in the ILT 210, respectively. The amplitudes of the third harmonic 3f0 components at the conductors VOUTP and VOUTN from the input buffer 200 are relatively weak. The ILT 210 then operates to amplify this harmonic signal into an output signal at the same third harmonic on the conductors VOP and VON. The signals driven at the conductors VOP and VON by the ILT 210 have opposite phases and have stronger amplitudes than those at the conductors VOUTP and VOUTN.

[0068] The buffers 502 and 504 of the output buffer 220 generate a periodic signal at a harmonic frequency multiple 3f0 at its output RFOUT, and its driving strength is suitable for application to a downstream circuit system (e.g., a mixer in an RF transceiver, a clock input of a data converter, etc.). Thus, the output buffer 220 buffers any input load presented by this downstream circuit system so as not to affect the operation of the ILT 210.

[0069] Figure 6 is a flowchart showing an example method of generating a periodic signal at a selected multiple of an input reference frequency using the circuit described above in conjunction with Figures 1 - 5 description to generate a periodic signal at a selected multiple of the input reference frequency.

[0070] In process block 600, the resonant tank circuits 351 and 361 of the input buffer 200 are tuned to a selected multiple m of the reference frequency f0, e.g., tuned to a frequency multiple that matches the multiplier to be applied by the injection-locked oscillator. For an example of the injection-locked tripler (ILT) 210, in process block 600, the resonant tank circuits 351 and 361 are tuned to resonate at the third harmonic of the reference frequency f0 (e.g., 3f0). In an example implementation, the resonant tank circuits 351 and 361 are tuned by applying a control word to the switched-capacitor type variable capacitors 354 and 364. In some implementations, the resonant tank circuits in the injection-locked oscillator (e.g., ILT 210) can also be tuned to the same frequency in process block 600.

[0071] In process block 602, an input signal at a reference frequency f0 is applied to the transistors of input buffer 200 via corresponding input buffers. In the example described above, a clock generator or buffer (e.g., Figure 1 clock generator / buffer 100 of

[0072] ) generates or receives a periodic signal at reference frequency f0 and applies opposite phase (180°) forms of the signal to conductors VIP, VIN. These conductors VIP, VIN are inductively coupled via inductors 356, 366 to the bases of bipolar transistors 350, 360 that receive the input reference signal and a DC bias voltage, respectively. In this example, transistors 350, 360 are biased in class AB by a DC bias voltage that is slightly below the threshold voltage of transistors 350, 360 (e.g., the threshold voltage of the base-emitter junction). This bias condition favors non-linearity in the collector current at, for example, the harmonics of interest at reference frequency f0. m1 ) of the first order, which in turn produces higher harmonic currents from the regenerative feedback.

[0073] Optionally, input buffer 200 can be configured such that inductors 352, 362 in resonant tanks 351, 361 are inductively coupled to input inductors 366, 356, respectively (process block 604). With inductive coupling, an improvement in the overall performance of the ILT can be achieved. However, for simplicity, the circuit can alternatively be used without inductive coupling, but there are some performance trade-offs. For example, it has been observed that inductive coupling at a coefficient k = 0.58 exceeds twice the magnitude of the third harmonic 3f0 compared to no inductive coupling (k = 0).

[0074] In Figure 6In process block 606, the output signal from the input buffer is applied to the input of the injection-locked oscillator. In the example described above, the collectors of transistors 360, 350 are coupled to conductors VOUTP, VOUTN respectively, and the output signal from input buffer 200 is provided. For the example of ILT 210, conductors VOUTP, VOUTN are coupled to the input of ILT 210 at the bases of injection transistors 304, 314. Injecting a signal at a selected harmonic m·f0 (e.g., 3f0) from input buffer 200 causes ILT 210 to oscillate at that frequency, and in process block 608, corresponding output signals are generated at that frequency m·f0 at conductors VOP, VON.

[0075] As described above for Figure 5 the example of frequency doubler 120, output buffer 220 receives and buffers the output signals at conductors VOP, VON. Output buffer 220 drives the corresponding signal at output RFOUT to downstream circuitry.

[0076] The examples described achieve important advantages in the frequency doubler. The regenerative feedback in the transformer-coupled input buffer enhances harmonic conduction at selected harmonics, such as the input reference frequency, by means of collector-to-base coupling induction. Thus, the input buffer can supply an injection current with strong harmonic components to the input of the injection-locked oscillator without correspondingly increasing the bias current to the injection-locked oscillator of the injection transistors, and a corresponding increase in the bias current may burden the resonant tank in the oscillator. Therefore, the frequency doubler provides reduced out-of-band phase noise, thus providing frequency doubling with a high jitter tracking bandwidth. These examples also achieve good sub-harmonic rejection ratio (SHRR) performance.

[0077] Examples implementing into a frequency tripler using bipolar junction transistors are described in this specification because this implementation is advantageous in this context. Aspects of these examples can be advantageously applied to alternative applications, such as frequency doubling by different multiples; and in alternative ways, such as using field effect transistors (e.g., MOSFETs). Therefore, the following description is provided by way of example only and is not intended to limit the true scope of what is claimed.

[0078] As used herein, the terms "terminal", "node", "interconnect", and "pin" are used interchangeably. Unless stated to the contrary specifically, these terms are generally used to denote the interconnect or its ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0079] Unless otherwise stated, "about", "substantially" or "generally" in front of a value means + / - 10% of the stated value. Modifications to the described examples are possible within the scope of the claims, and other examples are possible.

[0080] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be via firmware and / or software programming of the device, via the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0081] A circuit or device described herein as including certain components can in fact be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) can in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party. Although in some example embodiments certain elements are included within an integrated circuit and other elements are external to the integrated circuit, in other example embodiments additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit can be included within the integrated circuit, and / or some of the features shown as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0082] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can in fact be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can in fact be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0083] The use of the phrase "ground" in the foregoing description encompasses chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification.

[0084] Within the scope of the claims, modifications to the described examples are possible, and other examples are possible.

Claims

1. A frequency synthesis circuit, comprising: a first transistor having a first terminal, a second terminal and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a first inductor having a first terminal and having a second terminal coupled to the first terminal of the first transistor; a first capacitor having a first terminal coupled to the first terminal of the first inductor and having a second terminal coupled to the first terminal of the first transistor; a second inductor having a first terminal and having a second terminal coupled to the first terminal of the second transistor; a second capacitor having a first terminal coupled to the first terminal of the second inductor and having a second terminal coupled to the first terminal of the second transistor; a third inductor coupled between the first input and the control terminal of the first transistor; a fourth inductor coupled between the second input and the control terminal of the second transistor; as well as An injection locked oscillator has a first input coupled to the first terminal of the second transistor, and a second input coupled to the first terminal of the first transistor. 2 . The frequency synthesis circuit according to claim 1 , wherein the third inductor is inductively coupled to the second inductor, and the fourth inductor is inductively coupled to the first inductor.

3. The frequency synthesis circuit of claim 1, wherein the control terminals of the first transistor and the second transistor are coupled to a first bias input and a second bias input, respectively.

4. The frequency synthesis circuit of claim 1 , wherein the first input and the second input receive a first input signal and a second input signal at an input frequency, the first input signal and the second input signal being 180° out of phase with each other; And wherein the resonant frequencies of the network of the first inductor and the first capacitor and the network of the second inductor and the second capacitor are selected harmonics of the input frequency.

5. The frequency synthesis circuit according to claim 4, wherein the first capacitor and the second capacitor are variable capacitors.

6. The frequency synthesis circuit according to claim 4, wherein the injection locked oscillator is a frequency tripler; And wherein the resonant frequency is the third harmonic of the input frequency.

7. The frequency synthesis circuit of claim 1, wherein the injection locked oscillator has a first output and a second output; And the circuit further comprises: An output buffer has first and second inputs coupled to the first and second outputs of the injection locked oscillator.

8. The frequency synthesis circuit according to claim 1, wherein the first transistor and the second transistor are bipolar junction transistors.

9. A frequency synthesis circuit, comprising: a first inductor having a first terminal coupled to receive a first input signal at an input frequency and having a second terminal; a second inductor having a second terminal coupled to receive a second input signal at the input frequency and out of phase with respect to the first input signal, the second inductor having a second terminal; a first transistor having a first terminal, a second terminal coupled to a common terminal, and a control terminal coupled to the second terminal of the first inductor; a second transistor having a first terminal, a second terminal coupled to the common terminal, and a control terminal coupled to the second terminal of the second inductor; a first resonant tank circuit comprising an inductor and a capacitor coupled in parallel between a power supply terminal and the first terminal of the first transistor, the first resonant tank circuit being tuned to a selected harmonic of the input frequency; a second resonant tank circuit comprising an inductor and a capacitor coupled in parallel between the power supply terminal and the first terminal of the second transistor, the second resonant tank circuit being tuned to the selected harmonic of the input frequency; as well as An injection locked oscillator has an input coupled to the first terminal of the first transistor and the second transistor. 10 . The frequency synthesis circuit of claim 9 , wherein the first inductor and the second inductor are capacitively coupled to the control terminals of the first transistor and the second transistor, respectively.

11. The frequency synthesis circuit according to claim 10, further comprising: First and second bias inputs are coupled to the control terminals of the first and second transistors, respectively, and the first and second bias inputs receive bias voltages selected to bias the first and second transistors in a class AB mode of operation.

12. The frequency synthesis circuit of claim 9, wherein the capacitors of the first resonant tank circuit and the second resonant tank circuit are variable capacitors, each variable capacitor being controllable to tune the resonant frequencies of the first resonant tank circuit and the second resonant tank circuit, respectively, to the selected harmonics of the input frequency.

13. The frequency synthesis circuit according to claim 9, wherein the inductor of the second resonant tank circuit is inductively coupled to the first inductor, and the inductor of the first resonant tank circuit is inductively coupled to the second inductor.

14. The frequency synthesis circuit according to claim 9, wherein the injection locked oscillator comprises: a first injection transistor having a first terminal, a control terminal coupled to the first conduction terminal of the second transistor, and a second terminal coupled to a common terminal; a second injection transistor having a first terminal, a control terminal coupled to the first terminal of the first transistor, and a second terminal coupled to the common terminal; a first oscillator resonant tank circuit comprising an inductor and a capacitor (306) coupled in parallel between the power supply terminal and the first terminal of the first injection transistor; a second oscillator resonant tank circuit comprising an inductor and a capacitor coupled in parallel between the power supply terminal and the first terminal of the second injection transistor; A first oscillator transistor and a second oscillator transistor are coupled to the first oscillator resonant tank circuit and the second oscillator resonant tank circuit, respectively, and have control terminals cross-coupled to each other.

15. The frequency synthesis circuit according to claim 14, further comprising: An output buffer has first and second inputs coupled to the first terminals of the first injection transistor and the second injection transistor, respectively.

16. A circuit comprising: a first transistor having a first terminal, a second terminal and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a first inductor having a first terminal and having a second terminal coupled to the first terminal of the first transistor; a first capacitor having a first terminal coupled to the first terminal of the first inductor and having a second terminal coupled to the first terminal of the first transistor; a second inductor having a first terminal and having a second terminal coupled to the first terminal of the second transistor; a second capacitor having a first terminal coupled to the first terminal of the second inductor and having a second terminal coupled to the first terminal of the second transistor; a third inductor coupled between the first input and the control terminal of the first transistor; A fourth inductor is coupled between the second input and the control terminal of the second transistor.

17. The circuit of claim 16, wherein the third inductor is inductively coupled to the second inductor, and the fourth inductor is inductively coupled to the first inductor.

18. The circuit of claim 16, wherein the control terminals of the first and second transistors are coupled to first and second bias inputs, respectively.

19. The circuit of claim 16, wherein the first input and the second input receive a first input signal and a second input signal at an input frequency, the first input signal and the second input signal being 180° out of phase with each other; And wherein the resonant frequencies of the network of the first inductor and the first capacitor and the network of the second inductor and the second capacitor are selected harmonics of the input frequency.

20. The circuit of claim 19, wherein the first capacitor and the second capacitor are variable capacitors.

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