Pixel circuit and image sensor

Abstract

The present invention provides a pixel circuit and an image sensor, the pixel circuit including: a photodiode configured to operate in a photovoltaic mode and accumulate a charge corresponding to an amount of incident light; a reset transistor configured to reset the photodiode accumulated charge; and a peak holding circuit configured to hold an output corresponding to the photodiode accumulated charge, the peak holding circuit including a peak holding transistor connected to an output terminal of the photodiode, a switching transistor configured to turn on / off an output of the peak holding transistor, and a holding capacitor configured to hold an output of the switching transistor. The peak hold transistor operates in a state where there is no carrier charge or only one carrier charge on the channel.

Description

Technical Field

[0001] The present disclosure generally relates to a pixel circuit and an image sensor, each including a photodiode that operates in a photovoltaic mode and accumulates charge corresponding to an amount of incident light, and a peak hold circuit. Background Art

[0002] Photodiodes for image sensors typically operate in a logarithmic region and a linear region. In the logarithmic region, the photodiode operates with a forward bias and exhibits a logarithmic response to incident light; in the linear region, the photodiode operates with a reverse bias and a partial forward bias and exhibits a linear response to incident light.

[0003] One example discloses a pixel circuit using such a photodiode. The pixel circuit includes a peak hold circuit that holds a peak of the photodiode output, thereby eliminating flicker caused by an LED light source.

[0004] As described above, when the peak hold circuit is provided, the peak hold transistor performs a floating gate operation. Therefore, due to positive feedback, noise increases. Summary of the Invention

[0005] A pixel circuit according to the present disclosure includes: a photodiode configured to operate in a photovoltaic mode and accumulate charge corresponding to an amount of incident light; a reset transistor configured to reset the accumulated charge of the photodiode; and a peak hold circuit configured to hold an output corresponding to the accumulated charge of the photodiode, the peak hold circuit including a peak hold transistor connected to an output terminal of the photodiode, a switch transistor configured to turn on / off an output of the peak hold transistor, and a hold capacitor configured to hold an output of the switch transistor. The peak hold transistor operates in a state where there is no carrier charge or only one carrier charge in the channel.

[0006] An image sensor according to the present disclosure includes: a plurality of pixels; a plurality of analog-to-digital converters; and a horizontal scanning circuit. Each of the pixels includes (1) a photodiode configured to operate in a photovoltaic mode and accumulate charge corresponding to an incident light amount, (2) a reset transistor configured to reset the accumulated charge of the photodiode, (3) a peak hold circuit configured to hold an output corresponding to the accumulated charge of the photodiode, the peak hold circuit including (i) a peak hold transistor connected to the output terminal of the photodiode, (ii) a switch transistor configured to turn on / off the output of the peak hold transistor, and (iii) a holding capacitor configured to hold the output of the switch transistor, and (4) a source follower circuit configured to output the voltage held in the holding capacitor of the peak hold circuit as a signal voltage. The peak hold transistor operates in a state where no carrier charge or only one carrier charge exists in the channel. The plurality of analog-to-digital converters convert the respective signal voltages output from the source follower circuits of the plurality of pixels into digital signals. The horizontal scanning circuit serially outputs the digital signals.

[0007] In the pixel circuit and the image sensor according to the present disclosure, by restricting the movement of charges in the peak hold transistor, positive feedback noise can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described based on the following diagrams, where:

[0009] Figure 1 is a diagram illustrating a pixel circuit configuration as a premise of the present disclosure;

[0010] Figure 2 is a diagram illustrating the capacitance around the peak hold transistor PH;

[0011] Figure 3A is a diagram illustrating the potential state of the peak hold transistor PH in a strong inversion state;

[0012] Figure 3B is a diagram illustrating the potential state of the peak hold transistor PH in a weak inversion state;

[0013] Figure 4 is a diagram illustrating the relationship between frequency and noise power;

[0014] Figure 5 is a diagram illustrating a state where no charge (no electrons) exists in the channel region;

[0015] Figure 6 is a circuit diagram in a case where charge (holes) is injected from the drain of the p-channel peak hold transistor PH to operate the peak hold circuit, and the amount of injected holes is limited by the Tvct transistor;

[0016] Figure 7 is a timing diagram for circuit operations in Figure 6 ;

[0017] Figure 8 is a diagram illustrating an image sensor with a two-dimensional pixel arrangement according to an embodiment;

[0018] Figure 9 is a description of Figure 8 the timing diagram for image sensor operations in

[0019] Figure 10 is a diagram illustrating the configuration in the case of providing Figure 6 multiple pixels in and illustrates two pixels;

[0020] Figure 11 is a diagram illustrating another configuration of a pixel circuit;

[0021] Figure 12 is a diagram illustrating yet another configuration of a pixel circuit;

[0022] Figure 13 is a diagram illustrating the configuration in the case of providing Figure 12 multiple pixels in and illustrates two pixels; and

[0023] Figure 14 is a diagram illustrating the relationship between the signal current of the output PDout of the photodiode PD, the output PHout of the peak hold circuit, and the signal-to-noise ratio S / N.

[0024] Explanation of reference numerals in the figures

[0025] 40: Output line;

[0026] 200: Image sensor.

[0027] 210: Pixel array

[0028] 212: Vertical scanning circuit

[0029] 214: Analog-to-digital converter 216: Horizontal scanning circuit

[0030] B: Reset power supply

[0031] bias: Bias transistor

[0032] Cpd: Capacitance

[0033] Csig: Holding capacitance

[0034] Cox: Gate capacitance

[0035] e: Electron mobility fc, fcph, fcpd: Cutoff frequency H: Level

[0036] Isig: Logarithm (Log)

[0037] Injection: Injection power supply

[0038] k: Boltzmann constant

[0039] L: Gate length

[0040] load: Load transistor MOSFET: Transistor

[0041] N: Noise

[0042] P: Pixel

[0043] PD: Photodiode PDout, PHout: Output PH: Peak hold transistor RESET: Reset potential

[0044] RST: Reset transistor

[0045] SEL: Select transistor

[0046] SF: Source follower transistor

[0047] S / N: Signal-to-noise ratio

[0048] SWsig: Switch transistor

[0049] T: Absolute temperature

[0050] Ton / off: Switch transistor

[0051] Tvct: Voltage control transistor

[0052] t0, t1, t2: Time

[0053] Vg: Gate voltage

[0054] Vpd: Output voltage

[0055] Vt: Threshold voltage Detailed implementation manners

[0056] Embodiments of the present disclosure are described below with reference to the accompanying drawings. The following embodiments do not limit the present disclosure, and configurations obtained by selectively combining multiple descriptions are also included in the present disclosure.

[0057] Configuration of the pixel circuit

[0058] Figure 1 is a diagram for explaining the configuration of the pixel circuit that is a prerequisite for the present disclosure.

[0059] The photodiode PD accumulates charge (electrons in this case) based on the incident light. The cathode of the photodiode PD serves as the output terminal, and the anode is connected to a power supply (e.g., ground). Thus, the output voltage Vpd of the photodiode PD is the output signal.

[0060] One end (the drain) of the reset transistor RST is connected to the cathode of the photodiode PD, and the other end (the source) of the reset transistor RST is connected to a power supply (e.g., ground) through the reset power supply B. In this example, the reset transistor RST is an n-channel transistor.

[0061] The cathode of the photodiode PD is connected to the gate of the peak-holding transistor PH. The peak-holding transistor PH is a p-channel transistor. The drain of the peak-holding transistor PH is connected to a power supply (e.g., ground). The peak-holding circuit includes the peak-holding transistor PH and the holding capacitor Csig. In Figure 1 the example, the peak-holding circuit further includes a bias transistor bias, a load transistor load, and a switching transistor SWsig.

[0062] The source of the switching transistor SWsig is connected to the source of the peak-holding transistor PH. One end of the holding capacitor Csig is connected to the drain of the switching transistor SWsig. The other end of the holding capacitor Csig is connected to a power supply (e.g., ground). The switching transistor SWsig is a p-channel transistor.

[0063] The drain of the switching transistor SWsig is connected to the gate of the source-follower transistor SF. The drain of the source-follower transistor SF is connected to a power supply, and the source is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the output line 40.

[0064] The source of the peak-holding transistor PH is also connected to a power supply through the bias transistor and the load transistor. The bias transistor and the load transistor are p-channel transistors.

[0065] The gate voltage of the load transistor load is set to a DC voltage that enables the peak-holding transistor PH to perform a source-follower operation. To inject holes into the holding capacitor Csig, a negative pulse is applied to the bias transistor bias.

[0066] A row selection signal is provided to the gate of the selection transistor SEL. When the row selection signal becomes high, a signal corresponding to the gate voltage of the readout source-follower transistor SF is output to the output line 40.

[0067] After the reset transistor RST is turned on to reset the photodiode PD, the bias transistor and the switching transistor SWsig are turned on to inject charge (holes) into the holding capacitor Csig.

[0068] Thereafter, the bias transistor is turned off to discharge the excess charge through the peak-holding transistor PH. As a result, the holding capacitor Csig is placed in the reset state. In this state, within one frame period, the signal provided from the peak-holding transistor PH is accumulated in the holding capacitor Csig through the switching transistor SWsig. As described above, the output voltage corresponding to the accumulated charge of the photodiode PD is provided to the gate of the peak-holding transistor PH. Therefore, the charge corresponding to the incident light amount of the photodiode PD within one frame period is accumulated in the holding capacitor Csig.

[0069] In addition, when the switching transistor SWsig is turned off and the selection transistor SEL is turned on, the voltage signal corresponding to the charge accumulated in the holding capacitor Csig is read out to the output line 40.

[0070] In this example, the gate of the peak-holding transistor PH is only connected to the output terminal of the photodiode. Therefore, the gate of the peak-holding transistor PH is in a floating state, and the peak-holding transistor PH performs a floating-gate operation. As a result, due to positive feedback, the noise increases.

[0071] Note that in this embodiment, the MOSFET is configured to act as a transistor.

[0072] Figure 2 The capacitance around the peak-holding transistor PH is illustrated. In this example, an n-channel in which the carriers of the peak-holding transistor PH are electrons is described. In the case of a p-channel, the carriers are holes, and the polarity of the potential in the figure is opposite.

[0073] As shown in the figure, the capacitance Cpd of the photodiode PD is connected to the gate of the peak-holding transistor PH, and the holding capacitor Csig is connected to the source. In addition, the peak-holding transistor PH includes a gate capacitance Cox.

[0074] Figure 3A and Figure 3B are diagrams illustrating the potential states of the peak-holding transistor PH. Figure 3A Illustrates the potential in the strong inversion state, Figure 3B Illustrates the potential in the weak inversion state. In the figure, the potential is negative on the upper side and positive on the lower side.

[0075] As shown in the figure, in the strong inversion state where the gate voltage Vg exceeds the threshold voltage Vt, the potential on the holding capacitor Csig side further shifts to the negative side, and the charge (electrons) flows across the potential barrier of the gate to the power supply. On the contrary, in the weak inversion state where the gate voltage Vg does not exceed the threshold voltage Vt, the potential of the holding capacitor Csig is lower than the potential barrier of the gate, and a small amount of charge (electrons) randomly flows across the potential barrier of the gate to the power supply.

[0076] Describes the noise characteristics of a peak-holding circuit including a peak-holding transistor PH and a holding capacitor Csig. The noise is denoted as N when the gate voltage is fixed and the noise band is limited. In addition, the Boltzmann constant is denoted as k and the absolute temperature is denoted as T.

[0077] Strong inversion region

[0078] In the strong inversion region, in a limited band (in-phase) where the noise is limited to less than or equal to the cut-off frequency fc, the noise N is expressed as follows:

[0079] (1 + A)*N,

[0080] where A = (2 / 3)*Cox / Cpd.

[0081] In addition, in the full band where the frequency is not restricted, the noise N is expressed as follows:

[0082] (1 + A) 1 / 2 *[(2 / 3)*kT / Csig] 1 / 2 .

[0083] Weak inversion region

[0084] In the weak inversion region, in a limited band (in-phase) where the frequency band is limited to less than or equal to the cut-off frequency fc, the noise N is expressed as follows:

[0085] (1 + A)*N,

[0086] where A = (1 / 2)*Cox / Cpd.

[0087] Therefore, the noise is amplified by a factor of (1 + A) by the peak-holding circuit.

[0088] In addition, in the full band where the frequency band is not restricted, the noise is expressed as follows:

[0089] (1 + A) 1 / 2 *[(1 / 2)*kT / Csig] 1 / 2 .

[0090] In a limited band (where the frequency band is limited to less than or equal to the cut-off frequency fc), the noise is amplified by a factor of (1 + A) by the peak-holding circuit. This is because the peak-holding circuit performs an in-phase operation to cause positive feedback. In contrast, at frequencies greater than or equal to the cut-off frequency fc, positive feedback does not occur due to a 90-degree phase rotation. Therefore, in the full band, the noise is amplified by a factor of (1 + A) 1 / 2 times. Note that, as described above, the value of "A" is different between the strong inversion region and the weak inversion region.

[0091] Figure 4It is a chart showing the relationship between frequency and noise power. As shown in the figure, noise increases at frequencies less than or equal to the cut-off frequency fc. Noise decreases at frequencies greater than or equal to the cut-off frequency.

[0092] Note that whether the peak-hold circuit performs a limited-band operation or a full-band operation is determined by the circuits and signal processing in subsequent stages.

[0093] As described above, when a peak-hold circuit including a peak-hold transistor PH and a hold capacitor Csig is set up, due to positive feedback, noise increases.

[0094] Embodiment 1

[0095] According to the noise analysis, when there is only one carrier charge (hereinafter simply referred to as charge) in the channel of the peak-hold transistor PH, or when there is no charge in the channel of the peak-hold transistor PH, noise increase due to positive feedback does not occur.

[0096] Figure 5 The state where there is no charge (no electrons) in the channel region is illustrated.

[0097] The current in the case where there is only one electron in the channel region is estimated. When one electron flows through the gate channel, the current is expressed as follows,

[0098] I = kT * (e / L 2 ).

[0099] Where k is the Boltzmann constant, T is the absolute temperature, e is the electron mobility, and L is the gate length of the peak-hold transistor PH (in this case, a MOSFET).

[0100] When assuming L = 1μm and e = 0.02m 2 / V / s, the current value is approximately 10nA. Therefore, it can be considered that when the current (1nA) is one order of magnitude lower than this value, the peak-hold circuit operates in a state where there is only one electron.

[0101] Note that through recent microfabrication technologies, the L value can be reduced to less than or equal to 0.01μm, and the electron mobility e can be increased to approximately 0.15m 2 / V / s. Therefore, even at currents of 1nA or higher, the peak-hold circuit can be sufficiently operated with only one electron. This charge-limited mode is called the single-carrier transfer mode.

[0102] Therefore, when the peak-hold circuit operates at a level of approximately 1nA, the peak-hold circuit performs an operation in the single-carrier transfer mode, and noise increase due to positive feedback does not occur.

[0103] In this state, the noise N in the limited bandwidth (in-phase) is N = N, and the noise N in the full bandwidth is N = ((1 / 2)*kT / Csig) 1 / 2 holds true.

[0104] In this embodiment, the number of charges (electrons) present in the channel of the peak hold transistor PH is set to one or less. This makes it possible to suppress the occurrence of noise due to positive feedback. In the case of limiting the number of charges as described above, since the current value is small, the peak hold transistor PH performs full bandwidth operation.

[0105] As described above, in this embodiment, the Figure 1 drain current of the drain output of the peak hold transistor PH in the circuit is limited, causing the peak hold circuit to operate in the single carrier transfer mode. This makes it possible to prevent an increase in noise due to positive feedback.

[0106] Embodiment 2

[0107] Figure 6 is a circuit diagram in the case where charges (holes) are injected from the drain of the p-channel peak hold transistor PH to operate the peak hold circuit. Figure 7 is to illustrate Figure 6 the timing diagram of the circuit operation in

[0108] In this example, the drain of the p-channel peak hold transistor PH is connected to the injection power supply Injection through the voltage control transistor Tvct. The source of the peak hold transistor PH is connected to the holding capacitor Csig and the gate of the source follower transistor SF through the switching transistor SWsig.

[0109] The reset transistor RST is turned on to reset the output of the photodiode PD. Next, the injection power supply Injection is set to the H level for a short period of time to supply holes to the holding capacitor Csig through the peak hold transistor PH and the switching transistor SWsig.

[0110] After the signal integration period corresponding to one frame, the gate of the switching transistor SWsig is set to the H level (off for a p-channel transistor), and the selection transistor SEL is set to the H level (on). As a result, the signal voltage held in the holding capacitor Csig is output to the output line 40 through the source follower transistor SF and the selection transistor SEL.

[0111] At this time, if the drain voltage of the peak-holding transistor PH is too high, the drain current will increase. In this embodiment, the voltage control transistor Tvct is provided between the injection power supply and the drain of the peak-holding transistor PH. Further, the voltage control transistor Tvct performs control so that the drain voltage of the peak-holding transistor PH does not become too high. This makes it possible to reduce the amount of charge injected into the peak-holding transistor PH and to achieve operation in a single carrier transfer mode.

[0112] Configuration of the image sensor

[0113] Figure 8 FIG. 7 is a diagram illustrating the image sensor 200 in which pixels according to any embodiment are two-dimensionally arranged. The pixel array 210 includes pixels P arranged in m columns * n rows (m * n) as described above, that is, including m pixels in the horizontal direction and n pixels in the vertical direction. The vertical scanning circuit (V-Scan) 212 sequentially selects rows of pixels in the vertical direction. The pixels in each column are connected to their respective analog-to-digital converters (ADCs) 214 through respective vertical readout lines. The horizontal scanning circuit (H-Scan) 216 is connected to the analog-to-digital converters (ADCs) 214, and the image signals of the respective pixels are sequentially output from the horizontal scanning circuit (H-Scan) 216.

[0114] Figure 9 is illustrative of Figure 8 the timing chart of the image sensor operation in Figure 7 The timing charts of the injection power supply Injection and SWsig shown in

[0115] In the (k - 1)-th row, the reset transistor RST is turned on to reset the photodiode PD. The reset is performed for each vertical period (= one frame period). Further, the exposure starts after one reset. In addition, the signal is read out shortly before the next reset. As described above, the selection transistor SEL is turned on, and the signal accumulated in the holding capacitor Csig is read out to the output line 40. This control is performed in response to a signal from the vertical scanning circuit (V-scan) 212. The read-out signal is supplied to the analog-to-digital converter (ADC) 214 and converted into a digital signal. This operation is performed simultaneously on m pixels on one horizontal line. Thereafter, the horizontal scanning circuit (H-scan) 216 sequentially outputs the digital signals of the m pixels.

[0116] Next, by shifting the horizontal period by 1H, the same operation is performed in the k-th row. By repeating this operation n times, the signals of all m * n pixels can be read out.

[0117] Embodiment 3

[0118] Figure 10 is illustrative of providing Figure 6A diagram of the configuration in the case of multiple pixels, and two pixels are illustrated.

[0119] As shown in the figure, the drains of the peak-holding transistors PH of multiple pixels in a row are connected to a voltage control transistor Tvct. Therefore, a voltage control transistor Tvct can control the drain voltages of the peak-holding transistors PH of multiple pixels.

[0120] Note that the number of pixels controlled by a voltage control transistor Tvct is optional. For example, all the pixels in a row can be controlled by a voltage control transistor Tvct.

[0121] Embodiment 4

[0122] Figure 11 is a diagram illustrating the configuration according to Embodiment 4. The basic configuration is the same as that in Figure 6 However, in this example, the gate of the voltage control transistor Tvct is connected to the output terminal of the photodiode PD. Therefore, the gate voltage of the voltage control transistor Tvct varies with the output of the photodiode PD together with the gate of the peak-holding transistor PH. This makes it possible to eliminate the influence of the voltage variation in the output of the photodiode PD.

[0123] Embodiment 5

[0124] Figure 12 is a diagram illustrating the configuration according to Embodiment 5. In this example, holes are injected from the source side of the peak-holding transistor PH.

[0125] The source of the peak-holding transistor PH is connected to the power supply through a switching transistor Ton / off and a voltage control transistor Tvct.

[0126] In this circuit, after holes are injected into the holding capacitor Csig through the peak-holding transistor PH and the switching transistor SWsig, the switching transistor Ton / off is turned on, and the source voltage of the peak-holding transistor PH is controlled by the voltage control transistor Tvct. In other words, by controlling the source voltage of the peak-holding transistor PH to a predetermined value, the number of charges on the channel is reduced to one or less, resulting in operation in a single-carrier transfer mode.

[0127] Embodiment 6

[0128] Figure 13 is a diagram illustrating the configuration in the case of providing multiple pixels in Figure 12 and two pixels are illustrated. As shown in the figure, the sources of the peak-holding transistors PH of multiple pixels are connected to a voltage control transistor Tvct. Therefore, the source voltages of the peak-holding transistors PH of multiple pixels can be controlled by a voltage control transistor Tvct.

[0129] Other effects

[0130] Figure 14 It is a graph showing the relationship between the output PDout of the photodiode PD, the signal current of the output PHout of the peak hold circuit, and the signal-to-noise ratio S / N.

[0131] The thermal noise of the photodiode PD depends on the signal current and has a wide noise bandwidth. According to the prior art (Yang Ni. New Imaging Technologies, France, "QLOG - Logarithmic CMOS Pixel with Single - Electron Detection Capability" Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan, 30 May - 2 June 2017), the signal - to - noise ratio of the photodiode PD has a constant value in the logarithmic region (as shown by the solid line in Figure 14 ). According to the prior art, when the capacitance Cpd of the photodiode PD is 1 fF, the signal - to - noise ratio is 29 dB, which is not a good value.

[0132] When the peak hold circuit operates in the single - carrier transfer mode as in this embodiment, the operating bandwidth is narrowed. Therefore, the noise is reduced by band - limiting, and when the signal is acquired through the peak hold circuit, the signal - to - noise ratio is improved (as shown by the dashed line in Figure 14 ).

[0133] Therefore, according to this embodiment, a clear image can be obtained in the region where the signal current is large.

[0134] In the figure, "fcph" is the cut - off frequency of the peak hold circuit, and "fcpd" is the cut - off frequency of the photodiode PD.

Claims

1. A pixel circuit, comprising: a photodiode configured to operate in a photovoltaic mode and accumulate charge corresponding to an amount of incident light; a reset transistor configured to reset the accumulated charge of the photodiode; as well as A peak hold circuit configured to hold an output corresponding to the accumulated charge of the photodiode, the peak hold circuit comprising a peak hold transistor connected to the output terminal of the photodiode, a switch transistor configured to turn on / off the output of the peak hold transistor, and a hold capacitor configured to hold the output of the switch transistor, wherein The peak hold transistor operates in a state where there is no carrier charge or only one carrier charge on the channel.

2. The pixel circuit according to claim 1, wherein The peak hold transistor is a p-channel transistor and includes a drain connected to the voltage control transistor, and The injection of charge is controlled by adjusting the drain voltage of the peak hold transistor.

3. The pixel circuit according to claim 1, wherein The peak hold transistor is a p-channel transistor and includes a source connected to the voltage control transistor, and The injection of charge is controlled by adjusting the source voltage of the peak hold transistor.

4. The pixel circuit according to claim 2, wherein The voltage control transistor includes one end connected to an injection power supply for supplying charge for resetting the holding capacitor, and the other end connected to the drain of the peak holding transistor, and Charge from the injection power supply is supplied to the holding capacitor through the voltage control transistor and the peak hold transistor.

5. The pixel circuit according to claim 3, wherein A vertical scanning circuit; The voltage control transistor includes one end connected to a predetermined negative power supply and the other end connected to the source of the peak holding transistor, and The peak hold transistor is source-follower driven to supply charge from a gate of the peak hold transistor to the hold capacitor.

6. The pixel circuit according to claim 1, wherein the peak holding transistor operates under a condition where the drain current is less than or equal to kT*e / L2, and there is no charge or only a single charge on the channel of the peak holding transistor PH, wherein k is the Boltzmann constant, T is the absolute temperature, e is the mobility of the electron, and L is the gate length of the peak holding transistor.

7. An image sensor, comprising: Multiple pixels; Multiple analog-to-digital converters; as well as A horizontal scanning circuit, wherein Each of the pixels includes a photodiode configured to operate in a photoelectric mode and accumulate charges corresponding to an amount of incident light, a reset transistor configured to reset the accumulated charges of the photodiode, and a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, wherein the peak hold circuit includes a peak hold transistor connected to an output terminal of the photodiode, a switch transistor configured to turn on / off the output of the peak hold transistor, a hold capacitor configured to hold the output of the switch transistor, and a source follower circuit configured to output a voltage held in the hold capacitor of the peak hold circuit as a signal voltage, The peak hold transistor operates in a state where there is no carrier charge or only one carrier charge on its channel. The analog-to-digital converter converts a signal voltage output from the source follower circuit of the plurality of pixels into a digital signal, and The horizontal scanning circuit outputs the digital signal in series.

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