First medium GaN HEMT vertical structure chip and preparation method thereof

Abstract

The invention discloses a first medium GaN HEMT vertical structure chip and a preparation method thereof, and belongs to the technical field of first medium layer preparation, and the method comprises the steps: cleaning and drying a GaN HEMT vertical structure epitaxial wafer, passivating a SiN barrier layer, and positioning a mark; performing photoetching to form a source window and an electrode contact area, and performing evaporation to form a source electrode; performing photoetching ion implantation to form a chip isolation region; after the surface SiN is etched, photoetching a gate electrode contact area and forming a gate electrode through evaporation; growing a passivation layer, etching conductive channels of a source electrode and a grid electrode, and performing evaporation to obtain a field plate; after deep etching and trepanning, photoetching a drain electrode contact area at the bottom and forming a drain electrode through evaporation; and respectively growing passivation layers at the bottom and the top, and photoetching an electrode lead-out region to obtain the first medium GaN HEMT vertical structure chip. The insulating property of the device is remarkably improved, the leakage current is reduced, the conductivity, the breakdown voltage and the reliability of the device are improved, and a foundation is laid for application in the field of high-frequency and high-power electronic devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of pre-dielectric layer preparation, and specifically relates to a pre-dielectric GaN HEMT vertical structure chip and a preparation method thereof. Background Art

[0002] With the continuous progress of semiconductor technology and the rapid development of the power electronics field, higher requirements are put forward for high-performance and high-reliability GaN HEMT devices. As an important part of GaN HEMT devices, the dielectric layer is of great significance for improving the insulation performance of the devices, reducing the leakage current, and achieving efficient current transmission. The pre-dielectric layer preparation technology, as an important method for realizing high-performance GaN HEMT devices, can achieve better device performance and stability by first depositing the dielectric layer during the preparation process and then performing subsequent process steps.

[0003] The pre-dielectric layer preparation technology has been widely used in the research of GaN HEMT devices. By optimizing parameters such as the dielectric layer material, thickness, and deposition process, lower leakage current, higher insulation performance, and better device performance can be achieved. At present, certain progress has been made in the research on pre-dielectric GaN HEMT vertical structure chips, including the selection and optimization of dielectric layer materials, the exploration and improvement of deposition processes, and the integration technology of the dielectric layer and subsequent electrode structures.

[0004] Although certain achievements have been made in the research on pre-dielectric GaN HEMT vertical structure chips, there are still some challenges. First, the selection and optimization of dielectric layer materials are one of the key technologies, and factors such as the insulation performance, thermal stability, and compatibility with GaN of the materials need to be considered. Second, the deposition process of the dielectric layer is also one of the difficulties, and parameters such as the deposition rate, temperature, and atmosphere need to be precisely controlled to ensure the quality and performance of the dielectric layer. In addition, the pre-dielectric layer preparation technology also needs to be well integrated and coordinated with the subsequent electrode structure to achieve efficient device preparation and performance optimization. At the same time, how to further improve the insulation performance of the dielectric layer and reduce the leakage current is also one of the important research directions at present. Summary of the Invention

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a pre-dielectric GaN HEMT vertical structure chip and a preparation method thereof, so as to solve the technical problem of how to optimize the dielectric layer material, deposition process, and integration with the subsequent electrode structure of the pre-dielectric GaN HEMT vertical structure chip to improve the insulation performance of the device, reduce the leakage current, and enhance the overall performance.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a preparation method for a pre-dielectric GaN HEMT vertical structure chip, comprising the following steps: 1) After cleaning and drying the GaN HEMT vertical structure epitaxial wafer, first passivate a 80-90 nm thick SiN as the SiN barrier layer, and then perform positioning marks; 2) Photolithograph the window area of the source electrode at the top, and etch away the SiN barrier layer and the SiN dielectric capping layer in the window area; 3) Photolithograph the electrode contact area of the source electrode at the top, evaporate the electrode metal, and after stripping, form the source electrode; 4) Form a chip isolation area at the top by photolithography and ion implantation; 5) Etch the outermost SiN barrier layer, and retain the SiN dielectric capping layer; 6) Photolithograph the electrode contact area of the gate electrode at the top, evaporate the electrode metal, and form the gate electrode; 7) Grow a passivation layer at the top, etch out the conductive channels of the source electrode and the gate electrode, and after evaporation, obtain the field plate; 8) Perform deep etching and opening on the GaN HEMT vertical structure epitaxial wafer; 9) Photolithograph the electrode contact area of the drain electrode at the bottom, evaporate the electrode metal, and after stripping, form the drain electrode; 10) Grow a passivation layer at the bottom, and photolithograph the drain electrode lead-out area; Photolithograph the gate electrode and the source electrode lead-out areas at the top to obtain the pre-dielectric GaN HEMT vertical structure chip.

[0007] Preferably, in step 1), the preparation method for the GaN HEMT vertical structure epitaxial wafer comprises: sequentially growing a GaN drift region, an AlN insertion layer, an Al X Ga (1-X) N barrier layer and a SiN dielectric capping layer on the pre-treated substrate to obtain the GaN HEMT vertical structure epitaxial wafer; In the Al X Ga (1-X) N barrier layer, 0.15 ≤ X ≤ 0.5.

[0008] More preferably, the pre-treatment conditions of the substrate include: pre-treating the substrate at 1000-1150 °C, and simultaneously introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min; The conditions for growing the GaN drift region include: growing a GaN drift region with a thickness of 0.5 - 50 μm at a growth temperature of 1000 - 1150 °C and a growth rotation speed of 800 - 1200 rpm under a growth pressure of 200 torr by controlling the flow rates of trimethylgallium, N2, H2, NH3, and monosilane; wherein, the flow rate of trimethylgallium is 200 - 1000 sccm / min, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 50 - 200 L / min, the flow rate of NH3 is 1 - 100 L / min, the concentration of monosilane is 200 ppm, and the flow rate is 0 - 500 sccm / min; The carrier blocking layer region is defined by photolithography on the GaN drift region, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000 - 1150 °C, the rotation speed is 800 - 1200 rpm, the growth pressure is 200 torr, and trimethylgallium, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN with a thickness of 150 - 400 nm. Among them, the flow rate of trimethylgallium is 200 - 1000 sccm / min, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 0 - 200 L / min, and the flow rate of NH3 is 0 - 100 L / min.

[0009] Further preferably, the growth conditions of the AlN insertion layer include: growing an extremely thin AlN insertion layer with a thickness of 0 - 2 nm at a growth temperature of 800 - 1100 °C and a growth pressure of 75 torr by simultaneously introducing trimethylaluminum, H2, and NH3; wherein, the flow rate of trimethylaluminum is 0 - 500 sccm / min, the flow rate of H2 is 50 - 200 L / min, and the flow rate of NH3 is 1 - 100 L / min.

[0010] Further preferably, Al X Ga (1-X) The growth conditions of the AlGaN barrier layer include: growing an AlGaN barrier layer with a thickness of 15 - 35 nm at a growth temperature of 800 - 1100 °C, 800 - 1200 rpm, and a growth pressure of 100 torr by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2, and NH3; wherein, the molar percentage of X is 15% - 50%, the flow rate of trimethylgallium is 0 - 500 sccm / min, the flow rate of trimethylaluminum is 50 - 500 sccm / min, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 50 - 200 L / min, and the flow rate of NH3 is 1 - 100 L / min. X Ga (1-X) N barrier layer;

[0011] Further preferably, the conditions for growing the SiN dielectric capping layer include: growing a SiN dielectric capping layer with a thickness of 0.1 - 100 nm at a growth pressure of 200 torr and a temperature of 700 - 1100 °C by adjusting the flow rates of N2, H2, and NH3 and introducing disilane; wherein, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 50 - 200 L / min, the flow rate of NH3 is 1 - 100 L / min, the concentration of disilane is 2%, and the flow rate of disilane is 0 - 500 sccm / min.

[0012] Preferably, in step 2), the depth of the source window region is below the two-dimensional electron gas, and the lithography angle is 60°; inductively coupled plasma etching is used to remove the SiN dielectric capping layer in the window region. In step 3), after soaking in a strong oxidation solution tank before evaporation and then soaking in dilute hydrochloric acid; the source electrode is composed of at least one of Ti, Al, Ni, TiN, and AlSi as the electrode metal. In step 4), the elements for ion implantation include at least one of F, Ar, B, and N; the depth of ion implantation is 0.1 - 20 μm.

[0013] Preferably, in step 6), the gate electrode is a Ti / Al / Ti electrode metal. In step 7), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0014] Preferably, in step 9), the depth of the drain electrode contact region is below the two-dimensional electron gas, and the lithography angle is 60°; the drain electrode is composed of at least one of Ti, Al, Ni, TiN, and AlSi as the electrode metal. In step 10), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0015] The present invention also discloses a pre-dielectric GaN HEMT vertical structure chip, prepared by the above preparation method, including: a GaN HEMT vertical structure epitaxial wafer, and the SiN dielectric capping layer on the top is partially etched in the source window region to expose the surface of the GaN HEMT vertical structure epitaxial wafer. A SiN barrier layer, located above the SiN dielectric capping layer, with a thickness of 80 - 90 nm. A source electrode, forming an ohmic contact with the GaN HEMT vertical structure epitaxial wafer through the source window region. A chip isolation region, located on the top of the GaN HEMT vertical structure epitaxial wafer, formed by lithography and ion implantation. The gate electrode is disposed above the unetched SiN dielectric capping layer and forms a Schottky contact with the SiN dielectric capping layer; The top passivation layer covers the gate and the source, has a conductive channel etched therein, and forms a field plate structure connected to the electrode by evaporation; the top passivation layer is also etched with electrode lead-out areas for the gate and the source for external electrical connection; The drain electrode is located at the bottom of the GaN HEMT vertical structure epitaxial wafer and is connected to the drain region of the GaN HEMT vertical structure epitaxial wafer through a deep etched via hole; The bottom passivation layer covers the drain electrode and is etched with a drain lead-out window.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a preparation method for a vertical structure chip of a pre-medium GaN HEMT. Cleaning and drying ensure the cleanliness of the epitaxial wafer surface, providing a good foundation for subsequent process steps. As a barrier layer, SiN has good insulation performance and chemical stability, can effectively isolate the influence of the external environment on the device, and improve the insulation performance of the device. The positioning marks provide an accurate positioning reference for subsequent lithography steps. Through the lithography and etching steps, the window area of the source electrode is precisely defined, providing a position for subsequent electrode metal evaporation. Removing the SiN dielectric capping layer ensures direct contact between the electrode metal and the GaN material, reducing the contact resistance. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is evaporated. After stripping, the source electrode is formed, ensuring the accurate formation of the source electrode. The selection of the electrode metal and the optimization of the evaporation process help reduce the contact resistance between the electrode and GaN and improve the conductivity of the device. The ion implantation technology is used to form the chip isolation region, effectively preventing electrical interference between different devices and improving the integration and reliability of the device. Etching the outermost SiN provides space for the subsequent formation of the gate electrode while maintaining the cleanliness of the device surface, creating favorable conditions for subsequent process steps. By optimizing the lithography and evaporation processes, the accuracy and consistency of the gate electrode can be ensured, thereby improving the overall performance of the device. The growth of the passivation layer protects the device surface and improves the insulation performance and stability of the device. Etching out the conductive channels of the source and gate electrodes ensures the electrical connection between the electrodes and the inside of the device. The formation of the field plate helps optimize the electric field distribution of the device and improve the breakdown voltage of the device. Deep etching to open holes provides space for the subsequent formation of the drain electrode while maintaining the integrity of the device structure. The accurate formation of the drain electrode ensures the complete electrical connection of the device. By optimizing the lithography and evaporation processes, the contact resistance between the drain electrode and GaN can be reduced, improving the conductivity of the device. The growth of the bottom passivation layer further improves the insulation performance and stability of the device. Lithographing the electrode lead-out area ensures the connection between the device and the external circuit. By optimizing the entire preparation process, the present invention successfully solves the technical problems of the dielectric layer material, deposition process, and integration with the subsequent electrode structure, improves the insulation performance of the device, reduces the leakage current, and enhances the overall performance.

[0017] The present invention also discloses a pre-dielectric GaN HEMT vertical structure chip prepared by the above preparation method. SiN is selected as the barrier layer material. SiN can effectively isolate the influence of the external environment on the GaN HEMT device, prevent the intrusion of moisture, impurities, etc., thereby improving the insulation performance and long-term reliability of the device. By precisely controlling the thickness of the SiN layer, while ensuring sufficient insulation performance, the adverse effects of an overly thick dielectric layer on device performance are avoided, such as increasing the contact resistance or affecting the electric field distribution. A uniform dielectric layer can provide more stable insulation performance, while a dense dielectric layer can effectively block leakage current and improve the breakdown voltage of the device. By growing an additional passivation layer in the field plate region, the present invention optimizes the electric field distribution of the device, improves the breakdown voltage and reliability of the device. At the same time, the passivation layer also protects the surface of the device and prevents the external environment from eroding the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; Figure 2 is a schematic structural diagram of the GaN HEMT vertical structure power chip disclosed by the present invention; Figure 3 is a flowchart of the preparation method of the pre-dielectric GaN HEMT vertical structure chip disclosed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0021] The following further describes the present invention in detail with reference to the accompanying drawings: A preparation method for the vertical structure epitaxy of GaN HEMT disclosed by the present invention includes the following steps: GaN substrate preparation: Select an n-type doped GaN substrate with a thickness of 300 - 1000 μm as the growth basis. Selecting an appropriate thickness of the GaN substrate can ensure the uniformity and stability of the epitaxial layer. A thicker substrate usually has better thermal stability and mechanical strength, which is beneficial to the subsequent epitaxial growth process.

[0022] GaN substrate treatment: Pretreat the GaN substrate at a temperature of 1000 - 1150 °C (preferably 1100 °C). Meanwhile, introduce nitrogen (N2) at a rate of 0 - 100 L / min (preferably 0 L / min), hydrogen (H2) at a rate of 50 - 200 L / min (preferably 120 L / min), and ammonia (NH3) at a rate of 1 - 100 L / min (preferably 50 L / min) to prepare for the subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for the subsequent epitaxial growth.

[0023] GaN drift region growth: In the temperature range of 1000 - 1150 °C (preferably 1100 °C) and at a growth pressure of 200 torr, grow a GaN drift region with a thickness of 0.5 - 50 μm (preferably 7 μm) by precisely controlling the flow rates of trimethylgallium (TMGA), N2, H2, NH3, and monosilane (SiH4). This layer is crucial for the chip performance. Among them, the introduction rate of TMGA is 200 - 1000 sccm / min (preferably 600 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 10 L / min), the introduction rate of H2 is 50 - 200 L / min (preferably 90 L / min), the introduction rate of NH3 is 1 - 100 L / min (preferably 45 L / min), the concentration of the first SiH4 is 200 ppm, and the introduction rate is 0 - 500 sccm / min (preferably 10 sccm / min). The growth temperature is 1000 - 1150 °C (preferably 1100 °C), and the growth rotation speed is 800 - 1200 rpm (preferably 1200 rpm). The drift region is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the chip performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the chip.

[0024] Ion implantation: The carrier blocking layer region is defined by lithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. The implantation depth of the N ions is 0.1 - 20 μm (preferably 3 μm).

[0025] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1000 - 1150 °C (preferably 1080 °C), the rotation speed is 800 - 1200 rpm (preferably 1200 rpm), the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled within 150 - 400 nm (preferably 300 nm). The introduction rate of TMGa is 200 - 1000 sccm / min (preferably 500 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 64 L / min), the introduction rate of H2 is 0 - 200 L / min (preferably 120 L / min), and the introduction rate of NH3 is 0 - 100 L / min (preferably 50 L / min). The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0026] AlN insertion layer growth: Subsequently, at a temperature of 800 - 1100 °C (preferably 1000 °C) and a growth pressure of 75 torr, trimethylaluminum (TMAL), H2, and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer with a thickness controlled within 0 - 2 nm (preferably 0.8 nm) to optimize the chip performance. Among them, the introduction rate of TMAL is 0 - 500 sccm / min (preferably 200 sccm / min), the introduction rate of H2 is 50 - 200 L / min (preferably 190 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 5 L / min). The introduction of the insertion layer can optimize the interface characteristics of the chip, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the chip. By precisely controlling the thickness and growth conditions of the insertion layer, the chip performance can be further optimized.

[0027] Al X Ga (1-X) AlGaN barrier layer growth: Then, in the temperature range of 800 - 1100 °C (preferably 1020 °C), at 800 - 1200 rpm (preferably 1000 rpm), and a growth pressure of 100 torr, by adjusting the flow rates of TMGa, TMAL, N2, H2, and NH3 gases, an AlGaN barrier layer with a thickness of 15 - 35 nm (preferably 22 nm) is grownX Ga (1-X) N barrier layer, where the Al component X ranges from 15% to 50% (preferably 20 - 25%). This layer plays a key role in controlling the current magnitude and reliability. Among them, the feeding rate of TMGA is 0 - 500 sccm / min (preferably 80 sccm / min), the feeding rate of TMAL is 50 - 500 sccm / min (preferably 300 sccm / min), the feeding rate of N2 is 0 - 100 L / min (preferably 64 L / min), the feeding rate of H2 is 50 - 200 L / min (preferably 120 L / min), and the feeding rate of NH3 is 1 - 100 L / min (preferably 50 L / min). The barrier layer is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the current transmission characteristics of the chip. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the chip.

[0028] Growth of SiN dielectric capping layer: Finally, at a temperature of 700 - 1100 °C (preferably 1000 °C) and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric capping layer with a thickness of 0.1 - 100 nm (preferably 2 nm) is grown to protect and optimize the chip surface. Among them, the feeding rate of N2 is 0 - 100 L / min (preferably 64 L / min), the feeding rate of H2 is 50 - 200 L / min (preferably 120 L / min), the feeding rate of NH3 is 1 - 100 L / min (preferably 50 L / min), the concentration of the second SiH4 is 2%, and the feeding rate is 0 - 500 sccm / min (preferably 40 sccm / min). The above gases are fed simultaneously. The introduction of the SiN dielectric capping layer can protect the chip surface from the influence of the external environment and improve the stability and reliability of the chip. At the same time, by precisely controlling the growth parameters of the capping layer and introducing an appropriate amount of the second SiH4, the electrical characteristics of the chip surface can be further optimized.

[0029] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0030] During the entire preparation process, the growth of each layer needs to be carried out under strictly controlled temperature, gas flow rate, and doping conditions to ensure high-quality growth of the GaN HEMT vertical structure epitaxy.

[0031] A preparation method of a pre-dielectric GaN HEMT vertical structure chip disclosed by the present invention includes the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; sequentially grow a GaN drift region, an AlN insertion layer, an AlGaN barrier layer, and a SiN dielectric cap layer on a substrate by metalorganic chemical vapor deposition. X Ga (1-X) N barrier layer and a SiN dielectric cap layer.

[0032] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out of the pure water tank, transfer it to a spin dryer. The spin dryer needs to purge N2 at all times, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water having a water resistance of more than 8. The rotation speed changes are 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0033] 3. Dielectric passivation: First, passivate a layer of 80 - 90 nm of SiN as a SiN barrier layer.

[0034] 4. Alignment preparation: Prepare marks by photolithography and evaporation processes to achieve the purpose of alignment. First, use a 1 μm negative photoresist and coat it evenly on the surface. Expose the pattern using a lithography machine, bake it at 100 °C, and remove the excess photoresist with a positive photoresist developer. Before metal evaporation, bombard the surface of the wafer with an ion source for 2 min. Evaporate the metal using CrTiNi. After evaporation, perform stripping using a stripper. The stripper is first immersed in a deglue tank for 10 min, and finally, high-pressure rinse with pure water is performed, and a rotation of 1000 rpm for 2 min is added during the rinse process.

[0035] 5. Source opening: Make an opening at the top by photolithography and etching processes. Lithograph the window area of the source, and use inductively coupled plasma etching (ICP) to remove the SiN dielectric cap layer in the window area. Use a 3 μm positive photoresist for photolithography, and make a layer of pattern through exposure and development as a mask before etching. Use an ICP etching machine for etching. Use F - -based to etch the dielectric first, and then use Cl - -based to etch GaN.

[0036] Note: The depth after etching should be below the two-dimensional electron gas. The photolithography angle should be 55 - 65°, so that the etched trench can be smooth.

[0037] 6. Source electrode preparation: The source electrode of the device is fabricated by photolithography and evaporation. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi. The source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (Rapid Termal Anneal) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlNiAu is evaporated using a metal evaporator and annealed in a rapid thermal annealing furnace to form an alloy.

[0038] Note: The metal coating should be smooth and continuous. After evaporation, alloying is carried out at a high temperature of 480 - 520 °C. The purpose is to allow the gold-coated metal to penetrate downward into the two-dimensional electron layer to achieve the effect of conductivity.

[0039] 7. Electron isolation: Electron isolation is performed on the top using photolithography and ion implantation to form a chip isolation region, realizing the electrical isolation of the active region. The implanted element is at least one of F, Ar, B, and N. Photolithography uses a positive photoresist with a thickness of 3 μm, and a layer of pattern is developed through exposure as a mask before ion implantation. Boron ions are used for doping in the areas without a photolithography mask during ion implantation to achieve the purpose of electron isolation.

[0040] 8. Dielectric opening: It is required that the dielectric etching only etches the outermost SiN barrier layer, and the in-situ SiN dielectric capping layer grown by epitaxy is retained.

[0041] 9. Gate electrode preparation: The electrode contact area of the gate electrode is lithographed on the top, and the electrode metal Ti / Al / Ti is grown by electron beam evaporation or magnetron sputtering. The gate electrode is formed through a lift-off process. The gate of the device is fabricated by photolithography and evaporation. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator.

[0042] 10. Field plate preparation: First, a passivation layer is grown on the top by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition). The passivation layer is at least one of SiN, SiO2, and Al2O3. After photolithography, the conductive channels of the source electrode and the gate electrode are etched. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0043] 11. Deep etching opening: Deep etching is performed using photolithography and etching. A photoresist with a thickness of 7 - 9 μm is used as a mask. Deep holes are made at specific positions through exposure and development. Then, a Cl etcher is used.- Deep etching is performed on the base pair chip, and the etching depth is 3 - 5 μm.

[0044] 12. Drain preparation: Photolithography is performed at the bottom to pattern the electrode contact area of the drain. Electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of at least one of Ti, Al, Ni, TiN, and AlSi. The drain electrode is formed through a lift-off process, and the drain electrode metal is subjected to rapid thermal annealing treatment in a nitrogen atmosphere to form an ohmic contact in the drain region. Photolithography, etching, and evaporation are used to fabricate the drain of the device. A positive photoresist with a thickness of 1 - 3 μm is used as a mask, and an etcher is used to etch the drain channel at specific positions. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlTi is evaporated on the drain channel using a metal evaporator, and an alloy is formed by RTA annealing.

[0045] Note: The metal coating should be smooth and continuous without breaks. After evaporation, alloying is carried out at a high temperature of 480 - 520 °C. The purpose is to allow the gold-coated metal to penetrate downward into the two-dimensional electron layer to achieve the function of conduction.

[0046] 13. Bonding metal preparation: A passivation layer is grown at the bottom by plasma-enhanced chemical vapor deposition. The passivation layer consists of at least one of SiN, SiO2, and Al2O3, and the drain electrode lead-out area is patterned by photolithography. The gate electrode and source electrode lead-out areas are patterned at the top to obtain the chip. Photolithography and evaporation are used to fabricate the required bonding metal. Photolithography uses a negative photoresist with a thickness of 7 - 9 μm for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator. Before bonding, an infrared laser is used for alignment by a bonder to align the bonding metal with the deep etching holes, and the two chips A and B are bonded together in a vacuum manner.

[0047] See Figure 1Schematic diagram of the epitaxial structure of the GaN HEMT vertical structure disclosed by the present invention; as can be seen from the figure, when preparing the GaN HEMT vertical structure epitaxy disclosed by the present invention, first, high-quality GaN is selected as the substrate material, which provides mechanical support and thermal conductivity for the entire epitaxial structure, and at the same time avoids the epitaxial layer defects introduced during the heteroepitaxial process. The GaN drift region and the GaN channel layer are successively grown epitaxially on the GaN substrate. This region is the key part of the chip to withstand the off-state voltage and has a direct impact on the on-resistance of the chip. Subsequently, a layer of AlN (aluminum nitride) insertion layer is deposited on the GaN channel layer. This AlN insertion layer is used to adjust the height and distribution of the electron barrier and further optimize the chip performance. Immediately afterwards, a barrier layer is grown epitaxially on the AlN insertion layer. This layer and the GaN channel layer form a heterojunction to induce a two-dimensional electron gas with high concentration and high mobility, which is the key to forming an efficient electron transport channel. Finally, a dielectric capping layer is deposited in-situ on the barrier layer. This dielectric capping layer not only plays a protective role to prevent damage to the underlying structure by subsequent processes, but also serves as an etch stop layer to ensure the accuracy of subsequent processes.

[0048] See Figure 2 Schematic diagram of the vertical structure AlGaN / GaN power chip structure disclosed by the present invention; as can be seen from the figure, the AlGaN / GaN heterojunction provides the two-dimensional electron gas participating in the chip operation, serving as the carrier source for the chip to participate in conduction. The chip gate is located between the source electrodes, and the on-off of the current is controlled by applying a voltage. When the gate voltage is lower than the turn-on voltage (also called the threshold voltage) of the chip, the two-dimensional electron gas in the channel layer region under the gate is depleted, and the chip is in the off state. The breakdown voltage of the chip depends on the thickness of the channel layer, the drift region and the substrate. When the gate voltage is higher than the threshold voltage, the two-dimensional electron gas in the channel layer region under the gate is restored and flows vertically through the channel layer, the drift region and the substrate to the drain under the action of the electric field. The dielectric layer in the gate region can effectively reduce gate leakage and lower the operating loss of the chip. The drift region and the substrate are doped with n-type to reduce the bulk resistance, achieving a low on-resistance of the chip. The carrier blocking layers on both sides of the drift region are used to control the current direction to ensure that the current does not flow to other regions of the chip. The entire structure shows a complete path of injecting current from the source electrode, efficiently conducting through the GaN epitaxial layer and the substrate, and finally flowing out through the drain. This vertical structure design optimizes the current path, weakens the influence of the interface states at the passivation layer / barrier layer on the carrier transport, and improves the efficiency and reliability of the chip.

[0049] See Figure 3Flow chart of the preparation method of the pre-dielectric GaN HEMT vertical structure chip disclosed in the present invention; it can be seen from the figure that for the incoming material A processing: first, clean the material A to remove surface impurities, and then perform dielectric passivation to prevent oxidation. Source electrode preparation: After determining the position through positioning preparation, perform source electrode opening and prepare the source electrode material, and at the same time implement the electron isolation technology. Gate and field plate preparation: Perform dielectric opening at specific positions, prepare the gate material, and the field plate for optimizing the electric field distribution. Processing of incoming material B and drain electrode preparation: After cleaning the material B, perform positioning preparation again, perform drain electrode opening, electron isolation, and drain electrode preparation. Bonding completion: Finally, prepare the bonding metal on the AB wafers to complete the overall preparation of the chip. The multi-step fine processing ensures the accuracy and reliability of the chip preparation, improves the yield and performance. The electron isolation technology effectively prevents the electron interference between the source electrode and the drain electrode, and improves the electrical performance. The deep opening technology ensures the accuracy of key positions and enhances the reliability and stability of the chip. The metal bonding step ensures the firm bonding of the AB wafers and improves the overall mechanical strength and electrical performance of the chip.

[0050] Example 1 A preparation method of a pre-dielectric GaN HEMT vertical structure chip, comprising the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; sequentially grow a GaN drift region, an AlN insertion layer, Al X Ga (1-X) GaN barrier layer and a SiN dielectric capping layer on the substrate by metal organic chemical vapor deposition.

[0051] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C in a cleaning machine for 10 min, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the surface residual solution. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out from the pure water tank, transfer it to a spin dryer. The spin dryer needs to blow N2 at all times, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water having a water resistance of more than 8. The rotational speed changes are 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0052] 3. Dielectric passivation: First passivate a layer of 85 nm of SiN as the SiN barrier layer.

[0053] 4. Alignment and Fabrication: Markings are fabricated using photolithography and evaporation processes to achieve alignment. First, a 1μm negative photoresist is evenly coated on the surface. The pattern is exposed using a lithography machine, baked at 100°C, and the excess photoresist is removed using a positive photoresist developer. Before metal evaporation, the surface of the wafer is bombarded with an ion source for 2 minutes. The metal evaporated is CrTiNi. After evaporation, lift-off is performed using a lift-off machine. The lift-off machine is first soaked in a de-glue tank for 10 minutes and finally rinsed with high-pressure pure water. During the rinsing process, rotation at 1000 rpm for 2 minutes is added.

[0054] 5. Source Opening: Openings are made at the top using photolithography and etching processes. The window area of the source is lithographed, and the SiN dielectric capping layer in the window area is removed by inductively coupled plasma etching (ICP). For photolithography, a 3μm positive photoresist is used, and a pattern is made through exposure and development as a mask before etching. For etching, an ICP etching machine is used with F - -based to etch the dielectric first, and then Cl - -based to etch GaN.

[0055] Note: The depth after etching should be below the two-dimensional electron gas. The photolithography angle should be 60° to make the etched trenches smooth.

[0056] 6. Source Fabrication: The source of the device is fabricated using photolithography and evaporation. The electrode contact area of the source is lithographed at the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti; the source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (Rapid Termal Anneal) treatment in a nitrogen atmosphere to form an ohmic contact in the source area. For photolithography, a 2μm negative photoresist is used for lift-off. A pattern is developed through exposure. TiAlNiAu is evaporated using a metal evaporator and annealed into an alloy using a rapid annealing furnace (Rapid Thermal Annealing).

[0057] Note: The metal coating should be smooth and without breaks. After evaporation, alloying is performed at 500°C. The purpose is to let the gold-coated metal penetrate downward into the two-dimensional electron layer to achieve the conductivity effect.

[0058] 7. Electron Isolation: Electron isolation is performed at the top using photolithography and ion implantation to form a chip isolation area and achieve electrical isolation of the active area. The implanted element is F. For photolithography, a 3μm positive photoresist is used, and a pattern is made through exposure and development as a mask before ion implantation. Ion implantation is performed using boron ions to dope areas without a photolithography mask to achieve electron isolation.

[0059] 8. Dielectric Opening: It is required that the dielectric etching only etches the outermost SiN barrier layer and retains the in-situ SiN dielectric capping layer grown epitaxially.

[0060] 9. Gate Fabrication: Photolithograph the electrode contact area of the gate on the top, grow the electrode metal Ti / Al / Ti by electron beam evaporation or magnetron sputtering, and form the gate electrode through the lift-off process. Use photolithography and evaporation to make the gate of the device. Use a 2-μm negative photoresist for lift-off in photolithography. Develop the pattern through exposure. Evaporate TiAlNi using a metal evaporator.

[0061] 10. Field Plate Fabrication: First, grow a passivation layer on the top by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is SiN. After photolithography, etch out the conductive channels of the source and gate. Use a 2-μm negative photoresist for lift-off. Develop the pattern through exposure. Evaporate TiAlNi using a metal evaporator to complete the fabrication of the field plate.

[0062] 11. Deep Etching and Opening: Use photolithography and etching for deep etching. Use an 8-μm photoresist as a mask. Make deep holes at specific positions through exposure and development. Then use an etching machine with Cl - -based gas to perform deep etching on the wafer, and the etching depth is about 4 μm.

[0063] 12. Drain Fabrication: Photolithograph the electrode contact area of the drain on the bottom, grow the electrode metal by electron beam evaporation or magnetron sputtering. The metal is composed of Ti; form the drain electrode through the lift-off process, and perform rapid thermal annealing treatment on the drain electrode metal in a nitrogen atmosphere to form an ohmic contact in the drain area. Use photolithography, etching, and evaporation to make the drain of the device. Use a 2-μm positive photoresist as a mask, and use an etching machine to etch out the drain channel at a specific position. Use a 2-μm negative photoresist for lift-off in photolithography. Develop the pattern through exposure. Evaporate TiAlTi on the drain channel using a metal evaporator and anneal it with RTA to form an alloy.

[0064] Note: The metal overlay should be smooth and unbroken. After evaporation, perform alloying at a high temperature of 500 °C. The purpose is to allow the gold-coated metal to penetrate downward into the two-dimensional electron layer to achieve the function of conduction.

[0065] 13. Bonding Metal Fabrication: Grow a passivation layer on the bottom by plasma enhanced chemical vapor deposition. The passivation layer is composed of SiN, and photolithograph the drain electrode lead-out area. Photolithograph the gate electrode and source electrode lead-out areas on the top to obtain the chip. Use photolithography and evaporation to make the required bonding metal. Use an 8-μm negative photoresist for lift-off in photolithography. Develop the pattern through exposure. Evaporate TiAlNi using a metal evaporator. Use a bonder. Before bonding, align with an infrared laser to align the bonding metal with the deep etching holes, and bond the two wafers A and B in a vacuum manner.

[0066] Among them, the preparation method of the GaN HEMT vertical structure epitaxy includes the following steps: Substrate Preparation: A 300-μm GaN substrate is selected as the growth basis.

[0067] Substrate Treatment: The GaN substrate is pre-treated at a temperature of 1000 °C. Meanwhile, N2 is introduced at a rate of 0.1 L / min, H2 at a rate of 50 L / min, and NH3 at a rate of 1 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0068] Drift Region Growth: In the temperature range of 1000 °C and at a growth pressure of 200 torr, a drift region with a thickness of 0.5 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 200 sccm / min, the flow rate of N2 is 0.1 L / min, the flow rate of H2 is 50 L / min, the flow rate of NH3 is 1 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 0.1 sccm / min. The growth temperature is 1100 °C, and the growth rotation speed is 1200 rpm.

[0069] Ion Implantation: The carrier blocking layer region is defined by photolithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region and thus restricting the current direction. Among them, the implantation depth of N ions is 3 μm.

[0070] Channel Layer Growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1080 °C, the rotation speed is 1200 rpm, and the growth pressure is 200 torr. Meanwhile, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN with a thickness controlled at 300 nm. The flow rate of TMGa is 500 scmm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0071] Insertion layer growth: Subsequently, at a temperature of 800 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 were adjusted. In particular, the N2 flow rate was reduced to almost zero to grow an extremely thin insertion layer with a thickness controlled at 0.1 nm to optimize device performance. Among them, the introduction rate of TMAL was 0.1 sccm / min, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 50 L / min, and the introduction rate of NH3 was 1 L / min.

[0072] Barrier layer growth: Then, within the temperature range of 800 °C, at a rotation speed of 1000 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 15 nm was grown. The Al component X ranged from 20%, and this layer played a key role in controlling current transmission. Among them, the introduction rate of TMGA was 0.1 sccm / min, the introduction rate of TMAL was 50 sccm / min, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 50 L / min, and the introduction rate of NH3 was 1 L / min.

[0073] SIN dielectric capping layer growth: Finally, at a temperature of 700 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3, a SIN dielectric capping layer with a thickness of 0.1 nm was grown to protect and optimize the device surface. Among them, the introduction rate of H2 was 50 L / min, and the introduction rate of NH3 was 1 L / min.

[0074] Finally, a GaN HEMT vertical structure epitaxy was obtained.

[0075] Example 2 A preparation method for a pre-dielectric GaN HEMT vertical structure chip includes the following steps: The difference from Example 1 is: 3. Dielectric passivation: First, passivate a layer of 80 nm of SiN as a SiN barrier layer.

[0076] 5. Source opening: The lithography angle should be 55° to make the etched trench smooth.

[0077] 6. Source preparation: The metal is composed of Ti and Al. Lithography uses a 1-μm negative photoresist for lift-off. After evaporation, alloying is performed at a high temperature of 480 °C.

[0078] 7. Electron isolation: The implanted elements are F and Ar.

[0079] 9. Gate preparation: Lithography uses a 1-μm negative photoresist for lift-off.

[0080] 10. Field plate preparation: The passivation layer is SiN and SiO2. Use 1μm negative photoresist for lift-off.

[0081] 11. Deep etching for opening holes: Use 7μm photoresist as a mask. The etching depth is 3μm.

[0082] 12. Drain preparation: The metal consists of Ti and Al. Use 1μm positive photoresist as a mask. Use 1μm negative photoresist for lift-off during photolithography. After evaporation, alloy at 480°C.

[0083] 13. Bonding metal preparation: The passivation layer consists of SiN and SiO2. Use 7μm negative photoresist for lift-off during photolithography.

[0084] Among them, the preparation method of the GaN HEMT vertical structure epitaxy includes the following steps: Substrate preparation: Select a 1000μm GaN substrate as the growth basis.

[0085] Substrate treatment: Pretreat the GaN substrate at a temperature of 1150°C. At the same time, introduce N2 at a speed of 100 L / min, H2 at a speed of 200 L / min, and NH3 at a speed of 100 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0086] Drift region growth: In the temperature range of 1150°C and at a growth pressure of 200 torr, grow a drift region with a thickness of 50μm by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 1000 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, the flow rate of NH3 is 100 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 500 sccm / min. The growth temperature is 1000°C, and the growth rotation speed is 800 rpm.

[0087] Ion implantation: Define the carrier blocking layer region on the epitaxial drift region grown in the previous step through photolithography, and perform ion implantation on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1μm.

[0088] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1000 °C, the rotation speed is 800 rpm, the growth pressure is 200 torr. At the same time, TMGa is introduced to grow undoped GaN, and its thickness is controlled at 150 nm. The introduction speed of TMGa is 200 scmm / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0089] Insertion layer growth: Subsequently, at a temperature of 1100 °C and a growth pressure of 75 torr, the flow rates of gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 1 nm to optimize device performance. Among them, the introduction speed of TMAL is 500 sccm / min, the introduction speed of N2 is 100 L / min, the introduction speed of H2 is 200 L / min, and the introduction speed of NH3 is 100 L / min.

[0090] Barrier layer growth: Then, within the temperature range of 1100 °C, at a rotation speed of 1100 rpm and a growth pressure of 100 torr, by adjusting the flow rates of gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 35 nm is grown. The Al component X ranges from 15%. This layer plays a key role in controlling current transmission. Among them, the introduction speed of TMGA is 500 sccm / min, the introduction speed of TMAL is 500 sccm / min, the introduction speed of N2 is 100 L / min, the introduction speed of H2 is 200 L / min, and the introduction speed of NH3 is 100 L / min.

[0091] SIN dielectric cap layer growth: Finally, at a temperature of 1100 °C and a growth pressure of 200 torr, by adjusting the flow rates of gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric cap layer with a thickness of 100 nm is grown to protect and optimize the device surface. Among them, the introduction speed of N2 is 100 L / min, the introduction speed of H2 is 200 L / min, the introduction speed of NH3 is 100 L / min, and the concentration of the second SIH4 is 2%, and the introduction speed is 500 sccm / min.

[0092] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0093] Example 3 A preparation method for a pre-dielectric GaN HEMT vertical structure chip includes the following steps: Differing from Example 1: 3. Dielectric passivation: First, passivate a layer of 88 nm SiN as the SiN barrier layer.

[0094] 5. Source opening: The lithography angle should be 65° to make the etched trench smooth.

[0095] 6. Source preparation: The metal consists of Ni and TiN. Use a 3 μm negative photoresist for lift-off in lithography. After evaporation, alloy at a high temperature of 490 °C.

[0096] 7. Electron isolation: The implanted element is B.

[0097] 9. Gate preparation: Use a 3 μm negative photoresist for lift-off in lithography.

[0098] 10. Field plate preparation: The passivation layer is SiO2. Use a 3 μm negative photoresist for lift-off.

[0099] 11. Deep etching opening: Use a 9 μm photoresist as a mask. The etching depth is 3 μm.

[0100] 12. Drain preparation: The metal consists of Ni and TiN. Use a 3 μm positive photoresist as a mask. Use a 3 μm negative photoresist for lift-off in lithography. After evaporation, alloy at a high temperature of 490 °C.

[0101] 13. Bonding metal preparation: The passivation layer consists of SiO2. Use a 9 μm negative photoresist for lift-off in lithography.

[0102] Among them, the preparation method of the vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: Select a 750 μm GaN substrate as the growth basis.

[0103] Substrate treatment: Pretreat the GaN substrate at a temperature of 1030 °C. At the same time, introduce N2 at a rate of 30 L / min, H2 at a rate of 130 L / min, and NH3 at a rate of 80 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0104] Drift region growth: In the temperature range of 1080 °C, under a growth pressure of 200 torr, a drift region with a thickness of 30 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the feeding rate of TMGA is 300 sccm / min, the feeding rate of N2 is 30 L / min, the feeding rate of H2 is 120 L / min, the feeding rate of NH3 is 60 L / min, the concentration of the first SIH4 is 200 ppm, and the feeding rate is 300 sccm / min. The growth temperature is 1050 °C, and the growth rotation speed is 900 rpm.

[0105] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving a high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 5 μm.

[0106] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1100 °C, the rotation speed is 1000 rpm, the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN, and its thickness is controlled within 200 nm. Among them, the feeding rate of TMGa is 600 scmm / min, the feeding rate of N2 is 80 L / min, the feeding rate of H2 is 100 L / min, and the feeding rate of NH3 is 80 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0107] Insertion layer growth: Subsequently, at a temperature of 850 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, and an extremely thin insertion layer with a thickness controlled within 2 nm is grown to optimize device performance. Among them, the feeding rate of TMAL is 150 sccm / min, the feeding rate of N2 is 80 L / min, the feeding rate of H2 is 80 L / min, and the feeding rate of NH3 is 60 L / min.

[0108] Barrier layer growth: Then, in the temperature range of 950 °C, at 1200 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X)N-barrier layer, where the Al composition X ranges from 25%, and this layer plays a key role in controlling current transport. Among them, the flow rate of TMGA is 300 sccm / min, the flow rate of TMAL is 100 sccm / min, the flow rate of N2 is 40 L / min, the flow rate of H2 is 140 L / min, and the flow rate of NH3 is 80 L / min.

[0109] Growth of SIN dielectric capping layer: Finally, at a temperature of 850 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SIH4 gas, a SIN dielectric capping layer with a thickness of 70 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 90 L / min, the flow rate of H2 is 150 L / min, the flow rate of NH3 is 90 L / min, the concentration of the second SIH4 is 2%, and the flow rate is 300 sccm / min.

[0110] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0111] Example 4 A method for preparing a vertical structure chip of a pre-dielectric GaN HEMT, comprising the following steps: Differing from Example 1: 3. Dielectric passivation: First, passivate a 90-nm SiN as a SiN barrier layer.

[0112] 5. Source opening: The lithography angle should be 65° to make the etched trench smooth.

[0113] 6. Source preparation: The metal is composed of AlSi. After evaporation, alloying is carried out at a high temperature of 520 °C.

[0114] 7. Electron isolation: The injected element is N.

[0115] 10. Field plate preparation: The passivation layer is Al2O3.

[0116] 12. Drain preparation: The metal is composed of AlSi. After evaporation, alloying is carried out at a high temperature of 520 °C.

[0117] 13. Bonding metal preparation: The passivation layer is composed of Al2O3.

[0118] Among them, the preparation method of the vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: Select a 600-μm GaN substrate as the growth basis.

[0119] Substrate treatment: The GaN substrate is pre-treated at a temperature of 1100 °C. Meanwhile, H2 is introduced at a rate of 120 L / min and NH3 is introduced at a rate of 50 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0120] Drift region growth: In the temperature range of 1100 °C and under a growth pressure of 200 torr, a drift region with a thickness of 7 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 600 sccm / min, the flow rate of N2 is 10 L / min, the flow rate of H2 is 90 L / min, the flow rate of NH3 is 45 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 5 sccm / min. The growth temperature is 1150 °C and the growth rotation speed is 1150 rpm.

[0121] Ion implantation: The carrier blocking layer region is defined by photolithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving a high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 20 μm.

[0122] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1150 °C, the rotation speed is 1150 rpm, and the growth pressure is 200 torr. Meanwhile, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled at 400 nm. Among them, the flow rate of TMGa is 1000 scmm / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0123] Insertion layer growth: Subsequently, at a temperature of 1000 °C and under a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 0.8 nm to optimize device performance. Among them, the flow rate of TMAL is 200 sccm / min, the flow rate of N2 is 0.1 L / min, the flow rate of H2 is 190 L / min, and the flow rate of NH3 is 5 L / min.

[0124] Barrier layer growth: Next, within the temperature range of 1020 °C, at a growth pressure of 800 rpm and 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, an Al barrier layer with a thickness of 22 nm is grown. X Ga (1-X) N barrier layer, where the Al component X ranges from 50%, and this layer plays a key role in controlling current transmission. Among them, the introduction rate of TMGA is 80 sccm / min, the introduction rate of TMAL is 300 sccm / min, the introduction rate of N2 is 64 L / min, the introduction rate of H2 is 120 L / min, and the introduction rate of NH3 is 50 L / min.

[0125] SIN dielectric capping layer growth: Finally, at a temperature of 1000 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing the second SiH4 gas, a SIN dielectric capping layer with a thickness of 2 nm is grown to protect and optimize the device surface. Among them, the introduction rate of N2 is 64 L / min, the introduction rate of H2 is 120 L / min, the introduction rate of NH3 is 50 L / min, the concentration of the second SiH4 is 2%, and the introduction rate is 40 sccm / min.

[0126] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0127] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a dielectric GaN HEMT vertical structure chip, characterized in that: The following steps are involved: 1) After cleaning and drying the GaN HEMT vertical structure epitaxial wafer, first passivate a layer of 80-90 nm SiN as a SiN barrier layer, and then make positioning marks; 2) Photolithography a source window area on the top, and remove the SiN barrier layer and SiN dielectric cap layer in the window area by etching; 3) Photolithography the source electrode contact area on the top, and evaporate the electrode metal. After stripping, the source electrode is formed; 4) Form a chip isolation area on the top through photolithography and ion implantation; 5) Etch the SiN barrier layer on the surface and retain the SiN dielectric cap layer; 6) Photolithography the gate electrode contact area on the top, and evaporate the electrode metal to form the gate electrode; 7) Grow a passivation layer on the top, etch out the conductive channels of the source and gate, and obtain the field plate after evaporation; 8) Deeply etch and open holes in GaN HEMT vertical structure epitaxial wafers; 9) Photolithography the drain electrode contact area at the bottom, and evaporate the electrode metal. After stripping, the drain electrode is formed; 10) A passivation layer is grown at the bottom, and the drain electrode lead-out region is photolithographically formed; the gate electrode and source electrode lead-out regions are photolithographically formed at the top to obtain a first dielectric GaN HEMT vertical structure chip.

2. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the method for preparing the GaN HEMT vertical structure epitaxial wafer comprises: sequentially growing a GaN drift region, an AlN insertion layer, and an Al X Ga (1-X) N barrier layer and SiN dielectric cap layer to obtain GaN HEMT vertical structure epitaxial wafer; the Al X Ga (1-X) In the N barrier layer, 0.15≤X≤0.

5.

3. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 2, characterized in that: The substrate pretreatment conditions include: pretreating the substrate at 1000-1150° C., while introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min; The conditions for the growth of the GaN drift region include: growing a GaN drift region with a thickness of 0.5-50 μm at 1000-1150° C. and a growth pressure of 200 torr by controlling the flow rates of trimethylgallium, N2, H2, NH3 and the first monosilane, the growth temperature is 1000-1150° C., and the growth speed is 800-1200 rpm; wherein the introduction rate of trimethylgallium is 200-1000 sccm / min, the introduction rate of N2 is 0-100 L / min, the introduction rate of H2 is 50-200 L / min, the introduction rate of NH3 is 1-100 L / min, the concentration of the first monosilane is 200 ppm, and the introduction rate is 0-500 sccm / min; A carrier blocking layer region is defined on a GaN drift region by photolithography, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000-1150°C, the rotation speed is 800-1200rpm, the growth pressure is 200torr, and trimethylgallium, N2, H2 and NH3 are introduced simultaneously to grow undoped GaN, and the thickness of GaN is 150-400nm, wherein the introduction rate of trimethylgallium is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 0-200L / min, and the introduction rate of NH3 is 0-100L / min.

4. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 2, characterized in that: The growth conditions of the AlN insertion layer include: at 800-1100°C and a growth pressure of 75torr, trimethylaluminum, H2 and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer, and the thickness of the AlN insertion layer is 0-2nm; wherein the introduction rate of trimethylaluminum is 0-500sccm / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

5. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 2, characterized in that: Al X Ga (1-X) The growth conditions of the N barrier layer include: growing an Al layer with a thickness of 15-35 nm by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2 and NH3 at 800-1100°C, 800-1200rpm, and a growth pressure of 100 torr. X Ga (1-X) N barrier layer; wherein the molar percentage of X is 15%-50%, the introduction rate of trimethylgallium is 0-500sccm / min, the introduction rate of trimethylaluminum is 50-500sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

6. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 2, characterized in that: The conditions for the growth of the SiN dielectric cap layer include: at 700-1100° C. and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2 and NH3 and introducing a second monosilane, a SiN dielectric cap layer with a thickness of 0.1-100 nm is grown; wherein the N2 introduction rate is 0-100 L / min, the H2 introduction rate is 50-200 L / min, the NH3 introduction rate is 1-100 L / min, the concentration of the second monosilane is 2%, and the second monosilane introduction rate is 0-500 sccm / min.

7. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 2), the window region of the source electrode has a depth below the two-dimensional electron gas, and the photolithography angle is 60°; the SiN dielectric cap layer in the window region is removed by inductively coupled plasma etching; In step 3), before evaporation, the substrate is immersed in a strong oxidizing solution tank and then immersed in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 4), the ion implanted element includes: at least one of F, Ar, B and N; the depth of the ion implantation is 0.1-20 μm.

8. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 6), the gate electrode is a Ti / Al / Ti electrode metal; In step 7), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

9. The method for preparing a dielectric GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 9), the depth of the electrode contact region of the drain is below the two-dimensional electron gas, and the photolithography angle is 60°; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 10), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

10. A GaN HEMT vertical structure chip, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the GaN HEMT vertical structure epitaxial wafer, wherein the top SiN dielectric cap layer is partially etched in the source window region to expose the surface of the GaN HEMT vertical structure epitaxial wafer; SiN barrier layer, located above the SiN dielectric cap layer, with a thickness of 80-90 nm; A source electrode, forming an ohmic contact with the GaN HEMT vertical structure epitaxial wafer through a source window region; The chip isolation area is located on the top of the GaN HEMT vertical structure epitaxial wafer and is formed by photolithography and ion implantation; A gate electrode is disposed above the unetched SiN dielectric cap layer and forms a Schottky contact with the SiN dielectric cap layer; The top passivation layer covers the gate and source, has a conductive channel etched inside, and forms a field plate structure connected to the electrode by evaporation; the top passivation layer also has electrode lead-out areas for the gate and source etched for external electrical connection; The drain electrode is located at the bottom of the GaN HEMT vertical structure epitaxial wafer and is connected to the drain region of the GaN HEMT vertical structure epitaxial wafer through a deep etched through hole; The bottom passivation layer covers the drain electrode and is etched with a drain lead-out window.

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