Low-temperature ohmic GaN HEMT vertical structure chip and preparation method thereof

Abstract

The invention discloses a low-temperature ohmic GaN HEMT (High Electron Mobility Transistor) vertical structure chip and a preparation method thereof, and belongs to the technical field of low-temperature ohmic contact preparation. Firstly, a multi-layer epitaxial structure GaN drift region, an AlN insertion layer, an AlGaN barrier layer and a SiN dielectric cap layer are grown on a pretreatment substrate; and then an isolation region and an electrode contact window are formed through cleaning, marking, photoetching, ion implantation and etching processes. Next, a source electrode and a gate electrode are formed by metal vapor deposition, and a passivation layer is grown to protect the device. And then, deep etching trepanning is carried out, a drain electrode is formed at the bottom, finally, an electrode lead-out area is completed through photoetching and evaporation processes, and finally, the low-temperature ohmic GaN HEMT vertical structure chip is obtained. Ideal ohmic contact between metal and a semiconductor is achieved under the low-temperature condition, contact resistance is reduced, and the finally obtained chip has optimized electrode contact and isolation areas, is suitable for high-frequency and high-power application and shows excellent electrical performance and thermal stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of low-temperature ohmic contact preparation, and particularly relates to a low-temperature ohmic GaN HEMT vertical structure chip and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, especially its wide application in the fields of power electronics and microwave communication, higher requirements are put forward for high-performance and high-efficiency semiconductor devices. Gallium nitride (GaN), as a wide-bandgap semiconductor material, has become an ideal choice for fabricating high-efficiency and high-power-density semiconductor devices due to its high electron mobility, high breakdown electric field, and good thermal stability. GaN high electron mobility transistor (HEMT), as a representative of GaN-based devices, its vertical structure chip shows great potential in the fields of power conversion and microwave communication.

[0003] In the research of GaN HEMT devices, ohmic contact is the key to achieving low-resistance and high-efficiency current transmission. As an important method among them, low-temperature ohmic contact technology forms a good contact between metal and semiconductor at a relatively low temperature, avoiding the negative impact of high-temperature processes on device performance. At present, certain progress has been made in the research of low-temperature ohmic GaN HEMT vertical structure chips, including optimizing the metallization layer material, improving the deposition process, and exploring low-temperature annealing conditions, etc.

[0004] Although certain achievements have been made in the research of low-temperature ohmic GaN HEMT vertical structure chips, there are still some problems. The reaction activity between metal and semiconductor is relatively low under low-temperature conditions, making it difficult to achieve an ideal ohmic contact effect, resulting in a relatively high contact resistance. In addition, low-temperature ohmic contact technology has high requirements for material selection and process conditions, and precise control of each process step is required to ensure the performance and stability of the device. Summary of the Invention

[0005] In order to overcome the above-mentioned drawbacks of the prior art, the purpose of the present invention is to provide a low-temperature ohmic GaN HEMT vertical structure chip and a preparation method thereof, so as to solve the technical problem of how to achieve an ideal ohmic contact between metal and semiconductor under low-temperature conditions to reduce the contact resistance.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a preparation method of a low-temperature ohmic GaN HEMT vertical structure chip, including the following steps: 1) Grow a GaN drift region, an AlN insertion layer, and Al X Ga (1-X)N barrier layer and SiN dielectric cap layer to obtain a GaN HEMT vertical structure epitaxial wafer; among them, Al X Ga (1-X) In the N barrier layer, 0.15 ≤ X ≤ 0.5; 2) Clean the GaN HEMT vertical structure epitaxial wafer, and after drying, perform positioning marking; 3) Form a chip isolation region on the top by photolithography and ion implantation; 4) Photolithograph the window region of the source electrode on the top, and etch away the SiN dielectric cap layer in the window region; 5) Photolithograph the electrode contact region of the source electrode on the top, and evaporate electrode metal, and after stripping, form the source electrode; 6) Photolithograph the electrode contact region of the gate electrode on the top, and evaporate electrode metal to form the gate electrode; 7) Grow a passivation layer on the top, etch out the conductive channels of the source and the gate, and after evaporation, obtain the field plate; 8) Perform deep etching and opening on the GaN HEMT vertical structure epitaxial wafer; 9) Photolithograph the electrode contact region of the drain electrode on the bottom, and evaporate electrode metal, and after stripping, form the drain electrode; 10) Grow a passivation layer on the bottom, and photolithograph the drain electrode lead-out region; 11) Photolithograph the gate electrode and the source electrode lead-out region on the top to obtain a low-temperature ohmic GaN HEMT vertical structure chip.

[0007] Preferably, in step 3), the elements for ion implantation include at least one of F, Ar, B, and N; the depth of ion implantation is 0.1 - 20 μm; In step 4), the depth of the window region of the source electrode is below the two-dimensional electron gas, and the angle of photolithography is 60°; inductively coupled plasma etching is used to remove the SiN dielectric cap layer in the window region; In step 5), after soaking in a strong oxidation solution tank before evaporation, then soak in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi.

[0008] Preferably, in step 6), the gate electrode is a Ti / Al / Ti electrode metal; In step 7), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3; In step 9), the depth of the electrode contact region of the drain electrode is below the two-dimensional electron gas, and the angle of photolithography is 60°; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi; In step 10), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0009] Preferably, in step 1), the pretreatment conditions of the substrate include: pretreating the substrate at 1000 - 1150 °C, and simultaneously introducing N2 at a rate of 0 - 100 L / min, H2 at a rate of 50 - 200 L / min, and NH3 at a rate of 1 - 100 L / min.

[0010] Preferably, in step 1), the growth conditions of the GaN drift region include: growing a GaN drift region with a thickness of 0.5 - 50 μm at a growth pressure of 200 torr and a growth temperature of 1000 - 1150 °C by controlling the flow rates of trimethylgallium, N2, H2, NH3, and monosilane; the growth rotation speed is 800 - 1200 rpm; wherein, the introduction rate of trimethylgallium is 200 - 1000 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 50 - 200 L / min, the introduction rate of NH3 is 1 - 100 L / min, and the concentration of monosilane is 200 ppm, and the introduction rate is 0 - 500 sccm / min.

[0011] Preferably, in step 1), the carrier blocking layer region is defined on the GaN drift region by photolithography, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000 - 1150 °C, the rotation speed is 800 - 1200 rpm, the growth pressure is 200 torr, and trimethylgallium, N2, H2, and NH3 are introduced simultaneously to grow undoped GaN, and the thickness of the GaN is 150 - 400 nm, wherein the introduction rate of trimethylgallium is 200 - 1000 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 0 - 200 L / min, and the introduction rate of NH3 is 0 - 100 L / min.

[0012] Preferably, in step 1), the growth conditions of the AlN insertion layer include: growing an extremely thin AlN insertion layer with a thickness of 0 - 2 nm at a growth pressure of 75 torr and a growth temperature of 800 - 1100 °C by simultaneously introducing trimethylaluminum, H2, and NH3; wherein, the introduction rate of trimethylaluminum is 0 - 500 sccm / min, the introduction rate of H2 is 50 - 200 L / min, and the introduction rate of NH3 is 1 - 100 L / min.

[0013] Preferably, in step 1), Al X Ga (1-X)The growth conditions of the N barrier layer include: growing an AlGaN barrier layer with a thickness of 15 - 35 nm at a growth temperature of 800 - 1100 °C, a rotation speed of 800 - 1200 rpm, and a growth pressure of 100 torr by adjusting the flow rates of trimethylgallium, trimethylaluminum, N₂, H₂, and NH₃; where the molar percentage of X is 15% - 50%, the flow rate of trimethylgallium is 0 - 500 sccm / min, the flow rate of trimethylaluminum is 50 - 500 sccm / min, the flow rate of N₂ is 0 - 100 L / min, the flow rate of H₂ is 50 - 200 L / min, and the flow rate of NH₃ is 1 - 100 L / min. X Ga (1-X) barrier layer; among them, the molar percentage of X is 15% - 50%, the flow rate of trimethylgallium is 0 - 500 sccm / min, the flow rate of trimethylaluminum is 50 - 500 sccm / min, the flow rate of N₂ is 0 - 100 L / min, the flow rate of H₂ is 50 - 200 L / min, and the flow rate of NH₃ is 1 - 100 L / min.

[0014] Preferably, in step 1), the growth conditions of the SiN dielectric capping layer include: growing a SiN dielectric capping layer with a thickness of 0.1 - 100 nm at a growth temperature of 700 - 1100 °C and a growth pressure of 200 torr by adjusting the flow rates of N₂, H₂, and NH₃ and introducing disilane; where the flow rate of N₂ is 0 - 100 L / min, the flow rate of H₂ is 50 - 200 L / min, the flow rate of NH₃ is 1 - 100 L / min, the concentration of disilane is 2%, and the flow rate of disilane is 0 - 500 sccm / min.

[0015] The present invention also discloses a low - temperature ohmic GaN HEMT vertical - structure chip, prepared by the above - mentioned preparation method, which includes a stack structure composed of a substrate, a GaN drift region, an AlN insertion layer, an AlGaN barrier layer, and a SiN dielectric capping layer from bottom to top; in the AlGaN barrier layer, 0.15 ≤ X ≤ 0.5; X Ga (1-X) barrier layer; an ohmic contact is formed between the source electrode penetrating the SiN dielectric capping layer and the AlGaN barrier layer; X Ga (1-X) where 0.15 ≤ X ≤ 0.5 in the AlGaN barrier layer; a source electrode penetrating the SiN dielectric capping layer, and an ohmic contact is formed between the source electrode and the AlGaN barrier layer; X Ga (1-X) barrier layer; a gate electrode disposed on the SiN dielectric capping layer, and a Schottky contact is formed between the gate electrode and the AlGaN barrier layer; X Ga (1-X) barrier layer; a top passivation layer covering the source electrode and the gate electrode, and a metal field plate is provided in the top passivation layer. One end of the metal field plate is connected to the gate electrode, and the other end extends horizontally towards the source electrode; a conductive hole penetrating the GaN drift region, the AlN insertion layer, and the AlGaN barrier layer, and the conductive hole is filled with metal and is in direct contact with the source electrode and the back surface of the substrate; X Ga (1-X) barrier layer; A drain electrode disposed on the back surface of the substrate, and a bottom passivation layer covering the drain electrode, wherein the bottom passivation layer is provided with a through lead-out window to expose the drain electrode; A chip isolation region surrounding the sidewall of the stacked structure, and the isolation region is formed by ion implantation and penetrates through Al X Ga (1-X) N barrier layer, AlN insertion layer and GaN drift region.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a preparation method of a low-temperature ohmic GaN HEMT vertical structure chip. Through a carefully designed layer structure and growth conditions, it provides a good foundation for subsequent ohmic contacts. The introduction of the AlN insertion layer and Al X Ga (1-X) N barrier layer helps to modulate the properties of the two-dimensional electron gas (2DEG), while the SiN dielectric capping layer can protect the underlying structure and provide a flat surface for subsequent process steps. The cleaning and drying steps ensure the cleanliness of the epitaxial wafer surface, and the alignment marks provide accurate reference points for subsequent lithography and electrode fabrication. Forming the isolation region by ion implantation can effectively prevent electrical interference between different chip regions, improving the integration and performance of the chip. After removing the SiN dielectric capping layer, the underlying semiconductor material can be exposed, providing a contact surface for subsequent source electrode fabrication, which helps to achieve a low-resistance ohmic contact. By selecting appropriate electrode metals and evaporation conditions, good ohmic contact with the semiconductor material can be achieved at low temperature, reducing the contact resistance. The fabrication of the gate electrode is also crucial, and good ohmic contact can ensure the effective regulation of the 2DEG by the gate. The passivation layer can protect the chip from the external environment, and at the same time, the introduction of the field plate helps to improve the electric field distribution and increase the breakdown voltage of the chip. The deep etching opening provides a channel for subsequent drain electrode fabrication, and also helps to optimize the structure and performance of the chip. By selecting appropriate electrode metals and evaporation conditions, good ohmic contact between the drain and the semiconductor material can be achieved at low temperature, further reducing the contact resistance. The bottom passivation layer also provides protection, and the design of the drain electrode lead-out region facilitates subsequent packaging and testing. The final lithography step completes all the electrode lead-out regions of the chip, enabling the chip to be easily packaged and tested. The entire preparation process achieves an ideal ohmic contact between the metal and the semiconductor at low temperature, reducing the contact resistance.

[0017] The present invention also discloses a low-temperature ohmic GaN HEMT vertical structure chip prepared by the above preparation method. Through specific preparation methods and material selections, the present invention achieves an ideal ohmic contact between metal and semiconductor under low-temperature conditions, significantly reducing the contact resistance. This excellent ohmic contact performance helps improve the overall electrical performance of the GaN HEMT vertical structure chip, reduce energy loss, and improve the efficiency of the device. In response to the application requirements of GaN HEMT devices under low-temperature conditions, the present invention optimizes the preparation process and material selection, enabling the chip to maintain stable performance in a low-temperature environment. This is of great significance for electronic devices that need to operate under extreme temperature conditions in fields such as aerospace and deep space exploration. A good ohmic contact can reduce the thermal stress during device operation, lower the sensitivity of the contact resistance to temperature changes, thereby improving the reliability and lifespan of the device. This is crucial for high-power electronic devices that require long-term stable operation. By introducing a passivation layer and optimizing the layer structure design, the present invention enhances the thermal stability and heat dissipation performance of the chip. This helps reduce the temperature of the device during operation, improve the reliability and lifespan of the device, and also helps improve the power density and efficiency of the device. With the continuous development and maturity of GaN technology, the application prospects of vertical structure GaN HEMT devices in fields such as power electronics, wireless communication, and new energy vehicles will become increasingly broad. The research results of the present invention not only provide new ideas and methods for the preparation of GaN HEMT vertical structure chips, but also provide a new direction for the research and development of GaN semiconductor materials. By continuously optimizing the preparation process and material selection, the performance and reliability of GaN devices can be further improved, promoting the application of GaN technology in a wider range of fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; Figure 2 FIG. is a schematic structural diagram of the GaN HEMT vertical structure power chip disclosed by the present invention; Figure 3 FIG. is a schematic structural diagram of the vertical structure AlGaN / GaN power device disclosed by the present invention; Figure 4 FIG. is a flowchart of the preparation method of the low-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0021] The present invention will be further described in detail below in conjunction with the accompanying drawings: A preparation method for the vertical structure epitaxy of GaN HEMT disclosed by the present invention includes the following steps: GaN substrate preparation: Select an n-type doped GaN substrate with a thickness of 300 - 1000 μm as the growth basis. Selecting a GaN substrate with an appropriate thickness can ensure the uniformity and stability of the epitaxial layer. A thicker substrate usually has better thermal stability and mechanical strength, which is beneficial to the subsequent epitaxial growth process.

[0022] GaN substrate treatment: Pretreat the GaN substrate at a temperature of 1000 - 1150 °C (preferably 1100 °C). At the same time, introduce nitrogen (N2) at a rate of 0 - 100 L / min (preferably 0 L / min), hydrogen (H2) at a rate of 50 - 200 L / min (preferably 120 L / min), and ammonia (NH3) at a rate of 1 - 100 L / min (preferably 50 L / min) to prepare for the subsequent epitaxial growth. High-temperature pretreatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for the subsequent epitaxial growth.

[0023] GaN Drift Region Growth: In the temperature range of 1000 - 1150 °C (preferably 1100 °C), under a growth pressure of 200 torr, by precisely controlling the flow rates of trimethylgallium (TMGA), N2, H2, NH3, and the first silane (SiH4), a GaN drift region with a thickness of 0.5 - 50 μm (preferably 7 μm) is grown. This layer is crucial for the chip performance. Among them, the feeding rate of TMGA is 200 - 1000 sccm / min (preferably 600 sccm / min), the feeding rate of N2 is 0 - 100 L / min (preferably 10 L / min), the feeding rate of H2 is 50 - 200 L / min (preferably 90 L / min), the feeding rate of NH3 is 1 - 100 L / min (preferably 45 L / min), the concentration of the first SIH4 is 200 ppm, and the feeding rate is 0 - 500 sccm / min (preferably 10 sccm / min). The growth temperature is 1000 - 1150 °C (preferably 1100 °C), and the growth rotation speed is 800 - 1200 rpm (preferably 1200 rpm). The drift region is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the chip performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the chip.

[0024] Ion Implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1 - 20 μm (preferably 3 μm).

[0025] Channel Layer Growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1000 - 1150 °C (preferably 1080 °C), the rotation speed is 800 - 1200 rpm (preferably 1200 rpm), the growth pressure is 200 torr, and at the same time, TMGa, N2, H2, and NH3 are fed to grow undoped GaN, and its thickness is controlled within 150 - 400 nm (preferably 300 nm). Among them, the feeding rate of TMGa is 200 - 1000 sccm / min (preferably 500 scmm / min), the feeding rate of N2 is 0 - 100 L / min (preferably 64 L / min), the feeding rate of H2 is 0 - 200 L / min (preferably 120 L / min), the feeding rate of NH3 is 0 - 100 L / min (preferably 50 L / min). The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0026] Growth of AlN insertion layer: Subsequently, at a temperature of 800 - 1100 °C (preferably 1000 °C) and a growth pressure of 75 torr, trimethylaluminum (TMAL), H2, and NH3 are simultaneously introduced to grow an extremely thin AlN insertion layer with a thickness controlled within 0 - 2 nm (preferably 0.8 nm) to optimize the chip performance. Among them, the introduction rate of TMAL is 0 - 500 sccm / min (preferably 200 sccm / min), the introduction rate of H2 is 50 - 200 L / min (preferably 190 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 5 L / min). The introduction of the insertion layer can optimize the interface characteristics of the chip, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the chip. By precisely controlling the thickness and growth conditions of the insertion layer, the chip performance can be further optimized.

[0027] Al X Ga (1-X) Growth of AlGaN barrier layer: Next, within a temperature range of 800 - 1100 °C (preferably 1020 °C), at 800 - 1200 rpm (preferably 1000 rpm), and a growth pressure of 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, an AlGaN barrier layer with a thickness of 15 - 35 nm (preferably 22 nm) is grown. X Ga (1-X) The AlGaN barrier layer, where the Al component X ranges from 15% - 50% (preferably 20 - 25%), plays a key role in controlling the current magnitude and reliability. Among them, the introduction rate of TMGA is 0 - 500 sccm / min (preferably 80 sccm / min), the introduction rate of TMAL is 50 - 500 sccm / min (preferably 300 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 64 L / min), the introduction rate of H2 is 50 - 200 L / min (preferably 120 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 50 L / min). The barrier layer is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the current transmission characteristics of the chip. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the chip.

[0028] SiN dielectric capping layer growth: Finally, at a temperature of 700 - 1100 °C (preferably 1000 °C) and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric capping layer with a thickness of 0.1 - 100 nm (preferably 2 nm) is grown to protect and optimize the chip surface. Among them, the flow rate of N2 is 0 - 100 L / min (preferably 64 L / min), the flow rate of H2 is 50 - 200 L / min (preferably 120 L / min), the flow rate of NH3 is 1 - 100 L / min (preferably 50 L / min), the concentration of the second SiH4 is 2%, and the flow rate is 0 - 500 sccm / min (preferably 40 sccm / min). The above gases are introduced simultaneously. The introduction of the SiN dielectric capping layer can protect the chip surface from the influence of the external environment and improve the stability and reliability of the chip. At the same time, by precisely controlling the growth parameters of the capping layer and introducing an appropriate amount of the second SiH4, the electrical characteristics of the chip surface can be further optimized.

[0029] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0030] During the entire preparation process, the growth of each layer needs to be carried out under strictly controlled temperature, gas flow rate, and doping conditions to ensure the high-quality growth of the vertical structure epitaxy of GaN HEMT.

[0031] A method for preparing a low-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention includes the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; on the substrate, a GaN drift region, an AlN insertion layer, an Al X Ga (1-X) GaN barrier layer, and a SiN dielectric capping layer are sequentially grown by metal-organic chemical vapor deposition.

[0032] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out from the pure water tank, transfer it to a spin dryer. The spin dryer needs to blow N2 all the time, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water having a water resistance of more than 8. The rotation speed changes as 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0033] 3. Alignment and Fabrication: Markings are fabricated using photolithography and evaporation processes to achieve alignment. First, a 1μm negative photoresist is evenly coated on the surface. The pattern is exposed using a lithography machine, baked at 100°C, and the excess photoresist is removed using a positive photoresist developer. Before metal evaporation, the surface of the GaN HEMT vertical structure epitaxial wafer is bombarded with an ion source for 2 minutes. CrTiNi is used for metal evaporation. After evaporation, lift-off is performed using a lift-off machine. The lift-off machine is first soaked in a degumming bath for 10 minutes and finally rinsed with high-pressure pure water. A 2-minute rotation at 1000 rpm is added during the rinsing process.

[0034] 4. Electron Isolation: Electron isolation is performed at the top using photolithography and ion implantation to form a chip isolation region and achieve electrical isolation of the active region. The implanted elements are at least one of F, Ar, B, and N. Photolithography uses a 3μm positive photoresist to create a pattern through exposure and development, serving as a mask before ion implantation. Boron ions are used for ion implantation to dope areas without a photolithography mask to achieve electron isolation.

[0035] 5. Source Opening: Openings are made at the top using photolithography and etching processes. The window area of the source is lithographed, and the SiN dielectric capping layer in the window area is removed using inductively coupled plasma etching (ICP). Photolithography uses a 3μm positive photoresist to create a pattern through exposure and development, serving as a mask before etching. Etching is performed using an ICP etcher. First, the dielectric is etched using F - radicals, and then GaN is etched using Cl - radicals.

[0036] Note: Alloy issues need to be considered for the openings here, in an environment of around 480 - 520°C. Therefore, the depth after etching should be below the two-dimensional electron gas. The photolithography angle should be 55 - 65° to make the etched trenches smooth.

[0037] 6. Source Fabrication: The source of the device is fabricated using photolithography and evaporation. The electrode contact area of the source is lithographed at the top, and electrode metal is grown using electron beam evaporation or magnetron sputtering. The metal consists of at least one of Ti, Al, Ni, TiN, and AlSi; the source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (Rapid TermalAnneal) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Photolithography uses a 1 - 3μm negative photoresist for lift-off. The pattern is developed through exposure. TiAlTi is evaporated using a metal evaporator and alloyed using a rapid annealing furnace (Rapid Thermal Annealing).

[0038] Note: The metal coating should be smooth and without breaks. Before evaporation, soak in a 511 strong oxidation solution bath for 10 minutes and soak in dilute hydrochloric acid to further remove the etching derivatives between ohmic contacts.

[0039] 7. Gate Fabrication: Photolithography is performed on the top to pattern the electrode contact area of the gate. The electrode metal Ti / Al / Ti is grown by electron beam evaporation or magnetron sputtering, and the gate electrode is formed through a lift-off process. Photolithography and evaporation are used to fabricate the gate of the device. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off in photolithography. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator.

[0040] 8. Field Plate Fabrication: First, a passivation layer is grown on the top by Plasma Enhanced Chemical Vapor Deposition (PECVD). The passivation layer is at least one of SiN, SiO2, and Al2O3. After photolithography, the conductive channels of the source and the gate are etched. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0041] 9. Deep Etching and Hole Opening: Photolithography and etching are used for deep etching. A photoresist with a thickness of 7 - 9 μm is used as a mask. Deep holes are formed at specific positions through exposure and development. Then, a Cl-based etchant is used to perform deep etching on the GaN HEMT vertical structure epitaxial wafer, and the etching depth is about 3 - 5 μm. - The etching depth is about 3 - 5 μm.

[0042] 10. Drain Fabrication: Photolithography is performed on the bottom to pattern the electrode contact area of the drain. The electrode metal is grown by electron beam evaporation or magnetron sputtering, and the metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi; the drain electrode is formed through a lift-off process, and the drain electrode metal is subjected to rapid thermal annealing treatment in a nitrogen atmosphere to form an ohmic contact in the drain region. Photolithography, etching, and evaporation are used to fabricate the drain of the device. A positive photoresist with a thickness of 1 - 3 μm is used as a mask, and an etcher is used to etch the drain channel at a specific position. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off in photolithography. The pattern is developed through exposure. TiAlTi is evaporated on the drain channel using a metal evaporator, and alloying is achieved through RTA annealing.

[0043] Note: The hole opening here needs to consider the alloying issue in an environment of 480 - 520 °C. Therefore, the etching depth should be below the two-dimensional electron gas. The photolithography angle should be about 60 degrees to make the etched trenches smooth.

[0044] 11. Bonding metal preparation: A passivation layer is grown at the bottom by plasma-enhanced chemical vapor deposition. The passivation layer is composed of at least one of SiN, SiO2, and Al2O3, and the drain electrode lead-out area is lithographed. The gate electrode and source electrode lead-out areas are lithographed at the top to obtain a chip. Lithography and evaporation are used to make the required bonding metal. A negative photoresist with a thickness of 7-9 μm is used for lift-off in lithography. Patterns are developed through exposure. TiAlNi is evaporated using a metal evaporator. A bonder is used. Before bonding, infrared laser alignment is performed to align the bonding metal with the deep etched holes, and the two wafers A and B are bonded together in a vacuum manner.

[0045] See Figure 1 It is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; as can be seen from the figure, when preparing the GaN HEMT vertical structure epitaxy disclosed by the present invention, first, high-quality GaN is selected as the substrate material, which provides the mechanical support and thermal conductivity of the entire epitaxial structure, and at the same time avoids the epitaxial layer defects introduced during the heteroepitaxial process. The GaN drift region and the GaN channel layer are successively epitaxially grown on the GaN substrate. This region is the key part of the chip to withstand the off-state voltage and has a direct impact on the on-resistance of the chip. Subsequently, a layer of AlN (aluminum nitride) insertion layer is deposited on the GaN channel layer. This AlN insertion layer is used to adjust the height and distribution of the electron barrier and further optimize the chip performance. Immediately afterwards, a barrier layer is epitaxially grown on the AlN insertion layer. This layer and the GaN channel layer form a heterojunction to induce a two-dimensional electron gas with high concentration and high mobility, which is the key to forming an efficient electron transport channel. Finally, a dielectric capping layer is in-situ deposited on the barrier layer. This dielectric capping layer not only plays a protective role to prevent damage to the underlying structure during subsequent processes, but also serves as an etch stop layer to ensure the accuracy of subsequent processes.

[0046] See Figure 2Schematic diagram of the vertical structure AlGaN / GaN power chip disclosed by the present invention; it can be seen from the figure that the AlGaN / GaN heterojunction provides a two-dimensional electron gas participating in the operation of the chip, serving as the carrier source for the chip to conduct electricity. The chip gate is located between the source electrodes, and the on / off of the current is controlled by applying a voltage. When the gate voltage is lower than the turn-on voltage (also known as the threshold voltage) of the chip, the two-dimensional electron gas in the channel layer region under the gate is depleted, and the chip is in the off state. The breakdown voltage of the chip depends on the thickness of the channel layer, drift region, and substrate. When the gate voltage is higher than the threshold voltage, the two-dimensional electron gas in the channel layer region under the gate is restored and flows vertically through the channel layer, drift region, and substrate to the drain under the action of the electric field. The dielectric layer in the gate region can effectively reduce gate leakage and lower the operating loss of the chip. The drift region and the substrate are doped with n-type to reduce the bulk resistance, achieving a low on-resistance of the chip. The carrier blocking layers on both sides of the drift region are used to regulate the current direction to ensure that the current does not flow to other regions of the chip. The entire structure shows a complete path of injecting current from the source electrode, efficiently conducting through the GaN epitaxial layer and the substrate, and finally flowing out through the drain. This vertical structure design optimizes the current path, weakens the influence of the interface states between the passivation layer / barrier layer on carrier transport, and improves the efficiency and reliability of the chip.

[0047] See Figure 3Schematic diagram of the vertical structure AlGaN / GaN power device disclosed in the present invention; as can be seen from the figure, the three basic electrodes: Source, Gate, and Drain, together constitute the core part of the field effect transistor (FET), which is used to control the on and off of the current. The source and drain are responsible for the input and output of the current respectively, while the gate controls the current flow in the channel by applying a voltage. The A-sheet structure and the B-sheet structure represent the heterojunction semiconductor layers, the A-sheet is the AlGaN layer, and the B-sheet is the GaN layer. This heterojunction structure is the core of the HEMT, which can form a two-dimensional electron gas (2DEG) with high mobility at the interface, thus significantly improving the conductivity of the device. The bonding layer is used to connect different material layers to ensure the electrical and mechanical stability between the interfaces, which is crucial for the reliability and performance of the device. The drain layer is directly connected to the drain and undertakes the function of current output, while the drift region is located near the drain and is a high-resistance region used to withstand high voltage and improve the breakdown voltage of the device. GBL (Ground Base Layer) and CBL (Conductive Base Layer) represent the base layer and the conductive base layer respectively. The former provides mechanical support and heat conduction, while the latter optimizes the current distribution and heat dissipation. Gallium nitride (GAN) is the core semiconductor material for high-frequency and high-power applications, with excellent electron mobility and high-temperature resistance. The drift region is realized by doping or structural design and is used to expand the voltage tolerance range of the device. Overall, this structural design not only optimizes the current control and breakdown voltage performance, but also improves the overall efficiency and reliability of the device through the design of the heterojunction and functional layers, and is suitable for high-frequency and high-power electronic device fields such as 5G communication and power conversion.

[0048] See Figure 4Flow chart of the preparation method of the low-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention; as can be seen from the figure, the epitaxial wafer of the low-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention first undergoes a strict cleaning step to remove surface contaminants and impurities. Subsequently, through precise positioning and opening processes, key structures such as source and drain electrodes are formed on the material. The electron isolation step ensures electrical isolation between the electrodes and prevents current leakage. Next, the preparation of the source, drain, and gate electrodes is carried out, and the precise formation of these electrodes is crucial for the performance of the chip. Finally, after the deposition and opening of the passivation layer, the low-temperature ohmic GaN HEMT vertical structure chip is completed. The entire preparation process strictly follows the technological process, ensuring the high performance and stability of the finished product, and providing reliable high-performance electronic chips for the modern electronics industry. For the incoming material A, first, it is cleaned to ensure a clean surface, and then positioning preparation is carried out to precisely control the positions of subsequent steps. Next, electron isolation is implemented to enhance the isolation performance of the device, and openings are made on it to form the source region. After that, source preparation, alloying treatment, and the preparation of the gate and field plate are carried out, and finally, the structure is optimized through deep etching opening technology. The incoming material B undergoes a similar cleaning and positioning preparation process, but then drain opening is carried out, followed by electron isolation and drain preparation. In addition, the preparation of bonding metal is also involved to prepare for the subsequent bonding step. Finally, the processed A wafer and B wafer are bonded to complete the manufacture of the entire chip. Through fine cleaning, positioning, isolation, and alloying treatment, the low-temperature ohmic contact performance of the GaN HEMT vertical structure chip is significantly improved. The deep etching opening technology and drain preparation enhance the conductivity and overall reliability of the chip. The preparation of bonding metal and the AB wafer bonding step ensure the integrity of the chip structure and excellent electrical performance. This method not only improves the manufacturing efficiency of the GaN HEMT vertical structure chip but also significantly optimizes its performance, showing broad application prospects.

[0049] Example 1 A preparation method for GaN HEMT vertical structure epitaxy, comprising the following steps: Substrate preparation: Select a 300-μm GaN substrate as the growth basis.

[0050] Substrate treatment: At a temperature of 1100 °C, the GaN substrate is pre-treated, and at the same time, H2 is introduced at a rate of 120 L / min and NH3 is introduced at a rate of 50 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0051] Drift region growth: In the temperature range of 1100 °C and at a growth pressure of 200 torr, a drift region with a thickness of 7 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 600 sccm / min, the flow rate of N2 is 10 L / min, the flow rate of H2 is 90 L / min, the flow rate of NH3 is 45 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 10 sccm / min. The growth temperature is 1100 °C, and the growth rotation speed is 1200 rpm. The drift region is a key part of the HEMT device, and its thickness and growth conditions have an important impact on device performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the device.

[0052] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by lithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 3 μm.

[0053] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1080 °C, the rotation speed is 1200 rpm, the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN, and its thickness is controlled within 300 nm. Among them, the flow rate of TMGa is 500 scmm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0054] Insertion layer growth: Subsequently, at a temperature of 1000 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled within 0.8 nm to optimize device performance. Among them, the flow rate of TMAL is 200 sccm / min, the flow rate of H2 is 190 L / min, and the flow rate of NH3 is 5 L / min. The introduction of the insertion layer can optimize the interface characteristics of the device, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the device. By precisely controlling the thickness and growth conditions of the insertion layer, the device performance can be further optimized.

[0055] Al X Ga(1-X) Growth of N barrier layer: Next, within the temperature range of 1020 °C, at a growth pressure of 1000 rpm and 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, an AlGaN barrier layer with a thickness of 22 nm is grown. X Ga (1-X) The AlGaN barrier layer, where the Al composition X ranges from 20%, plays a key role in controlling current transport. Among them, the flow rate of TMGA is 80 sccm / min, the flow rate of TMAL is 300 sccm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min. The barrier layer is a key part of the HEMT device, and its thickness and growth conditions have an important impact on the current transport characteristics of the device. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the device.

[0056] Growth of SiN dielectric cap layer: Finally, at a temperature of 1000 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric cap layer with a thickness of 2 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, the flow rate of NH3 is 50 L / min, the concentration of the second SiH4 is 2%, and the flow rate is 40 sccm / min. The introduction of the SiN dielectric cap layer can protect the device surface from the influence of the external environment, improving the stability and reliability of the device. At the same time, by precisely controlling the growth parameters of the cap layer and introducing an appropriate amount of the second SiH4, the electrical characteristics of the device surface can be further optimized.

[0057] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0058] A preparation method of a low-temperature ohmic GaN HEMT vertical structure chip includes the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; on the substrate, grow a GaN drift region, an AlN insertion layer, an Al X Ga (1-X) GaN barrier layer, and a SiN dielectric cap layer in sequence by metal-organic chemical vapor deposition.

[0059] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out of the pure water tank, transfer it to a spin dryer. The spin dryer needs to purge N2 at all times, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water with a water resistance of more than 8. The rotation speed changes to 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0060] 3. Positioning preparation: Prepare marks using photolithography and evaporation processes to achieve the purpose of positioning. First, use a 2-μm negative photoresist and coat it evenly on the surface. Expose the pattern using a lithography machine, bake it at 100 °C, and remove the excess photoresist using a positive photoresist developer. Before metal evaporation, bombard the surface of the GaN HEMT vertical structure epitaxial wafer with an ion source for 2 min. Evaporate the metal using CrTiNi. After evaporation, perform stripping using a stripper. The stripper is first immersed in a degluing tank for 10 min, and finally, high-pressure rinsing is performed with pure water. During the rinsing process, add a rotation of 1000 rpm for 2 min.

[0061] 4. Electron isolation: Perform electron isolation on the top using photolithography and ion implantation to form a chip isolation region and achieve electrical isolation of the active region. The implanted element is F. For photolithography, use a 3-μm positive photoresist, expose and develop it to make a layer of pattern as a mask before ion implantation. For ion implantation, use boron ions to dope the areas without a photolithography mask to achieve the purpose of electron isolation.

[0062] 5. Source opening: Perform opening on the top using photolithography and etching processes. Lithograph the window area of the source electrode, and use inductively coupled plasma etching (ICP) to remove the SiN dielectric cap layer in the window area. For photolithography, use a 3-μm positive photoresist, expose and develop it to make a layer of pattern as a mask before etching. For etching, use an ICP etcher to first etch the dielectric with F - base, and then etch GaN with Cl - base.

[0063] Note: The opening here needs to consider the alloy problem in an environment of 500 °C. Therefore, the depth after etching should be below the two-dimensional electron gas. The photolithography angle should be about 60 so that the etched grooves can be smooth.

[0064] 6. Source electrode preparation: The source electrode of the device is fabricated by photolithography and evaporation. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti. The source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (RTA) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Photolithography uses a negative photoresist of about 2 μm for lift-off. The pattern is developed by exposure. TiAlTi is evaporated using a metal evaporator and annealed using a rapid thermal annealing furnace to form an alloy.

[0065] Note: The metal coating should be smooth and continuous. Before evaporation, soak it in a 511 strong oxidation solution tank for 10 minutes, and then soak it in dilute hydrochloric acid to further remove the etching derivatives between ohmic contacts.

[0066] 7. Gate electrode preparation: The electrode contact area of the gate electrode is lithographed on the top, and the electrode metal Ti / Al / Ti is grown by electron beam evaporation or magnetron sputtering. The gate electrode is formed through a lift-off process. The gate of the device is fabricated by photolithography and evaporation. Photolithography uses a negative photoresist of 2 μm for lift-off. The pattern is developed by exposure. TiAlNi is evaporated using a metal evaporator.

[0067] 8. Field plate preparation: First, a passivation layer is grown on the top by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is SiN. After photolithography, the conductive channels of the source and gate are etched. A negative photoresist of 2 μm is used for lift-off. The pattern is developed by exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0068] 9. Deep etching and opening holes: Deep etching is performed by photolithography and etching. An 8-μm photoresist is used as a mask. Deep holes are made at specific positions through exposure and development. Then, a Cl-based etchant is used to perform deep etching on the GaN HEMT vertical structure epitaxial wafer, and the etching depth is about 3 - 5 μm. -

[0069] 10. Drain electrode preparation: The electrode contact area of the drain electrode is lithographed on the bottom, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti. The drain electrode is formed through a lift-off process, and the drain electrode metal is subjected to rapid thermal annealing treatment in a nitrogen atmosphere to form an ohmic contact in the drain region. The drain of the device is fabricated by photolithography, etching, and evaporation. A 2-μm positive photoresist is used as a mask, and a drain channel is etched at a specific position using an etching machine. Photolithography uses a 2-μm negative photoresist for lift-off. The pattern is developed by exposure. TiAlTi is evaporated on the drain channel using a metal evaporator and annealed using RTA to form an alloy. ​

[0070] Note: The opening here should consider the alloy issue in an environment around 500 °C. Therefore, the etched depth should be below the two-dimensional electron gas. The lithography angle should be about 60 degrees to make the etched grooves smooth.

[0071] 11. Bonding metal preparation: A passivation layer is grown on the bottom by plasma-enhanced chemical vapor deposition. The passivation layer is composed of SiN, and the drain electrode lead-out area is lithographed. The gate electrode and source electrode lead-out areas are lithographed on the top to obtain the chip. Lithography and evaporation are used to make the required bonding metal. A negative photoresist with a thickness of 8 μm is used for lift-off in lithography. The pattern is developed by exposure. TiAlNi is evaporated using a metal evaporator. A bonder is used. Before bonding, infrared laser alignment is performed to align the bonding metal with the deep etched holes, and the two wafers A and B are bonded together in a vacuum manner.

[0072] Example 2 A preparation method for a vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: A 400-μm GaN substrate is selected as the growth basis.

[0073] Substrate treatment: The GaN substrate is pretreated at a temperature of 1000 °C. At the same time, N2 is introduced at a rate of 50 L / min, H2 is introduced at a rate of 50 L / min, and NH3 is introduced at a rate of 1 L / min to prepare for subsequent epitaxial growth. The high-temperature pretreatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0074] Drift region growth: In a temperature range of 1000 °C and a growth pressure of 200 torr, by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4, a drift region with a thickness of 0.5 μm is grown. This layer is crucial for device performance. Among them, the flow rate of TMGA is 200 sccm / min, the flow rate of H2 is 50 L / min, the flow rate of NH3 is 1 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 0.1 sccm / min. The growth temperature is 1000 °C, and the growth rotation speed is 800 rpm.

[0075] Ion implantation: The carrier blocking layer region is defined by lithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1 μm.

[0076] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1000 °C, the rotation speed is 800 rpm, the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled at 150 nm. The introduction speed of TMGa is 200 scmm / min, the introduction speed of H2 is 50 L / min, and the introduction speed of NH3 is 10 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0077] Insertion layer growth: Subsequently, at a temperature of 800 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 0.1 nm to optimize device performance. Among them, the introduction speed of TMAL is 0.1 sccm / min, the introduction speed of N2 is 20 L / min, the introduction speed of H2 is 50 L / min, and the introduction speed of NH3 is 1 L / min.

[0078] Barrier layer growth: Then, in the temperature range of 800 °C and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 15 nm is grown, where the Al component X ranges from 15%. This layer plays a key role in controlling current transmission. Among them, the introduction speed of TMGA is 0.1 sccm / min, the introduction speed of TMAL is 50 sccm / min, the introduction speed of N2 is 0.1 L / min, the introduction speed of H2 is 50 L / min, and the introduction speed of NH3 is 1 L / min.

[0079] SIN dielectric capping layer growth: Finally, at a temperature of 700 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric capping layer with a thickness of 0.1 nm is grown to protect and optimize the device surface. Among them, the introduction speed of N2 is 0.1 L / min, the introduction speed of H2 is 50 L / min, the introduction speed of NH3 is 1 L / min, and the concentration of the second SIH4 is 2%, and the introduction speed is 0.1 sccm / min.

[0080] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0081] A preparation method for a low-temperature ohmic GaN HEMT vertical structure chip includes the following steps: Differences from Example 1 are as follows: 3. Alignment and Preparation: First, a 1-μm negative photoresist is evenly coated on the surface.

[0082] 4. Electron Isolation: The implanted elements are F and Ar.

[0083] 5. Source Opening: The lithography angle should be 55° to make the etched trenches smooth.

[0084] 6. Source Preparation: The metal consists of Ti and Al. A 1-μm negative photoresist is used for lift-off in lithography.

[0085] 7. Gate Preparation: A 1-μm negative photoresist is used for lift-off in lithography.

[0086] 8. Field Plate Preparation: The passivation layer is SiN and SiO2. A 1-μm negative photoresist is used for lift-off.

[0087] 9. Deep Etching Opening: A 7-μm photoresist is used as a mask. The etching depth is 3 μm.

[0088] 10. Drain Preparation: The metal consists of Ti and Al. A 1-μm positive photoresist is used as a mask. A 1-μm negative photoresist is used for lift-off in lithography. The lithography angle should be 55° to make the etched trenches smooth.

[0089] 11. Bonding Metal Preparation: The passivation layer consists of SiN and SiO2. A 7-μm negative photoresist is used for lift-off in lithography.

[0090] Example 3 A preparation method for vertical structure epitaxy of GaN HEMT includes the following steps: Substrate Preparation: A 600-μm GaN substrate is selected as the growth base.

[0091] Substrate Treatment: The GaN substrate is pre-treated at a temperature of 1020 °C. Meanwhile, N2 is introduced at a rate of 70 L / min, H2 at a rate of 150 L / min, and NH3 at a rate of 60 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0092] Drift region growth: In the temperature range of 1070 °C and under a growth pressure of 200 torr, a drift region with a thickness of 10 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the feeding rate of TMGA is 500 sccm / min, the feeding rate of N2 is 20 L / min, the feeding rate of H2 is 100 L / min, the feeding rate of NH3 is 50 L / min, the concentration of the first SIH4 is 200 ppm, and the feeding rate is 20 sccm / min. The growth temperature is 1050 °C, and the growth rotation speed is 900 rpm.

[0093] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 5 μm.

[0094] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1100 °C, the rotation speed is 1000 rpm, the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN, and its thickness is controlled within 200 nm. Among them, the feeding rate of TMGa is 600 scmm / min, the feeding rate of N2 is 80 L / min, the feeding rate of H2 is 100 L / min, and the feeding rate of NH3 is 80 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0095] Insertion layer growth: Subsequently, at a temperature of 1050 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled within 0.7 nm to optimize device performance. Among them, the feeding rate of TMAL is 300 sccm / min, the feeding rate of N2 is 40 L / min, the feeding rate of H2 is 180 L / min, and the feeding rate of NH3 is 10 L / min.

[0096] Barrier layer growth: Then, in the temperature range of 1050 °C and under a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X)N barrier layer, where the Al component X ranges from 25%, and this layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 100 sccm / min, the flow rate of TMAL is 350 sccm / min, the flow rate of N2 is 60 L / min, the flow rate of H2 is 110 L / min, and the flow rate of NH3 is 60 L / min.

[0097] SIN dielectric capping layer growth: Finally, at a temperature of 900 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SIN dielectric capping layer with a thickness of 10 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 60 L / min, the flow rate of H2 is 110 L / min, the flow rate of NH3 is 60 L / min, the concentration of the second SiH4 is 2%, and the flow rate is 50 sccm / min.

[0098] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0099] A preparation method for a low-temperature ohmic GaN HEMT vertical structure chip includes the following steps: Differing from Example 1: 3. Alignment preparation: First, use a 3-μm negative photoresist and coat it evenly on the surface.

[0100] 4. Electron isolation: The implanted element is B.

[0101] 5. Source opening: The lithography angle should be 65° so that the etched trench can be smooth.

[0102] 6. Source preparation: The metal is composed of Ni and TiN. Lithography uses a 3-μm negative photoresist for lift-off.

[0103] 7. Gate preparation: Lithography uses a 3-μm negative photoresist for lift-off.

[0104] 8. Field plate preparation: The passivation layer is SiO2. Use a 3-μm negative photoresist for lift-off.

[0105] 9. Deep etching opening: Use a 9-μm photoresist as a mask. The etching depth is 3 μm.

[0106] 10. Drain preparation: The metal is composed of Ni and TiN. Use a 3-μm positive photoresist as a mask. Lithography uses a 3-μm negative photoresist for lift-off. The lithography angle should be 65° so that the etched trench can be smooth.

[0107] 11. Bonding metal preparation: The passivation layer is composed of SiO2. Lithography uses a 9-μm negative photoresist for lift-off.

[0108] Example 4 A preparation method for the epitaxy of a vertical GaN HEMT structure, comprising the following steps: Substrate preparation: Select a 1000-μm GaN substrate as the growth basis.

[0109] Substrate treatment: At a temperature of 1150 °C, pre-treat the GaN substrate. Meanwhile, introduce N2 at a rate of 100 L / min, H2 at a rate of 200 L / min, and NH3 at a rate of 100 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0110] Drift region growth: In the temperature range of 1150 °C and at a growth pressure of 200 torr, grow a drift region with a thickness of 50 μm by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the introduction rate of TMGA is 1000 sccm / min, the introduction rate of N2 is 100 L / min, the introduction rate of H2 is 200 L / min, the introduction rate of NH3 is 100 L / min, the concentration of the first SIH4 is 200 ppm, and the introduction rate is 500 sccm / min. The growth temperature is 1150 °C, and the growth rotation speed is 1150 rpm.

[0111] Ion implantation: Define the carrier blocking layer region on the epitaxial drift region grown in the previous step by photolithography, and perform ion implantation on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 20 μm.

[0112] Channel layer growth: On the epitaxial wafer after ion implantation, perform secondary epitaxy. Among them, the growth temperature is 1150 °C, the rotation speed is 1150 rpm, the growth pressure is 200 torr, and at the same time introduce TMGa, N2, H2, and NH3 to grow undoped GaN, and its thickness is controlled at 400 nm. Among them, the introduction rate of TMGa is 1000 scmm / min, the introduction rate of H2 is 200 L / min, and the introduction rate of NH3 is 100 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0113] Insertion layer growth: Subsequently, at a temperature of 1100 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 were adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 2 nm to optimize device performance. Among them, the introduction rate of TMAL was 500 sccm / min, the introduction rate of N2 was 100 L / min, the introduction rate of H2 was 200 L / min, and the introduction rate of NH3 was 100 L / min.

[0114] Barrier layer growth: Then, within a temperature range of 1100 °C and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 35 nm was grown, where the Al component X ranged from 50%, and this layer plays a key role in controlling current transport. Among them, the introduction rate of TMGA was 500 sccm / min, the introduction rate of TMAL was 500 sccm / min, the introduction rate of N2 was 100 L / min, the introduction rate of H2 was 200 L / min, and the introduction rate of NH3 was 100 L / min.

[0115] SIN dielectric capping layer growth: Finally, at a temperature of 1100 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SiH4 gas, a SIN dielectric capping layer with a thickness of 100 nm was grown to protect and optimize the device surface. Among them, the introduction rate of N2 was 100 L / min, the introduction rate of H2 was 200 L / min, the introduction rate of NH3 was 100 L / min, the concentration of the second SiH4 was 2%, and the introduction rate was 500 sccm / min.

[0116] Finally, a GaN HEMT vertical structure epitaxy was obtained.

[0117] A preparation method for a low-temperature ohmic GaN HEMT vertical structure chip includes the following steps: Different from Example 1: 4. Electron isolation: The injected element is N.

[0118] 5. Source opening: The lithography angle should be 65° to make the etched trench smooth.

[0119] 6. Source preparation: The metal is composed of AlSi.

[0120] 8. Field plate preparation: The passivation layer is Al2O3.

[0121] 10. Drain preparation: The metal is composed of AlSi. The lithography angle should be 65° to make the etched grooves smooth.

[0122] 11. Bonding metal preparation: The passivation layer is composed of Al2O3.

[0123] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a low-temperature ohmic GaN HEMT vertical structure chip, characterized in that: The following steps are involved: 1) The GaN drift region, AlN insertion layer, Al X Ga (1-X) N barrier layer and SiN dielectric cap layer to obtain GaN HEMT vertical structure epitaxial wafer; the Al X Ga (1-X) In the N barrier layer, 0.15≤X≤0.5; 2) Clean and dry the GaN HEMT vertical structure epitaxial wafer, and then make positioning marks; 3) Form a chip isolation area on the top through photolithography and ion implantation; 4) Photolithography a source window area on the top, and etching away the SiN dielectric cap layer in the window area; 5) Photolithography the source electrode contact area on the top, and evaporate the electrode metal. After peeling off, the source electrode is formed; 6) Photolithography the gate electrode contact area on the top, and evaporate the electrode metal to form the gate electrode; 7) Grow a passivation layer on the top, etch out the conductive channels of the source and gate, and obtain the field plate after evaporation; 8) Deeply etch and open holes in GaN HEMT vertical structure epitaxial wafers; 9) Photolithography the drain electrode contact area at the bottom, and evaporate the electrode metal. After stripping, the drain electrode is formed; 10) Grow a passivation layer at the bottom and photolithography the drain electrode lead-out area; 11) The gate electrode and source electrode lead-out regions are photolithographically formed on the top to obtain a low-temperature ohmic GaN HEMT vertical structure chip.

2. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 3), the ion implanted element includes: at least one of F, Ar, B and N; the depth of ion implantation is 0.1-20 μm; In step 4), the window region of the source electrode has a depth below the two-dimensional electron gas, and the photolithography angle is 60°; the SiN dielectric cap layer in the window region is removed by inductively coupled plasma etching; In step 5), after soaking in a strong oxidizing solution tank before evaporation, dilute hydrochloric acid is added; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi.

3. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 6), the gate electrode is a Ti / Al / Ti electrode metal; In step 7), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3; In step 9), the depth of the electrode contact region of the drain is below the two-dimensional electron gas, and the photolithography angle is 60°; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 10), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

4. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the pretreatment conditions of the substrate include: pretreating the substrate at 1000-1150° C., while introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min.

5. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for the growth of the GaN drift region include: at 1000-1150° C. and a growth pressure of 200 torr, by controlling the flow rates of trimethylgallium, N2, H2, NH3 and the first monosilane, a GaN drift region with a thickness of 0.5-50 μm is grown, the growth temperature is 1000-1150° C., and the growth speed is 800-1200 rpm; wherein the introduction rate of trimethylgallium is 200-1000 sccm / min, the introduction rate of N2 is 0-100 L / min, the introduction rate of H2 is 50-200 L / min, the introduction rate of NH3 is 1-100 L / min, the concentration of the first monosilane is 200 ppm, and the introduction rate is 0-500 sccm / min.

6. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), a carrier blocking layer region is defined on the GaN drift region by photolithography, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000-1150°C, the rotation speed is 800-1200rpm, the growth pressure is 200torr, and trimethylgallium, N2, H2 and NH3 are introduced at the same time to grow undoped GaN, and the thickness of GaN is 150-400nm, wherein the introduction rate of trimethylgallium is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 0-200L / min, and the introduction rate of NH3 is 0-100L / min.

7. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the growth conditions of the AlN insertion layer include: at 800-1100°C and a growth pressure of 75torr, trimethylaluminum, H2 and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer, and the thickness of the AlN insertion layer is 0-2nm; wherein the introduction rate of trimethylaluminum is 0-500sccm / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

8. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), Al X Ga (1-X) The growth conditions of the N barrier layer include: growing an Al layer with a thickness of 15-35 nm by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2 and NH3 at 800-1100°C, 800-1200rpm, and a growth pressure of 100 torr. X Ga (1-X) N barrier layer; wherein the molar percentage of X is 15%-50%, the introduction rate of trimethylgallium is 0-500sccm / min, the introduction rate of trimethylaluminum is 50-500sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

9. The method for preparing a low-temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for growing the SiN dielectric cap layer include: growing a SiN dielectric cap layer with a thickness of 0.1-100 nm at 700-1100° C. and a growth pressure of 200 torr by adjusting the flow rates of N2, H2 and NH3 and introducing a second monosilane; wherein the N2 introduction rate is 0-100 L / min, the H2 introduction rate is 50-200 L / min, the NH3 introduction rate is 1-100 L / min, the concentration of the second monosilane is 2%, and the second monosilane introduction rate is 0-500 sccm / min.

10. A low temperature ohmic GaN HEMT vertical structure chip, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the GaN layer, which comprises a substrate, a GaN drift region, an AlN insertion layer, an AlN layer, and a GaN layer. X Ga (1-X) The stacked structure consists of an N barrier layer and a SiN dielectric cap layer; the Al X Ga (1-X) In the N barrier layer, 0.15≤X≤0.5; A source electrode penetrating the SiN dielectric cap layer, the source electrode and the Al X Ga (1-X) The N barrier layer forms an ohmic contact; A gate electrode is disposed on the SiN dielectric cap layer, and the gate electrode is connected to the Al X Ga (1-X) The N barrier layer forms a Schottky contact; A top passivation layer covering the source electrode and the gate electrode, wherein a metal field plate is provided in the top passivation layer, one end of the metal field plate is connected to the gate electrode, and the other end of the metal field plate extends laterally toward the source electrode; The GaN drift region, the AlN insertion layer and the Al X Ga (1-X) A conductive hole in the N barrier layer, wherein the conductive hole is filled with metal and is in direct contact with the source electrode and the back side of the substrate; A drain electrode disposed on the back side of the substrate, and a bottom passivation layer covering the drain electrode, wherein the bottom passivation layer is provided with a lead-out window penetrating therethrough to expose the drain electrode; A chip isolation region surrounding the sidewall of the stacked structure, the isolation region being formed by ion implantation and penetrating the Al X Ga (1-X) N barrier layer, AlN insertion layer and GaN drift region.

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