Manufacturing method of display chip, display chip and substrate structure

Abstract

The invention discloses a manufacturing method of a display chip, the display chip and a substrate structure, and belongs to the technical field of semiconductors. The method comprises the following steps: forming a substrate structure; the base structure comprises a substrate and a two-dimensional material layer located on one side of the substrate; forming a pixel unit on one side, deviating from the substrate, of the two-dimensional material layer, wherein the pixel unit comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer which are sequentially arranged on one side, deviating from the substrate, of the two-dimensional material layer; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer; and removing the substrate structure. The damage risk of the pixel units can be reduced, and the light-emitting performance of the display chip can be improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a display chip, a display device and a manufacturing method thereof, a display chip and a substrate structure. Background Art

[0002] At present, the stress between the substrate and the chip structure in display chips such as Micro-LEDs is relatively large. When the chip structure is peeled off from the substrate, it is easy to damage the pixel units in the chip structure, affecting the light-emitting performance of the display chip. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a manufacturing method of a display chip, a display chip and a substrate structure, which can reduce the damage risk of pixel units and improve the light-emitting performance of the display chip.

[0004] In a first aspect, this application provides a manufacturing method of a display chip, including:

[0005] Forming a substrate structure; the substrate structure includes a substrate and a two-dimensional material layer located on one side of the substrate;

[0006] Forming pixel units on the side of the two-dimensional material layer facing away from the substrate, the pixel units including a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer sequentially arranged on the side of the two-dimensional material layer facing away from the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer;

[0007] Removing the substrate structure.

[0008] According to the manufacturing method of the display chip of this application, a two-dimensional material layer is arranged on one side of the substrate, and the weak van der Waals force between layers is used to reduce the stress between the chip structure and the substrate, so as to reduce the damage risk of pixel units and improve the light-emitting performance of the display chip when the substrate is peeled off.

[0009] According to an embodiment of this application, the two-dimensional material layer corresponds to the position of the pixel units.

[0010] According to an embodiment of this application, the substrate includes a substrate pattern layer located on the side of the substrate close to the two-dimensional material layer;

[0011] The forming of the substrate structure includes:

[0012] Providing a substrate;

[0013] Forming an initial two-dimensional material layer on one side of the substrate;

[0014] Patterning the initial two-dimensional material layer to obtain the two-dimensional material layer, and patterning one side of the substrate close to the initial two-dimensional material layer to obtain the substrate pattern layer.

[0015] According to an embodiment of the present application, the substrate pattern layer and the two-dimensional material layer form a two-dimensional material structure;

[0016] The shape of the two-dimensional material structure includes at least one of a cylindrical shape, a hemispherical shape, a conical shape, and a polyhedral shape.

[0017] According to an embodiment of the present application, the two-dimensional material layer includes at least one of graphene, hexagonal boron nitride, and molybdenum disulfide.

[0018] According to an embodiment of the present application, removing the substrate structure includes:

[0019] Removing the substrate;

[0020] Removing the two-dimensional material layer.

[0021] According to an embodiment of the present application, removing the substrate includes:

[0022] Forming a grid protection layer on one side of the substrate facing away from the pixel unit, and the grid protection layer corresponds to the position of the pixel unit;

[0023] Removing the substrate and simultaneously removing the grid protection layer.

[0024] According to an embodiment of the present application, the grid protection layer includes at least one of silicon oxide and silicon nitride.

[0025] According to an embodiment of the present application, removing the substrate includes:

[0026] Using a laser lift-off technique to remove the substrate.

[0027] According to an embodiment of the present application, the substrate structure further includes a transition layer located on one side of the two-dimensional material layer facing away from the substrate and covering the substrate, and the pixel unit is located on one side of the transition layer facing away from the substrate;

[0028] Removing the two-dimensional material layer includes:

[0029] Removing the transition layer and simultaneously removing the two-dimensional material layer.

[0030] According to an embodiment of the present application, the transition layer includes a buffer layer and a first undoped semiconductor layer;

[0031] The buffer layer is located on the side of the two-dimensional material layer facing away from the substrate and covers the substrate, and the first undoped semiconductor layer is located between the buffer layer and the pixel unit.

[0032] According to an embodiment of the present application, the transition layer further includes a gradient buffer layer located between the buffer layer and the first undoped semiconductor layer.

[0033] According to an embodiment of the present application, before removing the substrate structure, it further includes:

[0034] Bonding the side of the pixel unit facing away from the substrate structure to a substrate.

[0035] According to an embodiment of the present application, the pixel unit further includes a first transparent conductive layer and a first reflective layer sequentially disposed on the side of the second semiconductor layer facing away from the quantum well light-emitting layer, and the substrate includes a second bonding structure;

[0036] The bonding the side of the pixel unit facing away from the substrate structure to a substrate includes:

[0037] Forming a dielectric layer on the side of the first reflective layer facing away from the first transparent conductive layer;

[0038] Forming a first bonding structure penetrating through the dielectric layer and connected to the first reflective layer;

[0039] Bonding the pixel unit to the substrate through the first bonding structure and the second bonding structure.

[0040] According to an embodiment of the present application, the first bonding structure includes a bonding layer and a bonding protection layer;

[0041] The forming a first bonding structure penetrating through the dielectric layer and connected to the first reflective layer includes:

[0042] Forming an opening penetrating through the dielectric layer;

[0043] Forming the bonding protection layer on the sidewall of the opening;

[0044] Forming the bonding layer connected to the first reflective layer in the opening.

[0045] According to an embodiment of the present application, before forming the dielectric layer on the side of the first reflective layer facing away from the first transparent conductive layer, it further includes:

[0046] Forming a passivation layer on the side of the first reflective layer facing away from the first transparent conductive layer, and the passivation layer covers the sidewall of the pixel unit;

[0047] A second reflective layer is formed on the surface of the passivation layer. The dielectric layer is located on a side of the second reflective layer away from the first reflective layer. The first bonding structure penetrates through the dielectric layer, the second reflective layer, and the passivation layer to be connected to the first reflective layer.

[0048] According to an embodiment of the present application, after removing the substrate structure, it further includes:

[0049] A second transparent conductive layer is formed on a side of the pixel unit away from the substrate;

[0050] A microlens is formed on a side of the second transparent conductive layer away from the substrate.

[0051] According to an embodiment of the present application, the pixel unit further includes a second undoped semiconductor layer, a barrier layer, a first superlattice layer, and a second superlattice layer that are sequentially disposed between the first semiconductor layer and the quantum well light-emitting layer.

[0052] In a second aspect, the present application provides a display chip, which is formed by using the manufacturing method of the display chip described in the first aspect above.

[0053] In a third aspect, the present application provides a substrate structure, which is applied to the manufacturing method of the display chip described in the first aspect above. The substrate structure includes:

[0054] A substrate;

[0055] A two-dimensional material layer, located on one side of the substrate.

[0056] One or more of the above technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0057] A two-dimensional material layer is disposed on one side of the substrate, and the weak van der Waals force between layers is used to reduce the stress between the chip structure and the substrate, so as to reduce the risk of damage to the pixel unit when the substrate is peeled off and improve the light-emitting performance of the display chip.

[0058] The additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0060] Figure 1 is a schematic flowchart of a manufacturing method of a display chip provided by an embodiment of the present application;

[0061] Figure 2It is one of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0062] Figure 3 It is the second of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0063] Figure 4 It is the third of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0064] Figure 5 It is the fourth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0065] Figure 6 It is the fifth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0066] Figure 7 It is the sixth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0067] Figure 8 It is the seventh of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0068] Figure 9 It is the eighth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0069] Figure 10 It is the ninth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0070] Figure 11 It is the tenth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0071] Figure 12 It is the eleventh of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0072] Figure 13 It is the twelfth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0073] Figure 14 It is the thirteenth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0074] Figure 15 It is the fourteenth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0075] Figure 16 It is the fifteenth of the schematic structural diagrams in the manufacturing process of the display chip provided by the embodiments of the present application;

[0076] Figure 17 It is the sixteenth structural schematic diagram in the manufacturing process of the display chip provided by the embodiments of the present application;

[0077] Figure 18 It is the structural schematic diagram of the display chip provided by the embodiments of the present application;

[0078] Figure 19 It is the structural schematic diagram of the substrate structure provided by the embodiments of the present application. Detailed Embodiments

[0079] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application.

[0080] The following refers to the accompanying drawings to describe the manufacturing method of the display chip, the display chip, and the substrate structure provided by the embodiments of the present application.

[0081] Figure 1 It is a flowchart of the manufacturing method of the display chip provided by the embodiments of the present application. Among them, the display chip can be a Micro-LED display chip.

[0082] As Figure 1 shown, the manufacturing method of the display chip provided by the embodiments of the present application includes steps 110 to 130.

[0083] Step 110: Form a substrate structure; the substrate structure includes a substrate and a two-dimensional material layer located on one side of the substrate.

[0084] Combined with Figure 2 shown, the substrate structure 10 may include a substrate 1 and a two-dimensional material layer 2. Among them, the two-dimensional material layer 2 is located on one side of the substrate 1, and the two-dimensional material layer 2 does not completely cover one side of the substrate 1 to ensure the growth of subsequent film layers.

[0085] In some embodiments, the substrate 1 includes a substrate pattern layer 11 on the side of the substrate 1 close to the two-dimensional material layer 2, and the substrate pattern layer 11 and the two-dimensional material layer 2 form a two-dimensional material structure 21.

[0086] In some embodiments, the shape of the two-dimensional material structure 21 includes at least one of a cylindrical shape, a hemispherical shape, a conical shape, and a polyhedral shape, etc.

[0087] The two-dimensional material layer 2 may include at least one of graphene, hexagonal boron nitride and molybdenum disulfide, and the thickness of the two-dimensional material layer 2 may be 1 nm to 30 nm. The substrate 1 may include a c-plane sapphire substrate, a Si substrate, an n-SiC substrate or an n-GaN homogeneous substrate.

[0088] In some embodiments, forming a base structure in step 110 includes: providing a substrate; forming an initial two-dimensional material layer on one side of the substrate; patterning the initial two-dimensional material layer to obtain a two-dimensional material layer, and patterning the side of the substrate close to the initial two-dimensional material layer to obtain a substrate pattern layer.

[0089] For example, a chemical vapor deposition process is used to grow an initial two-dimensional material layer on one side of the substrate 1. Photoresist is deposited, and the initial two-dimensional material layer is etched using an exposure process and an ICP (Inductively Coupled Plasma) process, and the ICP process needs to etch into the substrate 1 to a depth of about 10nm to 50nm. Among them, the initial two-dimensional material layer is etched into a two-dimensional material layer 2, and the side of the substrate 1 close to the initial two-dimensional material layer is etched into a substrate pattern layer 11. The substrate pattern layer 11 and the two-dimensional material layer 2 constitute a two-dimensional material structure 21.

[0090] It should be noted that the two-dimensional material layer 2 can also be manufactured and formed by other processes, and the two-dimensional material structure 21 can also be manufactured and formed by other processes, which are not specifically limited here.

[0091] When the substrate 1 includes an n-GaN homogeneous substrate, the base structure 10 may include only the substrate 1 and the two-dimensional material layer 2 .

[0092] In some embodiments, Figure 3 As shown, the base structure 10 may further include a transition layer 3 , which is located on a side of the two-dimensional material layer 2 facing away from the substrate 1 and covers the substrate 1 .

[0093] When the substrate 1 includes an n-SiC substrate, the base structure 10 may further include a transition layer 3 , and the transition layer 3 may include an n-AlGaN layer.

[0094] For example, a MOCVD system is used to form a transition layer 3 on the side of the two-dimensional material layer 2 facing away from the substrate 1, and the transition layer 3 covers the substrate 1. It should be noted that the transition layer 3 can also be formed by other processes, which are not specifically limited here.

[0095] In some embodiments, the transition layer 3 may include a buffer layer and a first non-doped semiconductor layer. The buffer layer is located on the side of the two-dimensional material layer 2 facing away from the substrate 1 and covers the substrate 1, and the first non-doped semiconductor layer is located on the side of the buffer layer facing away from the substrate 1.

[0096] When the substrate 1 includes a c-plane sapphire substrate, the base structure 10 may further include a transition layer 3, and the transition layer 3 may include a buffer layer and a first undoped semiconductor layer. The buffer layer may include an AlN buffer layer, and the first undoped semiconductor layer may include a u-GaN layer.

[0097] For example, using a PVD (Physical Vapor Deposition) device, a buffer layer is deposited on the side of the two-dimensional material layer 2 away from the substrate 1. Then, using an MOCVD (Metal Organic Chemical Vapor Deposition) device and a high pressure and a low V / III ratio, a first undoped semiconductor layer is deposited on the side of the buffer layer away from the substrate 1, with a thickness of about 0.2 μm to 0.5 μm and a reaction chamber temperature of 1020 °C to 1040 °C. Such growth conditions are conducive to the rapid nucleation of GaN materials.

[0098] Then, using a low pressure and a high V / III ratio, the first undoped semiconductor layer is continuously grown, with a thickness of about 1 μm to 3 μm and a reaction chamber temperature of 1040 °C to 1080 °C. Such growth conditions are conducive to the rapid film formation of GaN materials. After growing the first undoped semiconductor layer, a CMP polishing process is performed on the first undoped semiconductor layer to ensure the flatness of the subsequent grown film layers. Then, using an MOCVD device, the first undoped semiconductor layer is continuously grown, with a thickness that can be 1 μm to 2 μm and a reaction chamber temperature of 1040 °C to 1080 °C.

[0099] It should be noted that the buffer layer and the undoped semiconductor layer can also be formed by other processes, and specific limitations are not made here.

[0100] In some embodiments, the transition layer 3 may further include a graded buffer layer located between the buffer layer and the first undoped semiconductor layer.

[0101] When the substrate 1 includes a Si substrate or an n-SiC substrate, the base structure 10 may further include a transition layer 3, and the transition layer 3 may include a buffer layer, a graded buffer layer, and a first undoped semiconductor layer. The buffer layer may include an AlN buffer layer, the graded buffer layer may include a graded AlGaN layer, and the first undoped semiconductor layer may include a u-GaN layer.

[0102] For example, using an MOCVD device, a buffer layer, a graded buffer layer, and a first undoped semiconductor layer are sequentially grown on the side of the two-dimensional material layer 2 away from the substrate 1. It should be noted that the buffer layer, the graded buffer layer, and the first undoped semiconductor layer can also be formed by other processes, and specific limitations are not made here.

[0103] Step 120: Form pixel units on the side of the two-dimensional material layer facing away from the substrate. The pixel units include a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer that are sequentially disposed on the side of the two-dimensional material layer facing away from the substrate. One of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer.

[0104] In some embodiments, the positions of the pixel units correspond to the two-dimensional material layer, so as to reduce the risk of damage to the pixel units and improve the light-emitting performance of the display chip when the substrate is peeled off subsequently.

[0105] Combined Figures 4 to 11 As shown, forming the pixel units on the side of the two-dimensional material layer facing away from the substrate in Step 120 includes: forming an initial first semiconductor layer 4' on the side of the two-dimensional material layer 2 facing away from the substrate 1; forming an initial quantum well light-emitting layer 5' on the side of the initial first semiconductor layer 4' facing away from the substrate 1; forming an initial second semiconductor layer 6' on the side of the initial quantum well light-emitting layer 5' facing away from the initial first semiconductor layer 4'; etching the initial first semiconductor layer 4', the initial quantum well light-emitting layer 5', and the initial second semiconductor layer 6' to correspondingly form the first semiconductor layer 4, the quantum well light-emitting layer 5, and the second semiconductor layer 6, and obtaining the pixel units 20. The pixel units 20 include the first semiconductor layer 4, the quantum well light-emitting layer 5, and the second semiconductor layer 6.

[0106] Among them, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer. Alternatively, the first semiconductor layer 4 is a p-type semiconductor layer, and the second semiconductor layer 6 is an n-type semiconductor layer.

[0107] In some implementations, in the direction A towards the substrate structure 10, the cross-sectional area of the pixel units 20 can gradually increase, that is, the cross-sectional area of the first semiconductor layer 4 is larger than the cross-sectional area of the quantum well light-emitting layer 5, and the cross-sectional area of the quantum well light-emitting layer 5 is larger than the cross-sectional area of the second semiconductor layer 6.

[0108] In this embodiment, the cross-sectional area of the pixel units 20 gradually increases in the direction A towards the substrate structure 10 to reduce the light-emitting divergence angle of the display chip, improve the light extraction efficiency of the display chip, and further improve the light efficiency of the display chip.

[0109] In some embodiments, the longitudinal section of the pixel units 20 is an isosceles trapezoid.

[0110] In some embodiments, such as Figure 4As shown, the initial first semiconductor layer 4' includes an initial heavily doped semiconductor layer 41' and an initial lightly doped semiconductor layer 42'. The initial heavily doped semiconductor layer 41' is located on one side of the substrate structure 10. For example, the initial heavily doped semiconductor layer 41' is located on the side of the transition layer 3 away from the substrate 1, and the initial lightly doped semiconductor layer 42' is located on the side of the initial heavily doped semiconductor layer 41' away from the substrate structure 10.

[0111] For example, the reaction chamber temperature is 1040°C to 1080°C. SiH4 is selected as the n-type dopant for the GaN layer. The initial heavily doped semiconductor layer 41' is grown on the side of the transition layer 3 away from the substrate 1, and the initial lightly doped semiconductor layer 42' is grown on the side of the initial heavily doped semiconductor layer 41' away from the transition layer 3.

[0112] It should be noted that the initial heavily doped semiconductor layer 41' and the initial lightly doped semiconductor layer 42' can also be formed by other processes, and specific limitations are not made here.

[0113] In some embodiments, as Figure 5 shown, before the step of forming the initial quantum well light-emitting layer 5', it may further include: sequentially forming an initial fourth undoped semiconductor layer 71', an initial first barrier layer 72', an initial first superlattice layer 73', and an initial second superlattice layer 74' on the side of the initial first semiconductor layer 4' away from the substrate structure 10.

[0114] For example, after growing the initial lightly doped semiconductor layer 42', the reaction chamber temperature is reduced to 900°C to 1000°C, and the initial fourth undoped semiconductor layer 71' is grown on the side of the initial lightly doped semiconductor layer 42' away from the initial heavily doped semiconductor layer 41'. The initial fourth undoped semiconductor layer 71' is used to repair the damage caused by hydrogen etching during the cooling process.

[0115] The growth atmosphere of the above film layers is a hydrogen atmosphere. Then, the reaction chamber temperature is reduced to 800°C to 900°C, and the atmosphere is switched to a nitrogen atmosphere. The initial first barrier layer 72' is grown on the side of the initial fourth undoped semiconductor layer 71' away from the initial lightly doped semiconductor layer 42'. Then, the initial first superlattice layer 73' is grown on the side of the initial first barrier layer 72' away from the initial fourth undoped semiconductor layer 71'. The initial second superlattice layer 74' is continuously grown on the side of the initial first superlattice layer 73' away from the initial first barrier layer 72'.

[0116] It should be noted that the initial fourth undoped semiconductor layer 71', the initial first barrier layer 72', the initial first superlattice layer 73', and the initial second superlattice layer 74' can also be formed by other processes, and specific limitations are not made here.

[0117] Then, as Figure 6As shown, an initial quantum well light-emitting layer 5' is formed on a side of the initial second superlattice layer 74' facing away from the initial first superlattice layer 73'.

[0118] In some embodiments, as Figure 7 shown, before the step of forming the initial second semiconductor layer 6', it may further include: forming an initial protective layer 75' on a side of the initial quantum well light-emitting layer 5' facing away from the initial first semiconductor layer 4', and the initial second semiconductor layer 6' is located on a side of the initial protective layer 75' facing away from the initial quantum well light-emitting layer 5'.

[0119] For example, in a nitrogen atmosphere, the initial protective layer 75' is grown on a side of the initial quantum well light-emitting layer 5' facing away from the initial first semiconductor layer 4'. The initial protective layer 75' is used to protect the initial quantum well light-emitting layer 5' when switching to a hydrogen atmosphere subsequently.

[0120] Then, as Figure 7 shown, the initial second semiconductor layer 6' is formed on a side of the initial protective layer 75' facing away from the initial quantum well light-emitting layer 5'.

[0121] In some embodiments, the initial second semiconductor layer 6' includes an initial electron blocking layer 61', an initial hole injection layer 62', and an initial ohmic contact layer 63' formed in sequence on a side of the initial quantum well light-emitting layer 5' facing away from the initial first semiconductor layer 4'.

[0122] For example, switch to a hydrogen atmosphere, and grow the initial electron blocking layer 61' on a side of the initial protective layer 75' facing away from the initial quantum well light-emitting layer 5'. Then, deposit the initial hole injection layer 62' on a side of the initial electron blocking layer 61' facing away from the initial protective layer 75'. Deposit the initial ohmic contact layer 63' on a side of the initial hole injection layer 62' facing away from the initial electron blocking layer 61'.

[0123] In some embodiments, as Figure 8 shown, after the step of forming the initial second semiconductor layer 6', it further includes: forming an initial first transparent conductive layer 76' and an initial first reflective layer 77' in sequence on a side of the initial second semiconductor layer 6' facing away from the initial quantum well light-emitting layer 5'.

[0124] For example, using an electron beam evaporation or PVD process, deposit the initial first transparent conductive layer 76' on a side of the initial ohmic contact layer 63' facing away from the initial hole injection layer 62', and combine an annealing process to improve the transmittance of the initial first transparent conductive layer 76' and reduce the material resistance. Then, using an electron beam evaporation or PVD process, deposit the initial first reflective layer 77' on a side of the initial first transparent conductive layer 76' facing away from the initial ohmic contact layer 63'.

[0125] It should be noted that the initial first transparent conductive layer 76' and the initial first reflective layer 77' can also be formed by other processes, and no specific limitation is made here.

[0126] Then, as Figure 9 shown, the initial lightly doped semiconductor layer 42', the initial fourth undoped semiconductor layer 71', the initial first barrier layer 72', the initial first superlattice layer 73', the initial second superlattice layer 74', the initial quantum well light-emitting layer 5', the initial second semiconductor layer 6', the initial first transparent conductive layer 76' and the initial first reflective layer 77' in the initial first semiconductor layer 4' are etched to correspondingly form a lightly doped semiconductor layer 42, a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, a second superlattice layer 74, a quantum well light-emitting layer 5, a second semiconductor layer 6, a first transparent conductive layer 76 and a first reflective layer 77, obtaining the initial pixel unit 20'. Among them, the initial pixel unit 20' includes a lightly doped semiconductor layer 42, a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, a second superlattice layer 74, a quantum well light-emitting layer 5, a second semiconductor layer 6, a first transparent conductive layer 76 and a first reflective layer 77 that are sequentially located on the side of the initial heavily doped semiconductor layer 41' away from the substrate structure 10. It should be noted that at this time, the initial heavily doped semiconductor layer 41' in the initial first semiconductor layer 4' is not etched, and a surface portion of the initial heavily doped semiconductor layer 41' away from the substrate structure 10 is exposed.

[0127] For example, photoresist (PR) is deposited, exposed using a yellow light process, and etched using an ICP process to form the initial pixel unit 20', and then a degluing process is performed.

[0128] Then, as Figure 10 shown, an initial passivation layer 81' is formed on the side of the first reflective layer 77 away from the first transparent conductive layer 76, and the initial passivation layer 81' covers the sidewalls of the initial pixel unit 20' and the exposed surface of the initial heavily doped semiconductor layer 41'; an initial second reflective layer 82' is formed on the surface of the initial passivation layer 81'.

[0129] For example, the sidewalls of the initial pixel unit 20' are repaired using wet etching (such as a TMAH solution), and the initial passivation layer 81' is deposited using an ALD device. Then, the initial second reflective layer 82' is deposited using PVD, electron beam evaporation or an ALD device.

[0130] For another example, the sidewalls of the initial pixel unit 20' are treated using plasma of a PE-ALD device, and the gas can include O2, Ar, H2, NH3, N2, etc., and the initial passivation layer 81' is deposited. Then, the initial second reflective layer 82' is deposited using PVD, electron beam evaporation or an ALD device.

[0131] For another example, through a photolithography process, a protective layer is deposited on the initial pixel unit 20' by a PECVD process. The protective layer may include a SiO2 layer or the like, and the thickness of the protective layer may be 10 nm to 40 nm. The sidewalls of the initial pixel unit 20' are processed by plasma using a PE-ALD device, and the gas may include O2, Ar, H2, NH3, N2, etc., to deposit an initial passivation layer 81'. Then, an initial second reflective layer 82' is deposited using a PVD, electron beam evaporation, or ALD device.

[0132] It should be noted that other processes may also be used to form the initial passivation layer 81' and the initial second reflective layer 82', and specific limitations are not made here.

[0133] Then, as Figure 11 shown, the initial second reflective layer 82', the initial passivation layer 81', and the initial heavily doped semiconductor layer 41 on the periphery of the initial pixel unit 20' are etched to correspondingly form a second reflective layer 82, a passivation layer 81, and a heavily doped semiconductor layer 41, obtaining a pixel unit 20. The pixel unit 20 may include a heavily doped semiconductor layer 41, a lightly doped semiconductor layer 42, a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, a second superlattice layer 74, a quantum well light-emitting layer 5, a second semiconductor layer 6, a first transparent conductive layer 76, and a first reflective layer 77, which are sequentially located on the side of the transition layer 3 away from the substrate 1. The passivation layer 81 is located on the side of the first reflective layer 77 away from the first transparent conductive layer 76, and the passivation layer 81 covers the sidewalls of the pixel unit 20. The second reflective layer 82 is located on the surface of the passivation layer 81.

[0134] In some embodiments, the cross-sectional area of the heavily doped semiconductor layer 41 is larger than the cross-sectional area of the lightly doped semiconductor layer 42.

[0135] Among them, the heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer, and the electron concentration of the heavily doped semiconductor layer 41 is 1×10 18 cm -3 ~2×10 19 cm -3 , and the thickness of the heavily doped semiconductor layer 41 is 1.5 μm to 2 μm.

[0136] The heavily doped semiconductor layer 41 may also include a periodically grown n-Al c Ga 1-c N / n-GaN superlattice layer, 0.05 ≤ c ≤ 0.1, and the electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 . Among them, n-Al c Ga 1-cThe Al component in N is about 5% - 10%, the thickness can be 2 nm - 3 nm, and the thickness of n-GaN can be 2.5 nm - 15 nm. The n-Al c Ga 1-c N / n-GaN superlattice layer can relieve the extension of dislocations and stress regulation.

[0137] The lightly doped semiconductor layer 42 can include an n-GaN lightly doped layer, and the electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3 , and the thickness of the lightly doped semiconductor layer 42 is 0.2 μm - 0.5 μm.

[0138] The lightly doped semiconductor layer 42 can also include an n-Al g Ga 1-g N / n-GaN superlattice layer, 0.02 ≤ g ≤ 0.08, and the electron concentration can be 1×10 17 cm -3 ~5×10 17 cm -3 . Among them, the Al component in n-Al g Ga 1-g N is about 2% - 8%, the thickness can be 2 nm - 3 nm, and the thickness of n-GaN can be 2.5 nm - 15 nm.

[0139] In some embodiments, the cross-sectional areas of the fourth undoped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 gradually decrease. Additionally, the cross-sectional area of the fourth undoped semiconductor layer 71 is smaller than the cross-sectional area of the lightly doped semiconductor layer 42.

[0140] Among them, the fourth undoped semiconductor layer 71 can include a u-GaN layer, and the thickness of the fourth undoped semiconductor layer 71 can be 10 nm - 30 nm. The first barrier layer 72 can include a GaN layer, and the thickness of the first barrier layer 72 can be 10 nm - 30 nm. The first superlattice layer 73 can include at least one period (such as 1 - 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01 ≤ a ≤ 0.05. Among them, the thickness of u-In a Ga 1-a N can be 2 nm - 3 nm, the In component is 1% - 5%, and the thickness of u-GaN can be 2.5 nm - 15 nm. The second superlattice layer 74 can include at least one period (such as 1 - 3 periods) of u-In b Ga 1-bN / n-GaN superlattice layer, 0.05 ≤ b ≤ 0.08. Among them, the electron concentration of n-GaN can be 1×10 17 cm -3 ~5×10 17 cm -3 , u-In b Ga 1-b N has a thickness that can be 2 nm to 3 nm, the In composition can be 5% to 8%, and the thickness of n-GaN can be 2.5 nm to 15 nm.

[0141] In some embodiments, the cross-sectional area of the quantum well light-emitting layer 5 is smaller than the cross-sectional area of the second superlattice layer 74.

[0142] In some embodiments, the quantum well light-emitting layer 5 includes at least one of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer, and a red light quantum well light-emitting layer.

[0143] In some embodiments, the blue light quantum well light-emitting layer includes a third undoped semiconductor layer, a first potential well layer, a fourth undoped semiconductor layer, and a second potential barrier layer that are sequentially disposed between the second superlattice layer 74 and the second semiconductor layer 6.

[0144] Among them, both the third undoped semiconductor layer and the fourth undoped semiconductor layer can include a u-GaN layer, and the thicknesses of both the third undoped semiconductor layer and the fourth undoped semiconductor layer can be 2 nm to 3 nm. The first potential well layer can include a u-In j Ga 1-j N layer, 0.15 ≤ j ≤ 0.2, and the thickness of the first potential well layer can be 2.5 nm to 3.5 nm. The second potential barrier layer can include a u-In k Ga 1-k N layer, 0.01 ≤ k ≤ 0.02, and the thickness of the second potential barrier layer can be 10 nm to 15 nm.

[0145] In some embodiments, the green light quantum well light-emitting layer can include a fifth undoped semiconductor layer, a second potential well layer, a sixth undoped semiconductor layer, a third potential barrier layer, a seventh undoped semiconductor layer, a third potential well layer, an eighth undoped semiconductor layer, and a fourth potential barrier layer that are sequentially disposed between the second superlattice layer 74 and the second semiconductor layer 6.

[0146] In some embodiments, the green light quantum well light-emitting layer includes at least one first periodic structure (such as 1 to 2 first periodic structures) and at least one second periodic structure (such as 2 to 3 first periodic structures). The first periodic structure can include a fifth undoped semiconductor layer, a second potential well layer, a sixth undoped semiconductor layer, and a third potential barrier layer, and the second periodic structure can include a seventh undoped semiconductor layer, a third potential well layer, an eighth undoped semiconductor layer, and a fourth potential barrier layer.

[0147] Among them, the fifth to eighth undoped semiconductor layers may all include u-GaN layers, and the thicknesses of the fifth to eighth undoped semiconductor layers may all be 2 nm to 3 nm. The second quantum well layer includes u-In m Ga 1-m N layer, 0.22 ≤ m ≤ 0.25, and the thickness of the second quantum well layer may be 2.5 nm to 3.5 nm. The third barrier layer may include an n-GaN layer, and the electron concentration may be 1×10 17 cm -3 ~5×10 17 cm -3 , and the thickness of the third barrier layer may be 10 nm to 15 nm. The third quantum well layer may include u-In p Ga 1-p N layer, 0.25 ≤ p ≤ 0.28, and the thickness of the third quantum well layer may be 2.5 nm to 3.5 nm. The fourth barrier layer includes an n-GaN layer, and the electron concentration may be 1×10 17 cm -3 ~5×10 17 cm -3 , and the thickness of the fourth barrier layer may be 10 nm to 15 nm. It should be noted that the growth mode in the green light quantum well light-emitting layer can effectively alleviate the wavelength shift problem under high current injection.

[0148] In some embodiments, the red light quantum well light-emitting layer includes at least one third periodic structure (such as 2 to 3 periodic structures), and each third periodic structure includes a ninth undoped semiconductor layer, a fourth quantum well layer, a first capping layer, a fifth barrier layer, a tenth undoped semiconductor layer, a fifth quantum well layer, a second capping layer, and a sixth barrier layer that are sequentially arranged between the second superlattice layer 74 and the second semiconductor layer 6.

[0149] Among them, the ninth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the ninth undoped semiconductor layer may be 2 nm to 3 nm. The fourth quantum well layer may include u-In x Ga 1-x N layer, 0.1 ≤ x ≤ 0.15, and the thickness of the fourth quantum well layer may be 2.5 nm to 3.5 nm. The first capping layer may include a GaN layer, and the thickness of the first capping layer may be 2 nm to 3 nm. The fifth barrier layer may include a GaN layer or u-In y Ga 1-y N layer, 0.01 ≤ y ≤ 0.03, and the thickness of the fifth barrier layer may be 10 nm to 15 nm. The tenth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the tenth undoped semiconductor layer may be 2 nm to 3 nm. The fifth quantum well layer may include u-In z Ga1-z N layer, 0.35 ≤ z ≤ 0.4, the thickness of the fifth potential well layer can be 2.5 nm to 3.5 nm. The second capping layer can include a GaN layer, and the thickness of the second capping layer can be 2 nm to 3 nm. The sixth barrier layer can include u-Al d Ga 1-d N layer, 0.3 ≤ d ≤ 0.35, the thickness of the sixth barrier layer can be 10 nm to 15 nm.

[0150] In some embodiments, the cross-sectional area of the protective layer 75 is smaller than the cross-sectional area of the quantum well light-emitting layer 5.

[0151] Among them, the protective layer 75 can include a u-GaN layer, and the thickness of the protective layer 75 can be 20 nm to 50 nm.

[0152] In some embodiments, the cross-sectional areas of the electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 gradually decrease. Additionally, the cross-sectional area of the electron blocking layer 61 is smaller than the cross-sectional area of the protective layer 75.

[0153] Among them, the electron blocking layer 61 can include a p-AlGaN polarization-induced layer, the thickness of the p-AlGaN polarization-induced layer can be 50 nm to 60 nm, and the Al component can linearly decrease from 30% to 0. The theoretical calculated hole concentration in the film layer is 2.5×10 18 cm -3 . It should be noted that the electron blocking layer 61 is usually made of p-AlGaN material, but in this material system, the activation energy of doping Mg is relatively high, and it is difficult to achieve a high hole concentration and a low resistivity. Therefore, the electron blocking layer 61 in this embodiment adopts a p-AlGaN polarization-induced layer, which can reduce the differential resistance of the device.

[0154] The electron blocking layer 61 can also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.1 ≤ e ≤ 0.3, the Al component in p-Al e Ga 1-e N is about 10% to 30%, the thickness of p-Al e Ga 1-e N can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm.

[0155] The hole injection layer 62 can include a p-GaN layer, and the thickness of the hole injection layer 62 can be 80 nm to 200 nm. The hole injection layer 62 can also include p-Al h Ga 1-h N / p-GaN superlattice layer, 0.15 ≤ h ≤ 0.25, and the hole concentration can be 1.5×10 18 cm-3 ~2.5×10 18 cm -3 . Among them, the Al component in p-Al h Ga 1-h N is about 15% - 25%, and the thickness of p-Al h Ga 1-h N can be 2 nm - 3 nm, and the thickness of p-GaN can be 2.5 nm - 15 nm.

[0156] The ohmic contact layer 63 can include at least one period (such as 4 - 6 periods) of p-In f Ga 1-f N / p-GaN superlattice layer, 0.1 ≤ f ≤ 0.2. Among them, the In component in p-In f Ga 1-f N is about 10% - 20%, and the thickness of p-In f Ga 1-f N can be 2 nm - 3 nm, and the thickness of p-GaN can be 2.5 nm - 15 nm.

[0157] In some embodiments, the cross-sectional areas of the first transparent conductive layer 76 and the first reflective layer 77 gradually decrease. Additionally, the cross-sectional area of the first transparent conductive layer 76 is smaller than that of the ohmic contact layer 63. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip.

[0158] Among them, the first transparent conductive layer 76 can include an ITO (indium tin oxide) layer, and the thickness of the first transparent conductive layer 76 can be 50 nm - 200 nm. The first reflective layer 77 can include a metal reflective layer, such as including at least one of Ag and Al, etc., and the thickness of the first reflective layer 77 can be 100 nm - 300 nm.

[0159] In some embodiments, the passivation layer 81 can include at least one of SiO2, SiN x and Al2O3, and the thickness of the passivation layer 81 can be 10 nm - 40 nm. The second reflective layer 82 can further enhance the light extraction efficiency of the chip. The second reflective layer 82 can include a DBR (Distributed Bragg Reflection) layer, and the DBR layer can include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0160] In some embodiments, such as Figure 11As shown, after the step of forming the pixel unit, it further includes: forming an isolation layer 83 on the peripheral side of the pixel unit 20. The isolation layer 83 covers the substrate structure 10, and the surface of the isolation layer 83 facing away from the substrate structure 10 is flush with the surface of the second reflective layer 82 facing away from the substrate structure 10. Among them, the isolation layer 83 may include at least one of SiO2 and SiNx.

[0161] For example, use a PECVD device to deposit the isolation layer 83 on the peripheral side of the pixel unit 20. It should be noted that the isolation layer 83 can also be formed by other processes, and no specific limitation is made here.

[0162] In some embodiments, as Figure 12 As shown, the manufacturing method of the display chip further includes: forming a groove in the isolation layer 83 and forming a third reflective layer 85 in the groove. The third reflective layer 85 is located on the peripheral side of the pixel unit 20. The third reflective layer 85 can reduce the light crosstalk and the light extraction divergence angle between pixels, and improve the light extraction efficiency.

[0163] Among them, the third reflective layer 85 may include a metal layer, such as including at least one of Ag and Al, etc.

[0164] For example, deposit photoresist, and successively use the exposure process and the etching process to etch a groove in the isolation layer 83. Then, use electron beam evaporation or PVD process to deposit the third reflective layer 85 in the groove. Finally, use an acetone solution to remove the photoresist and the third reflective layer 85 on the photoresist.

[0165] It should be noted that the third reflective layer 85 can also be formed by other processes, and no specific limitation is made here.

[0166] In some embodiments, after the step of forming the pixel unit, the manufacturing method of the display chip further includes:

[0167] Bonding the side of the pixel unit facing away from the substrate structure to the substrate.

[0168] In some embodiments, the step of bonding the side of the pixel unit facing away from the substrate structure to the substrate includes: forming a dielectric layer on the side of the first reflective layer facing away from the first transparent conductive layer; forming a first bonding structure penetrating the dielectric layer and connected to the first reflective layer; bonding the pixel unit to the substrate through the first bonding structure.

[0169] As Figure 13As shown, a passivation layer 81 and a second reflective layer 82 are provided on the side of the first reflective layer 77 facing away from the first transparent conductive layer 76, and a dielectric layer (i.e., the first dielectric layer 84) is formed on the side of the second reflective layer 82 facing away from the substrate structure 10 and on the side of the isolation layer 83 facing away from the substrate structure 10. Then, a first bonding structure 30 is formed that penetrates the first dielectric layer 84, the second reflective layer 82, and the passivation layer 81 and is connected to the first reflective layer 77.

[0170] Among them, the first dielectric layer 84 may include at least one of SiO2 and SiN, and the thickness of the first dielectric layer 84 may be 100 nm to 200 nm. x

[0171] In some embodiments, the first bonding structure 30 may include a bonding layer (i.e., the first bonding layer 86) and a bonding protection layer (i.e., the first bonding protection layer 87). The step of forming the first bonding structure that penetrates the dielectric layer and is connected to the first reflective layer includes: forming an opening that penetrates the dielectric layer; forming a bonding protection layer on the sidewalls of the opening; and forming a bonding layer in the opening that is connected to the first reflective layer.

[0172] As Figure 13 shown, an opening 85 is formed that penetrates the first dielectric layer 84, the second reflective layer 82, and the passivation layer 81. As Figure 14 shown, first, a first bonding protection layer 87 is formed on the sidewalls of the opening 80, and then the first bonding layer 86 is filled in the second groove 80.

[0173] Among them, the first bonding protection layer 87 may include a TiN layer, and the first bonding layer 86 may include a metal layer, such as Ni / Au, Pt / Au, or Cu, etc.

[0174] For example, the first dielectric layer 84 is deposited using a PECVD device, and then a photoresist is deposited. An exposure process and an etching process are used to etch and form the opening 80 to expose the first reflective layer 77. Then, a photoresist is deposited, and a physical and chemical vapor deposition process is used to deposit the first bonding protection layer 87 on the sidewalls of the opening 80, and the photoresist is removed. Then, an electron beam evaporation or PVD process is used to deposit the first bonding layer 86 in the opening 80, and a CMP (Chemical Mechanical Polishing) process is performed to make the surface of the first bonding structure 30 on the side facing away from the substrate structure 10 flush with the surface of the first dielectric layer 84 on the side facing away from the substrate structure 10.

[0175] It should be noted that the first dielectric layer 84 and the first bonding structure 30 may also be formed using other processes, and specific limitations are not made here.

[0176] As Figure 15As shown, the substrate 100 is located on the side of the first dielectric layer 84 facing away from the first semiconductor layer 4, and the pixel unit 20 is bonded to the substrate 100 through the first bonding structure 30. Among them, the substrate 100 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0177] In some embodiments, the substrate 100 may include a second dielectric layer 91 and a second bonding structure 50 penetrating the second dielectric layer 91. The second bonding structure 50 is bonded to the first bonding structure 30, that is, the pixel unit 20 is bonded to the substrate 100 through the first bonding structure 30 and the second bonding structure 50.

[0178] In some embodiments, the second bonding structure 50 includes a second bonding layer 92 and a second bonding protection layer 93 disposed around the second bonding layer 92. Among them, the second bonding protection layer 93 may include a TiN layer, and the second bonding layer 92 may include a metal layer, such as Ni / Au, Pt / Au, or Cu, etc.

[0179] In this embodiment, by setting the first bonding structure 30 and the second bonding structure 50, the bonding accuracy between the pixel unit 20 and the substrate 100 is improved.

[0180] Step 130: Remove the substrate structure.

[0181] The substrate structure 10 includes a substrate 1 and a two-dimensional material layer 2. Removing the substrate structure in step 130 includes: removing the substrate 1; removing the two-dimensional material layer 2.

[0182] For example, when the substrate 1 is a Si substrate, the substrate 1 is removed by a wet etching method. When the substrate 1 is an n-SiC substrate, the substrate 1 is removed by a wet etching method, grinding, or ICP-RIE etching. When the substrate 1 is an n-GaN homo-substrate, the substrate 1 is removed by grinding or ICP-RIE etching.

[0183] In this embodiment, a two-dimensional material layer is provided on one side of the substrate, and the weak van der Waals force between layers is used to reduce the stress between the chip structure and the substrate, and the two-dimensional material pattern layer corresponds to the position of the pixel unit, so as to reduce the risk of damage to the pixel unit when the substrate is peeled off and improve the light-emitting performance of the display chip.

[0184] In some embodiments, removing the substrate in step 130 includes: forming a grid protection layer on the side of the substrate facing away from the pixel unit, and the grid protection layer corresponds to the position of the pixel unit; removing the substrate and simultaneously removing the grid protection layer.

[0185] Such as Figure 16As shown, when the substrate 1 is a sapphire substrate, a grid protection layer 12 is first formed on the side of the substrate 1 facing away from the pixel unit 20. The grid protection layer 12 corresponds to the position of the pixel unit 20, that is, the grid protection layer 12 corresponds to the position of the two-dimensional material layer 2, and the grid protection layer 12 is not provided in other areas, that is, the other areas expose the substrate 1. Then, the substrate 1 is removed. When the substrate 1 is removed, the grid protection layer 12 is removed together.

[0186] In some embodiments, the step of removing the substrate includes: removing the substrate by using a laser lift-off technique.

[0187] As Figure 17 shown, the substrate 1 is removed by using a laser lift-off technique. Among them, the selected pulsed laser wavelength can be 355 nm, 266 nm, and 248 nm. The setting of the grid protection layer 12 can avoid the damage of the laser lift-off technique to the quantum wells in the pixel unit 20, and the setting of the two-dimensional material layer 2 can achieve a better lift-off effect (the weak bonding characteristics between two-dimensional material layers). When the substrate 1 is removed, the grid protection layer 12 is removed.

[0188] Then, the two-dimensional material layer 2 is removed to expose the heavily doped semiconductor layer 41, as Figure 17 shown.

[0189] In some embodiments, the substrate structure 10 further includes a transition layer 3 located on the side of the two-dimensional material layer 2 facing away from the substrate 1 and covering the substrate 1, and the pixel unit 20 is located on the side of the transition layer 3 facing away from the substrate 1. The step of removing the two-dimensional material layer includes: removing the transition layer and removing the two-dimensional material layer at the same time.

[0190] For example, the ICP-RIE (inductively coupled plasma-reactive ion etching) process is used to etch the transition layer 3 until the heavily doped semiconductor layer 41 is exposed. When the transition layer 3 is removed, the two-dimensional material layer 2 is removed. In some embodiments, after the step of removing the substrate structure, it further includes: forming a second transparent conductive layer on the side of the pixel unit facing away from the substrate; forming a microlens on the side of the second transparent conductive layer facing away from the substrate.

[0191] As Figure 18 shown, a second transparent conductive layer 88 is formed on the side of the heavily doped semiconductor layer 41 facing away from the lightly doped semiconductor layer 42. Among them, the second transparent conductive layer 88 may include an ITO layer, and the thickness of the second transparent conductive layer 88 may be 100 nm to 400 nm.

[0192] For example, a dry etching or wet etching process is used to roughen the surface of the heavily doped semiconductor layer 41. Then, the second transparent conductive layer 88 is deposited by using an electron beam evaporation or PVD process, and an annealing process is combined to improve the transmittance of the second transparent conductive layer 88 and reduce the material resistance.

[0193] It should be noted that the second transparent conductive layer 88 can also be formed by other processes, and no specific limitation is made here.

[0194] Then, a microlens 89 (micro-lens) is formed on the side of the second transparent conductive layer 88 facing away from the substrate 100. The microlens 89 corresponds to the position of the pixel unit 20. The microlens 89 is used to increase the light collection of the chip. The microlens 85 includes SiO2, etc.

[0195] For example, the microlens 87 is deposited by using a PECVD device. It should be noted that the microlens 87 can also be formed by other processes, and no specific limitation is made here.

[0196] In a display chip, the laser lift-off technology (LLO) is usually used to separate the chip structure from the substrate. However, the instant high energy (interface high temperature) of the laser is likely to cause damage to the quantum well structure of the device, and In in the quantum well layer is likely to precipitate, resulting in blue shift of the wavelength and reduction of the chip brightness at the same time.

[0197] If a patterned substrate (PSS) is used to prepare a display chip, the cost is relatively high. Moreover, after the chip is miniaturized (<10 μm), the yield of separating the chip structure on the substrate (such as a sapphire substrate) side by the LLO process is relatively low. At the same time, the substrate generates relatively large stress in the nitride epitaxial layer, resulting in defects or even cracks in the chip structure and affecting the fabrication of subsequent devices.

[0198] In this embodiment, a two-dimensional material layer is arranged between the substrate and the chip structure. The two-dimensional material is a layered material with a single-atom or single-molecule thickness, that is, the atoms within the layer are covalently bonded, and the layers are bonded together by weak van der Waals forces. This weak bonding characteristic between the layers can reduce the stress generated by lattice mismatch and coefficient of thermal expansion mismatch, improve the material quality, and is easy to realize the interlayer separation of the two-dimensional material, so as to realize the high-quality epitaxy and transfer of nitrides and reduce the dependence of nitride devices on the substrate.

[0199] Based on the easy peelability and good stress regulation of the two-dimensional material, a two-dimensional material layer is formed on the substrate in this embodiment. By regulating the film-forming process parameters, the growth of both gallium-polarity and nitrogen-polarity display chips can be realized simultaneously. In the subsequent peeling process, the pixel unit corresponds to the two-dimensional material layer. On the one hand, the damage to the quantum well by the LLO process can be avoided, achieving a better peeling effect. On the other hand, the stress can be regulated, and the light-emitting performance of the display chip can be improved to a certain extent.

[0200] In addition, in order to improve the light extraction efficiency of the display chip, current related technologies include patterned substrate (PSS) technology, surface roughening technology, plasmon and photonic crystal technology, etc. However, the PSS technology has high requirements for the substrate process. Since sapphire substrates are relatively hard, it is difficult to ensure the consistency and uniformity of the patterns, resulting in high costs. The plasmon and photonic crystal technologies have relatively complex processes, increasing the complexity of the manufacturing process.

[0201] In this embodiment, the geometric profile of the pixel unit is reshaped so that the cross-sectional area of the pixel unit gradually increases in the direction towards the substrate, thereby reducing the light emission divergence angle of the display chip, improving the light extraction efficiency of the display chip, and further improving the light efficiency of the display chip, while avoiding cost increase and complexity increase of the process.

[0202] Correspondingly, the embodiment of the present application further provides a substrate structure that can be applied to the manufacturing method of the above display chip.

[0203] As Figure 19 shown, the substrate structure 10 may include a substrate 1 and a two-dimensional material layer 2. Among them, the two-dimensional material layer 2 is located on one side of the substrate 1, and the two-dimensional material layer 2 does not completely cover one side of the substrate 1.

[0204] In some embodiments, the two-dimensional material layer 2 corresponds to the position of the pixel unit in the display chip.

[0205] In some embodiments, the substrate 1 includes a substrate pattern layer 11 on the side of the substrate 1 close to the two-dimensional material layer 2, and the substrate pattern layer 11 and the two-dimensional material layer 2 form a two-dimensional material structure 21.

[0206] In some embodiments, the shape of the two-dimensional material structure 21 includes at least one of a cylindrical shape, a hemispherical shape, a conical shape, a polyhedral shape, etc.

[0207] Among them, the two-dimensional material layer 2 may include at least one of graphene, hexagonal boron nitride, molybdenum disulfide, etc., and the thickness of the two-dimensional material layer 2 may be 1 nm to 30 nm. The substrate 1 may include a c-plane sapphire substrate, an Si substrate, an n-SiC substrate, an n-GaN homo-substrate, etc.

[0208] When the substrate 1 includes an n-GaN homo-substrate, the substrate structure 10 may only include the substrate 1 and the two-dimensional material layer 2.

[0209] In some embodiments, the substrate structure 10 further includes a transition layer 3, and the transition layer 3 is located on the side of the two-dimensional material layer 2 facing away from the substrate 1 and covers the substrate 1.

[0210] When the substrate 1 includes an n-SiC substrate, the transition layer 3 may include an n-AlGaN layer.

[0211] In some embodiments, the transition layer 3 may include a buffer layer and a first undoped semiconductor layer. The buffer layer is located on the side of the two-dimensional material layer 2 facing away from the substrate 1 and covers the substrate 1, and the first undoped semiconductor layer is located on the side of the buffer layer facing away from the substrate 1.

[0212] When the substrate 1 includes a c-plane sapphire substrate, the buffer layer may include an AlN buffer layer, and the first undoped semiconductor layer may include a u-GaN layer.

[0213] In some embodiments, the transition layer 3 may further include a graded buffer layer located between the buffer layer and the first undoped semiconductor layer.

[0214] When the substrate 1 includes a Si substrate or an n-SiC substrate, the buffer layer may include an AlN buffer layer, the graded buffer layer may include a graded AlGaN layer, and the first undoped semiconductor layer may include a u-GaN layer.

[0215] According to the substrate structure 10 of the present application, a two-dimensional material layer 2 is disposed on one side of the substrate 1, and the weak van der Waals force between the layers is used to reduce the stress between the pixel unit on one side of the substrate structure 10 and the substrate 1, and the two-dimensional material layer corresponds to the position of the pixel unit, so as to reduce the risk of damage to the pixel unit when the substrate is peeled off and improve the light-emitting performance of the display chip.

[0216] Correspondingly, an embodiment of the present application further provides a display chip, which can be formed by using the manufacturing method of the above display chip. Among them, the display chip may be a Micro-LED display chip.

[0217] As Figure 18 shown, the display chip includes a pixel unit 20, and the pixel unit 20 includes a first semiconductor layer 4, a quantum well light-emitting layer 5, and a second semiconductor layer 6. The quantum well light-emitting layer 5 is located on one side of the first semiconductor layer 4, and the second semiconductor layer 6 is located on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4.

[0218] One of the first semiconductor layer 4 and the second semiconductor layer 6 is an n-type semiconductor layer, and the other is a p-type semiconductor layer, that is, the first semiconductor layer 4 is an n-type semiconductor layer and the second semiconductor layer 6 is a p-type semiconductor layer; or, the first semiconductor layer 4 is a p-type semiconductor layer and the second semiconductor layer 6 is an n-type semiconductor layer.

[0219] In some embodiments, in the direction A in which the second semiconductor layer 6 points to the first semiconductor layer 4, the cross-sectional area of the pixel unit 20 gradually increases, that is, the cross-sectional area of the first semiconductor layer 4 is larger than the cross-sectional area of the quantum well light-emitting layer 5, and the cross-sectional area of the quantum well light-emitting layer 5 is larger than the cross-sectional area of the second semiconductor layer 6.

[0220] In this embodiment, the cross-sectional area of the pixel unit gradually increases in the direction A from the second semiconductor layer 6 to the first semiconductor layer 4, so as to reduce the light-emitting divergence angle of the display chip, improve the light extraction efficiency of the display chip, and further improve the light efficiency of the display chip.

[0221] In some embodiments, the longitudinal section of the pixel unit 20 is an isosceles trapezoid.

[0222] In some embodiments, the pixel unit 20 further includes a first transparent conductive layer 76 and a first reflective layer 77 that are sequentially disposed on the side of the second semiconductor layer 6 away from the quantum well light-emitting layer 5, that is, the first transparent conductive layer 76 is located on the side of the second semiconductor layer 6 away from the quantum well light-emitting layer 5, and the first reflective layer 77 is located on the side of the first transparent conductive layer 76 away from the second semiconductor layer 6. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip.

[0223] In some embodiments, the cross-sectional area of the first transparent conductive layer 76 is larger than the cross-sectional area of the first reflective layer 77, and the cross-sectional area of the second semiconductor layer 6 is larger than the cross-sectional area of the first transparent conductive layer 76.

[0224] Among them, the first transparent conductive layer 76 may include an ITO (indium tin oxide) layer, and the thickness of the first transparent conductive layer 76 may be 50 nm to 200 nm. The first reflective layer 77 may include a metal reflective layer, such as at least one of Ag and Al, etc., and the thickness of the first reflective layer 77 may be 100 nm to 300 nm.

[0225] In some embodiments, the display chip further includes a first dielectric layer 84 and a first bonding structure 30. The first dielectric layer 84 is located on the side of the first reflective layer 77 away from the first transparent conductive layer 76, and the first bonding structure 30 penetrates the first dielectric layer 84 and is connected to the first reflective layer 77.

[0226] Among them, the first dielectric layer 84 may include at least one of SiO2 and SiN x and the thickness of the first dielectric layer 84 may be 100 nm to 200 nm.

[0227] In some embodiments, the first bonding structure 30 includes a first bonding layer 86 and a first bonding protective layer 87. The first bonding layer 86 penetrates the first dielectric layer 84 and is connected to the first reflective layer 77, and the first bonding protective layer 87 is disposed around the first bonding layer 86.

[0228] Among them, the first bonding protective layer 87 may include a TiN layer, and the first bonding layer 86 may include a metal layer, such as Ni / Au, Pt / Au, or Cu, etc.

[0229] In this embodiment, by providing the first bonding structure 30, the bonding accuracy between the pixel unit 20 and other substrates is improved.

[0230] In some embodiments, the chip structure 200 further includes a passivation layer 81 and a second reflective layer 82. The passivation layer 81 is located between the first reflective layer 77 and the first dielectric layer 84 and covers the sidewalls of the pixel unit 20. The second reflective layer 82 is located between the passivation layer 81 and the first dielectric layer 84 and covers the passivation layer 81, that is, the second reflective layer 82 is located on the surface of the passivation layer 81. The second reflective layer 82 can further enhance the light extraction efficiency of the chip.

[0231] Among them, the passivation layer 81 may include at least one of SiO2, SiN x and Al2O3. The thickness of the passivation layer 81 can be 10 nm to 40 nm. The second reflective layer 82 may include a DBR (Distributed Bragg Reflection) layer, and the DBR layer may include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0232] In some embodiments, the pixel unit 20 further includes a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74. The fourth undoped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are sequentially disposed between the first semiconductor layer 4 and the quantum well light-emitting layer 5.

[0233] The cross-sectional areas of the fourth undoped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 gradually decrease. Moreover, the cross-sectional area of the fourth undoped semiconductor layer 71 is smaller than the cross-sectional area of the first semiconductor layer 4, and the cross-sectional area of the second superlattice layer 74 is larger than the cross-sectional area of the quantum well light-emitting layer 5.

[0234] Among them, the fourth undoped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth undoped semiconductor layer 71 can be 10 nm to 30 nm. The first barrier layer 72 may include a GaN layer, and the thickness of the first barrier layer 72 can be 10 nm to 30 nm. The first superlattice layer 73 may include at least one period (such as 1 to 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01 ≤ a ≤ 0.05. Among them, the thickness of u-In a Ga 1-a N can be 2 nm to 3 nm, the In component is 1% to 5%, and the thickness of u-GaN can be 2.5 nm to 15 nm. The second superlattice layer 74 may include at least one period (such as 1 to 3 periods) of u-In b Ga 1-b N / n-GaN superlattice layer, 0.05 ≤ b ≤ 0.08. Among them, the electron concentration of n-GaN can be 1×1017 cm -3 ~5×10 17 cm -3 ,u-In b Ga 1-b The thickness of u-InGaN can be 2 nm to 3 nm, the In component can be 5% to 8%, and the thickness of n-GaN can be 2.5 nm to 15 nm.

[0235] In some embodiments, the first semiconductor layer 4 includes a heavily doped semiconductor layer 41 and a lightly doped semiconductor layer 42. The heavily doped semiconductor layer 41 is located on the side of the undoped semiconductor layer 3 away from the buffer layer 2, the lightly doped semiconductor layer 42 is located between the heavily doped semiconductor layer 41 and the quantum well light-emitting layer 5, and the lightly doped semiconductor layer 42 is located between the heavily doped semiconductor layer 41 and the fourth undoped semiconductor layer 71. The cross-sectional area of the heavily doped semiconductor layer 41 is larger than that of the lightly doped semiconductor layer 42. Moreover, the cross-sectional area of the lightly doped semiconductor layer 42 is larger than that of the fourth undoped semiconductor layer 71.

[0236] The heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer, and the electron concentration of the heavily doped semiconductor layer 41 is 1×10 18 cm -3 ~2×10 19 cm -3 , and the thickness of the heavily doped semiconductor layer 41 is 1.5 μm to 2 μm.

[0237] The heavily doped semiconductor layer 41 may also include an n-Al c Ga 1-c N / n-GaN superlattice layer, 0.05 ≤ c ≤ 0.1, and the electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 . Among them, the Al component in n-Al c Ga 1-c N is about 5% to 10%, the thickness can be 2 nm to 3 nm, and the thickness of n-GaN can be 2.5 nm to 15 nm. Using the n-Al c Ga 1-c N / n-GaN superlattice layer can alleviate the extension of dislocations and stress regulation.

[0238] The lightly doped semiconductor layer 42 may include an n-GaN lightly doped layer, and the electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3 , and the thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0239] The lightly doped semiconductor layer 42 may also include n-Al g Ga 1-g GaN superlattice layer, 0.02 ≤ g ≤ 0.08, and the electron concentration may be 1×10 17 cm -3 ~5×10 17 cm -3 . Among them, the Al component in n-Al g Ga 1-g N is about 2% - 8%, the thickness may be 2nm - 3nm, and the thickness of n-GaN may be 2.5nm - 15nm.

[0240] In some embodiments, the quantum well light-emitting layer 5 includes at least one of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer, and a red light quantum well light-emitting layer.

[0241] In some embodiments, the blue light quantum well light-emitting layer includes a third undoped semiconductor layer, a first potential well layer, a fourth undoped semiconductor layer, and a second potential barrier layer that are sequentially disposed between the first semiconductor layer 4 and the second semiconductor layer 6 (such as between the second superlattice layer 74 and the second semiconductor layer 6).

[0242] Among them, both the third undoped semiconductor layer and the fourth undoped semiconductor layer may include a u-GaN layer, and the thicknesses of both the third undoped semiconductor layer and the fourth undoped semiconductor layer may be 2nm - 3nm. The first potential well layer may include a u-In j Ga 1-j N layer, 0.15 ≤ j ≤ 0.2, and the thickness of the first potential well layer may be 2.5nm - 3.5nm. The second potential barrier layer may include a u-In k Ga 1-k N layer, 0.01 ≤ k ≤ 0.02, and the thickness of the second potential barrier layer may be 10nm - 15nm.

[0243] In some embodiments, the green light quantum well light-emitting layer may include a fifth undoped semiconductor layer, a second potential well layer, a sixth undoped semiconductor layer, a third potential barrier layer, a seventh undoped semiconductor layer, a third potential well layer, an eighth undoped semiconductor layer, and a fourth potential barrier layer that are sequentially disposed between the first semiconductor layer 4 and the second semiconductor layer 6 (such as between the second superlattice layer 74 and the second semiconductor layer 6).

[0244] In some embodiments, the green light quantum well light-emitting layer includes at least one first periodic structure (such as 1 to 2 first periodic structures) and at least one second periodic structure (such as 2 to 3 first periodic structures). The first periodic structure may include a fifth undoped semiconductor layer, a second quantum well layer, a sixth undoped semiconductor layer, and a third barrier layer, and the second periodic structure may include a seventh undoped semiconductor layer, a third quantum well layer, an eighth undoped semiconductor layer, and a fourth barrier layer.

[0245] Among them, the fifth to eighth undoped semiconductor layers may all include u-GaN layers, and the thicknesses of the fifth to eighth undoped semiconductor layers may all be 2 nm to 3 nm. The second quantum well layer includes a u-In m Ga 1-m N layer, 0.22 ≤ m ≤ 0.25, and the thickness of the second quantum well layer may be 2.5 nm to 3.5 nm. The third barrier layer may include an n-GaN layer, and the electron concentration may be 1×10 17 cm -3 ~5×10 17 cm -3 ,and the thickness of the third barrier layer may be 10 nm to 15 nm. The third quantum well layer may include a u-In p Ga 1-p N layer, 0.25 ≤ p ≤ 0.28, and the thickness of the third quantum well layer may be 2.5 nm to 3.5 nm. The fourth barrier layer includes an n-GaN layer, and the electron concentration may be 1×10 17 cm -3 ~5×10 17 cm -3 ,and the thickness of the fourth barrier layer may be 10 nm to 15 nm. It should be noted that the growth mode in the green light quantum well light-emitting layer can effectively alleviate the problem of wavelength shift under high current injection.

[0246] In some embodiments, the red light quantum well light-emitting layer includes at least one third periodic structure (such as 2 to 3 periodic structures), and each third periodic structure includes a ninth undoped semiconductor layer, a fourth quantum well layer, a first capping layer, a fifth barrier layer, a tenth undoped semiconductor layer, a fifth quantum well layer, a second capping layer, and a sixth barrier layer that are sequentially arranged between the first semiconductor layer 4 and the second semiconductor layer 6 (such as between the second superlattice layer 74 and the second semiconductor layer 6).

[0247] Among them, the ninth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the ninth undoped semiconductor layer may be 2 nm to 3 nm. The fourth quantum well layer may include a u-In x Ga 1-xN layer, 0.1 ≤ x ≤ 0.15, the thickness of the fourth potential well layer can be 2.5 nm to 3.5 nm. The first capping layer can include a GaN layer, and the thickness of the first capping layer can be 2 nm to 3 nm. The fifth barrier layer can include a GaN layer or u-In y Ga 1-y N layer, 0.01 ≤ y ≤ 0.03, the thickness of the fifth barrier layer can be 10 nm to 15 nm. The tenth undoped semiconductor layer can include a low-temperature u-GaN layer, and the thickness of the tenth undoped semiconductor layer can be 2 nm to 3 nm. The fifth potential well layer can include u-In z Ga 1-z N layer, 0.35 ≤ z ≤ 0.4, the thickness of the fifth potential well layer can be 2.5 nm to 3.5 nm. The second capping layer can include a GaN layer, and the thickness of the second capping layer can be 2 nm to 3 nm. The sixth barrier layer can include u-Al d Ga 1-d N layer, 0.3 ≤ d ≤ 0.35, the thickness of the sixth barrier layer can be 10 nm to 15 nm.

[0248] In some embodiments, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62, and an ohmic contact layer 63 that are sequentially disposed on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4. That is, the electron blocking layer 61 is located on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4, the hole injection layer 62 is located on the side of the electron blocking layer 61 facing away from the quantum well light-emitting layer, and the ohmic contact layer 63 is located on the side of the hole injection layer 62 facing away from the electron blocking layer 61. The cross-sectional areas of the electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 gradually decrease. Moreover, the cross-sectional area of the electron blocking layer 61 is smaller than the cross-sectional area of the quantum well light-emitting layer 5.

[0249] Among them, the electron blocking layer 61 can include a p-AlGaN polarization-induced layer, and the thickness of the p-AlGaN polarization-induced layer can be 50 nm to 60 nm. The Al component can linearly decrease from 30% to 0, and the theoretical calculated hole concentration of the film layer is 2.5×10 18 cm -3 . It should be noted that the electron blocking layer 61 is usually made of p-AlGaN material. However, in this material system, the activation energy of doping Mg is relatively high, and it is difficult to achieve a high hole concentration and a low resistivity. Therefore, the electron blocking layer 61 in this embodiment adopts a p-AlGaN polarization-induced layer, which can reduce the differential resistance of the device.

[0250] The electron blocking layer 61 can also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.1 ≤ e ≤ 0.3, p-Al e Ga 1-eThe Al component in p-AlGaN is about 10% to 30%. e Ga 1-e The thickness of p-GaN can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm.

[0251] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 can be 80 nm to 200 nm. The hole injection layer 62 may also include p-Al h Ga 1-h The p-AlGaN / p-GaN superlattice layer has 0.15 ≤ h ≤ 0.25, and the hole concentration can be 1.5×10 18 cm -3 ~2.5×10 18 cm -3 。Among them, the Al component in p-AlGaN is about 15% to 25%. h Ga 1-h The Al component in p-AlGaN is about 15% to 25%, and the thickness of p-AlGaN can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm. h Ga 1-h The Al component in p-AlGaN is about 15% to 25%, and the thickness of p-AlGaN can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm.

[0252] The ohmic contact layer 63 may include at least one period (such as 4 to 6 periods) of p-InGaN / p-GaN superlattice layer, 0.1 ≤ f ≤ 0.2. Among them, the In component in p-InGaN is about 10% to 20%. f Ga 1-f The ohmic contact layer 63 may include at least one period (such as 4 to 6 periods) of p-InGaN / p-GaN superlattice layer, 0.1 ≤ f ≤ 0.2. Among them, the In component in p-InGaN is about 10% to 20%. f Ga 1-f The In component in p-InGaN is about 10% to 20%, and the thickness of p-InGaN can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm. f Ga 1-f The In component in p-InGaN is about 10% to 20%, and the thickness of p-InGaN can be 2 nm to 3 nm, and the thickness of p-GaN can be 2.5 nm to 15 nm.

[0253] In some embodiments, the pixel unit 20 further includes a protective layer 75. The protective layer 75 is located between the quantum well light-emitting layer 5 and the second semiconductor layer 6, that is, the protective layer 75 is located between the quantum well light-emitting layer 5 and the electron blocking layer 61. The cross-sectional area of the protective layer 75 is smaller than the cross-sectional area of the quantum well light-emitting layer 5, and the cross-sectional area of the protective layer 75 is larger than the cross-sectional area of the electron blocking layer 61.

[0254] Among them, the protective layer 75 may include a u-GaN layer, and the thickness of the protective layer 75 can be 20 nm to 50 nm.

[0255] In some embodiments, the display chip further includes a substrate 100. The substrate 100 is bonded to the side of the pixel unit 20 facing away from the first semiconductor layer 4.

[0256] In some embodiments, the substrate 100 is located on the side of the first dielectric layer 84 away from the first semiconductor layer 4, and the substrate 100 is bonded to the chip structure 200 through the first bonding structure 30.

[0257] Among them, the substrate 100 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0258] In some embodiments, the substrate 100 includes a second dielectric layer 91 and a second bonding structure 50 penetrating the second dielectric layer 91, and the second bonding structure 50 is bonded to the first bonding structure 30 in the chip structure 200.

[0259] In this embodiment, the bonding connection between the pixel unit 20 and the substrate 100 is realized through the first bonding structure 30 and the second bonding structure 50, improving the bonding accuracy.

[0260] In some embodiments, the second bonding structure 50 includes a second bonding layer 92 and a second bonding protection layer 93. The second bonding layer 92 penetrates the second dielectric layer 91, and the second bonding protection layer 93 is disposed around the second bonding layer 92. Among them, the second bonding protection layer 93 may include a TiN layer, and the second bonding layer 92 may include a metal layer such as Ni / Au, Pt / Au or Cu.

[0261] In some embodiments, the display chip further includes a second transparent conductive layer 88. The second transparent conductive layer 88 is located on the side of the first semiconductor layer 4 away from the second semiconductor layer 5, that is, the second transparent conductive layer 88 is located on the side of the heavily doped semiconductor layer 41 away from the lightly doped semiconductor layer 42. Among them, the second transparent conductive layer 88 may include an ITO layer, and the thickness of the second transparent conductive layer 88 may be 100 nm to 400 nm.

[0262] In some embodiments, the display chip further includes a microlens 85. The microlens 85 is located on the side of the second transparent conductive layer 88 away from the substrate 100, and the microlens 89 corresponds to the position of the pixel unit 20. The microlens 89 is used to increase the light collection of the chip. The microlens 85 includes SiO2, etc.

[0263] According to the display chip provided by the embodiments of the present application, the risk of damage to the pixel unit 20 is reduced, and the light-emitting performance of the display chip is improved. Moreover, the cross-sectional area of the pixel unit 20 gradually increases in the direction A pointing from the second semiconductor layer 6 to the first semiconductor layer 4, so as to reduce the light-emitting divergence angle of the display chip, improve the light extraction efficiency of the display chip, and further improve the light efficiency of the display chip, improve the display effect of the display device, and achieve high-precision bonding of the pixel unit and the substrate 100 through the first bonding structure 30 and the second bonding structure 50.

[0264] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category and do not limit the number of objects. For example, the first object can be one or more.

[0265] In the description of this application, "a plurality of" means two or more.

[0266] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0267] Although the embodiments of this application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this application, and the scope of this application is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a display chip, characterized in that, Comprising: Forming a base structure; The base structure includes a substrate and a two-dimensional material layer on one side of the substrate; Forming pixel units on the side of the two-dimensional material layer facing away from the substrate, the pixel units including a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially disposed on the side of the two-dimensional material layer facing away from the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; Removing the base structure.

2. The method for manufacturing a display chip according to claim 1, characterized in that, The two-dimensional material layer corresponds to the position of the pixel units.

3. The method for manufacturing a display chip according to claim 2, characterized in that, The substrate includes a substrate pattern layer on the side of the substrate close to the two-dimensional material layer; The forming of the base structure includes: Providing a substrate; Forming an initial two-dimensional material layer on one side of the substrate; Patterning the initial two-dimensional material layer to obtain the two-dimensional material layer, and patterning the side of the substrate close to the initial two-dimensional material layer to obtain the substrate pattern layer.

4. The method for manufacturing a display chip according to claim 3, characterized in that, The substrate pattern layer and the two-dimensional material layer constitute a two-dimensional material structure; The shape of the two-dimensional material structure includes at least one of cylindrical, hemispherical, conical, and polyhedral shapes.

5. The method for manufacturing a display chip according to claim 1, characterized in that, The two-dimensional material layer includes at least one of graphene, hexagonal boron nitride, and molybdenum disulfide.

6. The method for manufacturing a display chip according to claim 1, characterized in that, The removing of the base structure includes: Removing the substrate; Removing the two-dimensional material layer.

7. The method for manufacturing a display chip according to claim 6, characterized in that, The removing of the substrate includes: Forming a grid protection layer on the side of the substrate facing away from the pixel units, and the grid protection layer corresponds to the position of the pixel units; Removing the substrate and simultaneously removing the grid protection layer.

8. The method for manufacturing a display chip according to claim 7, characterized in that, The grid protection layer includes at least one of silicon oxide and silicon nitride.

9. The method for manufacturing a display chip according to claim 7, characterized in that, The removing of the substrate includes: Using a laser lift-off technique to remove the substrate.

10. The method for manufacturing a display chip according to claim 6, characterized in that, The base structure further includes a transition layer on the side of the two-dimensional material layer facing away from the substrate and covering the substrate, and the pixel units are located on the side of the transition layer facing away from the substrate; The removing of the two-dimensional material layer includes: Removing the transition layer and simultaneously removing the two-dimensional material layer.

11. The method for manufacturing a display chip according to claim 10, characterized in that, The transition layer includes a buffer layer and a first undoped semiconductor layer; The buffer layer is on the side of the two-dimensional material layer facing away from the substrate and covers the substrate, and the first undoped semiconductor layer is between the buffer layer and the pixel units.

12. The manufacturing method of the display chip according to claim 11, wherein The transition layer further includes a graded buffer layer between the buffer layer and the first undoped semiconductor layer.

13. The manufacturing method of the display chip according to any one of claims 1-12, wherein Before removing the base structure, further including: Bonding the side of the pixel units facing away from the base structure to a substrate.

14. The manufacturing method of the display chip according to claim 13, wherein The pixel units further include a first transparent conductive layer and a first reflective layer sequentially disposed on the side of the second semiconductor layer facing away from the quantum well light-emitting layer, and the substrate includes a second bonding structure; The bonding of the side of the pixel units facing away from the base structure to a substrate includes: Forming a dielectric layer on the side of the first reflective layer facing away from the first transparent conductive layer; Forming a first bonding structure passing through the dielectric layer and connected to the first reflective layer; Bond the pixel unit to the substrate through the first bonding structure and the second bonding structure.

15. The manufacturing method of the display chip according to claim 14, wherein The first bonding structure includes a bonding layer and a bonding protective layer; The formation of the first bonding structure that penetrates the dielectric layer and is connected to the first reflective layer includes: Form an opening that penetrates the dielectric layer; Form the bonding protective layer on the sidewall of the opening; Form the bonding layer connected to the first reflective layer in the opening.

16. The manufacturing method of the display chip according to claim 14, wherein Before forming the dielectric layer on the side of the first reflective layer facing away from the first transparent conductive layer, it further includes: Form a passivation layer on the side of the first reflective layer facing away from the first transparent conductive layer, and the passivation layer covers the sidewall of the pixel unit; Form a second reflective layer on the surface of the passivation layer, the dielectric layer is located on the side of the second reflective layer facing away from the first reflective layer, and the first bonding structure penetrates the dielectric layer, the second reflective layer and the passivation layer and is connected to the first reflective layer.

17. The manufacturing method of the display chip according to claim 13, wherein After removing the base structure, it further includes: Form a second transparent conductive layer on the side of the pixel unit facing away from the substrate; Form a microlens on the side of the second transparent conductive layer facing away from the substrate.

18. The manufacturing method of the display chip according to claim 1, wherein The pixel unit further includes a second undoped semiconductor layer, a barrier layer, a first superlattice layer, and a second superlattice layer that are sequentially arranged between the first semiconductor layer and the quantum well light-emitting layer.

19. A display chip, wherein It is formed by using the manufacturing method of the display chip according to any one of claims 1 to 18.

20. A substrate structure, wherein Applied in the manufacturing method of the display chip according to any one of claims 1 to 18, the base structure includes: A substrate; A two-dimensional material layer located on one side of the substrate.

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