Techniques for configuring computing nodes in computing system

Abstract

The disclosure relates to techniques for configuring computing nodes in a computing system. An integrated circuit includes logic circuitry that may be configured by a bitstream of configuration data to perform a computing service requested in a computing system. An integrated circuit communicates with a central processing unit in a computing system to perform a computing service in accordance with an interface characteristic indicated by metadata provided to the central processing unit.

Description

Technical Field

[0001] This disclosure relates to electronic computing systems, and more particularly to circuits, systems, and methods for configuring computing nodes in a computing system to perform computing services. Background Art

[0002] A configurable integrated circuit (IC) can be configured by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom circuit design. When the design process is complete, the computer-aided design tool generates an image containing configuration data. The configuration data is then loaded into configuration memory elements that configure the configurable logic circuits in the integrated circuit to perform the functions of the custom circuit design. Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided an integrated circuit comprising: a logic circuit that can be configured by a bitstream of configuration data to perform a computing service requested in a computing system, wherein the integrated circuit communicates with a central processing unit in the computing system according to interface characteristics indicated by metadata provided to the central processing unit to perform the computing service.

[0004] According to one aspect of the present disclosure, there is provided a method for configuring a computing system to perform a first computing service, the method comprising: receiving an application request for performing the first computing service from a primary computing node in the computing system; in response to the application request, configuring a configurable integrated circuit in a secondary computing node in the computing system with an image to perform the first computing service; and communicating with the configurable integrated circuit in the secondary computing node according to interface parameters indicated by metadata.

[0005] According to one aspect of the present disclosure, there is provided a computing system comprising: a configurable integrated circuit that can be configured by an image including a bitstream to perform a computing service for the computing system; and a central processing device that communicates with the configurable integrated circuit according to interface characteristics defined by metadata provided to the central processing device. Brief Description of the Drawings

[0006] Figure 1 is a schematic diagram of an orchestrated and configured computing system that includes a primary computing node controlling secondary computing nodes.

[0007] Figure 2 is a schematic diagram illustrating an example of a configurable logic integrated circuit that can implement the techniques disclosed herein.

[0008] Figure 3 The block diagram of the system is illustrated, and the system can be used to implement the circuit design to be programmed onto the programmable logic device using design software.

[0009] Figure 4 It is a schematic diagram depicting an example of a programmable logic device, which includes a structural die and a substrate die connected to each other via microbumps.

[0010] Figure 5 It is a block diagram of a computing system configured to implement one or more aspects of the embodiments disclosed herein. Detailed Description

[0011] A field programmable gate array (FPGA) is a type of configurable integrated circuit. In a traditional FPGA deployment (e.g., in a cloud computing environment), the FPGA is used both as an accelerator for the host and for providing dynamic or customized interface functions via networking or host interface standards. Traditionally, the accelerator features are exposed as software definable elements and integrated into the orchestration and provisioning solutions.

[0012] The FPGA is used as an accelerator as part of a node in the computing system. The accelerator function is orchestrated like any other computing solution. The interface characteristics are not presented to the provisioning elements because in most implementations, the interface characteristics are immutable. However, when using an FPGA, not only does the accelerator function change dynamically, but also the interface (i.e., host, network, memory) characteristics (such as throughput, latency, power consumption, and security) change.

[0013] Previously known heterogeneous cloud orchestration systems provide an abstract definition of the logical function understood by the orchestration software. For example, the function and the node capable of executing the function are presented to the orchestration software. The orchestration software only knows that the node is capable of executing the function but does not know how to execute the function. The provisioning and execution of the function are invoked via an industry standard middleware framework that has an abstract function and translates the function into the underlying hardware for execution. When a node is inserted into the network, it is usually defined and exposed and fixed to the orchestration software at this function level.

[0014] Prior known orchestration and provisioning techniques do not allow for direct dynamic configuration of interface characteristics, which greatly limits the key advantages of FPGAs (i.e., flexible interface and computational characteristics). To fully realize the potential of FPGAs in heterogeneous computing systems, it would be desirable to provide the ability to seamlessly integrate interface characteristics as well as computational acceleration services. It would be desirable to be able to teach the orchestration and provisioning software about the capabilities of the available FPGA images so that appropriate workloads and interface specifications can be directly loaded onto the FPGA. It would also be desirable to enable the provisioning software to request certain interface characteristics so that the images can be built with those interface characteristics in cases where the images do not already exist in the library.

[0015] Field programmable gate arrays (FPGAs) are unique as hardware computing or acceleration platforms because FPGAs can provide many different acceleration or interface operations. Additionally, by loading a new bitstream image into the FPGA, the functions performed by the FPGA can change during runtime. According to some examples disclosed herein, the functionality of configurable ICs such as FPGAs can be dynamically managed as part of a cloud or enterprise orchestration and provisioning computing system.

[0016] According to some examples, containerized application build frameworks (e.g., Kubernetes, docker-compose, etc.) are extended to include interface characteristics as new configuration parameters, which include fields such as throughput, latency, power, and security for each general purpose input / output (I / O) (e.g., network, host interface, memory interface). The provisioning requests for the configurable ICs include these configuration parameters as part of the metadata sent to the services. These services are, for example, included in a pre-built image library or fed into a synthesis tool to build an appropriate image for the accelerator and the interface. The image is used to configure one or more configurable ICs. The decision on how to balance the accelerator and interface circuits can be fixed or can be dynamic based on various computational requirements and weighted characteristics of the available FPGA resources.

[0017] One or more specific examples are described below. To provide a concise description of these examples, not all features of actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Additionally, it should be understood that such development work may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, this is merely routine design, fabrication, and manufacturing work.

[0018] Throughout the specification, and in the claims, the term "connected" means a direct electrical connection between the connected circuits, without any intermediate devices. The term "coupled" means a direct electrical connection between circuits, or an indirect electrical connection through one or more passive or active intermediate devices, which allows information transfer between the circuits. The term "circuit" may refer to one or more passive and / or active electrical components arranged to cooperate with each other to provide a desired function.

[0019] This disclosure discusses integrated circuit devices, including configurable (programmable) logic integrated circuits, such as field programmable gate arrays (FPGAs). As described herein, an integrated circuit (IC) may include hard logic and / or soft logic. Circuits in an integrated circuit device (e.g., a configurable logic IC) that can be configured by an end user are referred to as "soft logic". "Hard logic" generally refers to circuits in an integrated circuit device that have significantly fewer configurable features or no configurable features.

[0020] An infrastructure processing unit (IPU) is a system-on-chip (SoC) that has hardware accelerators for performing any infrastructure operations. The IPU may include programmable networking devices that manage system-level infrastructure resources by securely accelerating the functions of a data center. An artificial intelligence (AI) engine is an SoC, a graphics processing unit (GPU), an application specific integrated circuit (ASIC), or a configurable IC that has hardware for accelerating AI algorithms. When presented to the orchestration software in a heterogeneous computing system, a node can be configured to perform a target function. For example, a node configured as an IPU node can offload IPU-centric functions (e.g., firewall or TLS encryption or remote storage). An AI node performs AI operations for AI-oriented services or workloads. Prior known nodes are fixed in terms of their functions to the orchestration software and do not need to be dynamically configured.

[0021] Compared with application-specific integrated circuits (ASICs) used for functional abstraction, FPGAs have enhanced functionality. At any given time, an FPGA can have the characteristics of any (or all) of the IPU nodes, AI nodes, or another type of node. The performance of these nodes depends to a large extent on the I / O and may therefore also need to be modified to achieve optimal application behavior. Thus, for example, FPGA nodes in a heterogeneous computing system are not typically labeled as IPU or AI nodes but may have the characteristics of both types of nodes, depending on what image is loaded onto the FPGA. To properly orchestrate such a product, a new classification is used in the orchestration software, which includes I / O characteristics related to a list of capabilities that can be loaded onto the target node. This list can be from an FPGA image library that has both the images that need to be loaded onto the FPGA and an inventory of all available images and how the images map to functional orchestration. The list can also include a set of configuration parameters for the FPGA synthesis tool used to dynamically generate the images loaded onto the FPGA.

[0022] After the target image is selected or generated by the orchestration software, the underlying provisioning function is initiated. This provisioning function loads the selected or generated image into the FPGA, loads the appropriate middleware software onto the node to integrate the capabilities of the node into a larger execution environment, and notifies the orchestration software of the functions loaded onto the FPGA node. The node then appears as a functional node (e.g., an IPU or AI node) and is presented as such to the rest of the computing environment, including any interface configurations needed to execute the function with optimal behavior.

[0023] Figure 1 is a schematic diagram of an orchestrated and provisioned computing system 100 that includes a main computing node 101 that controls secondary computing nodes 103, 105, 107, and 109. The main computing node 101 can be deployed, for example, in a cloud computing environment. Each of the computing nodes 101, 103, and 105 includes a computer or computing system that has a memory, a central processing unit (CPU), and other computing resources. The CPU in each of the computing nodes 101, 103, and 105 can be, for example, one or more microprocessor integrated circuits (ICs), a system-on-chip (SoC), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC).

[0024] The main computing node 101 runs a load balancing service 102, which can be implemented, for example, by software running on the CPU in node 101. The load balancing service 102 load balances application service requests to the main computing node 101 among the secondary computing nodes 103, 105, 107, and 109 via the bus 130. Thus, the load balancing service 102 provides application service requests to perform various computing services for the secondary computing nodes 103, 105, 107, and 109. Then, the secondary computing nodes 103, 105, 107, and 109 perform the computing services associated with the application service requests and provide the results of these computing services back to the main computing node 101 via the bus 130.

[0025] The secondary computing nodes 103 and 105 have fixed functions, which are respectively executed by the application services 104 and 106 and cannot be dynamically configured. For example, if one of the secondary computing nodes 103 and 105 is configured as an artificial intelligence (AI) node, then this secondary computing node can only perform AI operations for AI-oriented services or workloads. For another example, if one of the secondary computing nodes 103 and 105 is configured as an infrastructure processing unit (IPU) node, then this secondary computing node can only perform functions associated with computing infrastructure operations. Therefore, the load balancing service 102 provides application service requests to the secondary computing nodes 103 and 105 to perform computing services that can be executed by the fixed functions of nodes 103 and 105.

[0026] The secondary computing nodes 107 and 109 are also referred to as computing flexible nodes in this document. The computing flexible nodes 107 and 109 have dynamic functions, which can be dynamically configured and executed by the configuration services 108 and 110 respectively. Each of the computing flexible nodes 107 and 109 has a computer or computing system, which includes a central processing unit (CPU), CPU storage, a configurable integrated circuit (CIC), and other computing resources. The computing flexible node 107 includes a CPU 141, a CIC 143, and a CPU storage (STG) 145. The computing flexible node 109 includes a CPU 142, a CIC 144, and a CPU storage (STG) 146. The configurable IC in each of the computing flexible nodes 107 and 109 can include, for example, one or more configurable logic devices, such as a field programmable gate array (FPGA). The CPU in each of the computing flexible nodes 107 and 109 can be, for example, one or more microprocessor integrated circuits (ICs), a system on a chip (SoC), a graphics processing unit (GPU), or an application specific integrated circuit (ASIC).

[0027] By configuring the configurable ICs 143 or 144 in each of the compute flexible nodes 107 or 109 with an image of a bitstream containing configuration data, each of the compute flexible nodes 107 and 109 can be configured to perform the functions of any type of compute node (e.g., IPU node or AI node) in the compute system 100. For example, the configurable IC 143 in the compute flexible node 107 can be configured via an image containing a bitstream to act as a configured compute node 111 and perform the configured service 112 requested by the load balancing service 102. As another example, the configurable IC 144 in the compute flexible node 109 can be configured via an image containing a bitstream to act as a configured compute node 113 and perform the configured service 114 requested by the load balancing service 102. Each of the configured compute nodes 111 and 113 can be configured to perform the functions of any type of compute node (e.g., IPU node or AI node) in the compute system 100.

[0028] The compute system 100 includes a provisioning manager 122 and a provisioning executor 123 that provision the provisioning services 108 and 110 to generate the provisioned services 112 and 114 by configuring the configurable ICs 143 and 144 in the compute flexible nodes 107 and 109 to respectively generate the configured compute nodes 111 and 113. The provisioning manager 122 includes software (e.g., running on a processor circuit) that receives one or more application service requests (e.g., from the load balancing service 102) to provision one or more sub-compute nodes in the compute system 100 to perform one or more requested application services, such as a firewall service, an image recognition AI service, a user management service, a web server service, or an application accelerator.

[0029] The provisioning manager 122 receives one or more bundles 121 for one or more application service requests. The bundle 121 includes an image containing a bitstream for configuring one or more configurable ICs to perform an application service. For example, an image containing a bitstream for configuring a configurable IC to perform an application service can be accessed from a pre-built image library or from a synthesis tool that generates an appropriate image for implementing one or more application services.

[0030] Bundle 121 may also include metadata of the application service. The metadata of the bundle of the application service may include configuration parameters that describe interface characteristics, and these interface characteristics define the ways in which host CPUs 141-142 communicate with CICs 143-144 respectively. The metadata provided to compute flexible node 107 is used as an input to the orchestration decision logic in CPU 141 to select interface characteristics for defining the way in which host CPU 141 communicates with CIC 143. The metadata provided to compute flexible node 109 is used as an input to the orchestration decision logic in CPU 142 to select interface characteristics for defining the way in which host CPU 142 communicates with CIC 144. Alternatively, the orchestration decision logic in CPUs 141-142 may select an image containing a bitstream to be loaded into CICs 143-144 based on the configuration parameters indicated by the metadata, and these images are accessed from host CPU storage devices 145-146 respectively. Based on a library of pre-built configuration images or as part of features that can be synthesized in the real-time synthesis of CICs 143-144, the metadata indicates to the orchestration decision logic in CPUs 141-142 what the capabilities of CICs 143-144 are.

[0031] Host CPUs 141-142 may use the metadata to configure or reconfigure the interface characteristics of CPUs 141 and 142, such as data throughput, latency, power consumption, or security characteristics of each general-purpose input / output (I / O) (e.g., network, host interface, or memory interface). The performance of compute flexible nodes 107 and 109 may depend on these interface characteristics, and thus, it may be necessary to modify compute flexible nodes 107 and 109 through the metadata to achieve optimal application behavior. In some examples, the load balancing service 102 or other applications running on compute node 101 (e.g., containerized application building framework) include these interface characteristics as configuration parameters (e.g., throughput, latency, power consumption, and security characteristics) in the application service request, and these requests are provided to the provisioning manager 122 for provisioning compute flexible nodes 107 and 109.

[0032] The provisioning manager 122 selects metadata and an image containing a bitstream for configuring the configurable ICs 143 and 144 in the selected nodes among the compute flexible nodes 107 and 109, and provides the selected image and metadata to the provisioning executor 123. The provisioning executor 123 includes software that provides the image and metadata received from the provisioning manager 122 to one or both of the compute flexible nodes 107 and 109. The image received from the provisioning executor 123 is loaded into the configurable ICs 143 - 144 in the selected compute flexible nodes 107 and 109. Then, the configurable ICs 143 - 144 in the compute flexible nodes 107 and 109 are configured with the image containing the bitstream to act as the configured nodes 111 and 113, respectively. Accordingly, the provisioning services 108 and 110 associated with the compute flexible nodes 107 and 109 are configured as the provisioned services 112 and 114, respectively. In addition, the provisioning executor 123 notifies the load balancing service 102 that at least some subset of the application service requests is assigned to the compute flexible nodes 107 and 109.

[0033] As a non - limiting specific example, the provisioning manager 122 and the provisioning executor 123 can provision and configure the configurable ICs 143 and 144 in the compute flexible nodes 107 and 109 as the configured nodes 111 and 113, which implement the provisioned services 112 and 114, respectively, such as one or more of the following: the firewall service of the primary compute node 101, the AI service (e.g., image recognition) of the primary compute node 101, the IPU service of the primary compute node 101, the user management service of the primary compute node 101, the web server of the primary compute node 101, the encryption / decryption service of the primary compute node 101, the storage service of the primary compute node 101, and / or the application acceleration task of the primary compute node 101. Thus, the compute flexible nodes 107 and 109 can be configured to perform various different computing services.

[0034] Figure 2 is a schematic diagram illustrating an example of a configurable logic IC 200 that can implement the techniques disclosed herein. According to some examples, the CICs 143 and / or 144 disclosed herein in the compute flexible nodes 107 and 109 can include the architecture of the configurable logic IC 200. As Figure 2As shown, the configurable logic IC 200 includes a two-dimensional array of configurable logic circuit blocks, which includes configurable logic array blocks (LABs) 210 and other functional circuit blocks, such as random access memory (RAM) blocks 230 and digital signal processing (DSP) blocks 220. Functional blocks such as LAB 210 may include smaller configurable logic circuits (e.g., logic elements, logic blocks, or adaptive logic modules) that receive input signals and perform customized functions on the input signals to generate output signals.

[0035] In addition, the configurable logic IC 200 may have input / output elements (IOEs) 202 for driving signals out of the configurable logic IC 200 and for receiving signals from other devices. The IOE 202 may include parallel input / output circuits, serial data transceiver circuits, differential receiver and transmitter circuits, or other circuits for connecting one integrated circuit to another. As shown, the IOE 202 may be located at the periphery of the chip. If desired, the configurable logic IC 200 may have IOEs 202 arranged in different ways. For example, the IOE 202 may form one or more columns, one or more rows, or one or more islands of input / output elements that may be located anywhere on the configurable IC 200. The input / output elements 202 may include general purpose input / output (GPIO) circuits (e.g., at the top and bottom edges of the IC 200), high-speed input / output (HSIO) circuits (e.g., at the left edge of the IC 200), and on-package input / output (OPIO) circuits (e.g., at the right edge of the IC 200).

[0036] The configurable logic IC 200 may also include programmable interconnect circuits in the form of vertical routing channels 240 (i.e., interconnects formed along the vertical axis of the configurable logic IC 200) and horizontal routing channels 250 (i.e., interconnects formed along the horizontal axis of the configurable logic IC 200), each routing channel including at least one track for routing at least one wire. One or more of the routing channels 240 and / or 250 may be part of a network-on-chip (NOC) with router circuits.

[0037] Note that in addition to Figure 2In addition to the topologies of the interconnect circuits depicted, other routing topologies may be used. For example, the routing topology may include wires that travel diagonally or horizontally and vertically along different portions of its extent, and in the case of a three-dimensional integrated circuit, wires perpendicular to the device plane. The driver of a wire may be located at a point different from one end of the wire.

[0038] In addition, it should be understood that the embodiments disclosed herein may be implemented in any integrated circuit or electronic system. If desired, the functional blocks of such an integrated circuit may be arranged in more levels or layers, where multiple functional blocks are interconnected to form larger blocks. Other device arrangements may use functional blocks that are not arranged in rows and columns. Figure 1 The configurable logic IC 200 may include programmable memory elements. The memory elements may be loaded with configuration data using the IOE 202. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated configurable functional block (e.g., LAB 210, DSP block 220, RAM block 230, or IOE 202). The configuration data may set the function of the configurable functional circuit blocks (soft logic) in the IC 200.

[0039] In a typical scenario, the output of the loaded memory elements is applied to the gates of field effect transistors in the functional blocks to turn on or off certain transistors, thereby configuring the logic in the functional blocks, including routing paths. Programmable logic circuit elements controlled in this manner include a portion of multiplexers (e.g., multiplexers used to form routing paths in the interconnect circuit), look-up tables, logic arrays, AND, OR, NAND, and NOR logic gates, transmission gates, and the like.

[0040] The memory elements may use any suitable volatile and / or non-volatile memory structure, such as random access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask programming and laser programming structures, combinations of these structures, and so on. Since the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memory or programmable memory elements.

[0041] The memory elements may be organized in a configuration memory array consisting of rows and columns. Data registers spanning all columns and address registers spanning all rows may receive configuration data. The configuration data may be transferred onto the data registers. When an appropriate address register is asserted, the data register writes the configuration data to the configuration memory bits of the row specified by the address register.

[0042]

[0043] ​The configurable integrated circuit 200 may include a configuration memory organized in sectors, whereby a sector may include configuration bits that specify the function and / or interconnection of sub-components and wires within or traversing the sector. Each sector may include separate data and address registers.

[0044] Figure 2 The configurable IC of is just one example of an IC that may include the embodiments disclosed herein. The embodiments disclosed herein may be incorporated into any suitable integrated circuit or system. For example, the embodiments disclosed herein may be incorporated into a variety of types of devices, such as processor integrated circuits, central processing units, memory integrated circuits, graphics processing unit integrated circuits, application specific standard products (ASSPs), application specific integrated circuits (ASICs), and programmable logic integrated circuits. Examples of programmable logic integrated circuits include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), to name just a few.

[0045] The integrated circuit disclosed in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; a memory; input / output circuitry; and peripherals. The data processing system may be used in a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application. The integrated circuit may be used to perform a variety of different logical functions.

[0046] In general, software and data for performing any function disclosed herein can be stored in a non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium is a tangible computer-readable storage medium that stores data and software for later access, rather than a medium that only transmits propagating electrical signals (e.g., wires). Software code may sometimes be referred to as software, data, program instructions, instructions, or code. A non-transitory computer-readable storage medium may include, for example, computer memory chips, non-volatile memory, such as non-volatile random-access memory (NVRAM), one or more hard disk drives (e.g., magnetic drives or solid-state drives), one or more removable flash drives or other removable media, compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs (BDs), other optical media, and floppy disks, magnetic tapes, or any other suitable (one or more) memory or storage devices.

[0047] Figure 3 FIG. shows a block diagram of a system 10 that can be used to implement a circuit design to be programmed onto a programmable logic device 19 using design software. A designer can implement circuit design functionality on an integrated circuit, such as a reconfigurable programmable logic device 19 (e.g., a field programmable gate array (FPGA)). The designer can use design software 14 to implement a circuit design to be programmed onto the programmable logic device 19. The design software 14 can use a compiler 16 to generate a low-level circuit design program (bitstream) 18 for programming the programmable logic device 19, sometimes referred to as a program object file and / or a configuration program. Thus, the compiler 16 can provide machine-readable instructions representing the circuit design to the programmable logic device 19. For example, the programmable logic device 19 can receive one or more programs (bitstreams) 18 that describe the hardware implementation that should be stored in the programmable logic device 19. The program (bitstream) 18 can be programmed into the programmable logic device 19 as a configuration program 20. In some cases, the configuration program 20 can represent an accelerator function to be performed for machine learning, video processing, speech recognition, image recognition, or other highly specialized tasks.

[0048] In some implementations, the programmable logic device can be any integrated circuit device that includes a programmable logic device having two separate integrated circuit die, where at least some of the programmable logic structures are separated from at least some of the structural support circuits that operate the programmable logic structures. Figure 4An example of such a programmable logic device is shown, but many other examples may also be used, and it should be understood that the present disclosure is intended to cover any suitable programmable logic device in which the programmable logic structure and the structure support circuitry are at least partially separated on different integrated circuit dies.

[0049] Figure 4 FIG. is a schematic diagram depicting an example of a programmable logic device 25 that includes three structural dies 22 and two substrate dies 24 connected to each other via microbumps 26. In Figure 4 this example, at least some of the programmable logic structure of the programmable logic device 25 is located in the three structural dies 22, and at least some of the structure support circuitry that operates the programmable logic structure is located in the two substrate dies 24. For example, Figure 2 some circuits of the configurable IC 200 shown in FIG. (e.g., LAB 210, DSP 220, RAM 230) may be located in the structural die 22, and some circuits of the IC 200 (e.g., input / output elements 202) may be located in the substrate die 24.

[0050] Although in Figure 4 FIG., the structural die 22 and the substrate die 24 appear in a one-to-one relationship or a two-to-one relationship, other relationships may also be used. For example, a single substrate die 24 may be attached to a plurality of structural dies 22, or a plurality of substrate dies 24 may be attached to a single structural die 22, or a plurality of substrate dies 24 may be attached to a plurality of structural dies 22 (e.g., in a staggered pattern). The peripheral circuitry 28 may be attached to, embedded within, and / or disposed on top of the substrate die 24, and a heat sink 30 may be used to reduce heat buildup on the programmable logic device 25. The heat sink 30 may appear above and / or below the package as shown (e.g., as a double-sided heat sink). The substrate die 24 may be attached to the package substrate 32 via conductive bumps 34. In Figure 4 this example of FIG., two pairs of structural dies 22 and substrate dies 24 are shown communicatively connected to each other via an interconnect bridge 36 (e.g., an embedded multi-die interconnect bridge (EMIB)) and microbumps 38 at a bridge interface 39 in the substrate die 24.

[0051] In combination, the fabric die 22 and the base die 24 can operate in combination as a programmable logic device 25, such as a field programmable gate array (FPGA). It should be understood that when both the fabric die 22 and the base die 24 operate in combination, the FPGA can represent, for example, the circuit type and / or logic arrangement of a programmable logic device. Additionally, while an FPGA is described for this example herein, it should be understood that any suitable type of programmable logic device can be used.

[0052] Figure 5 The block diagram of illustrates a computing system 500 configured to implement one or more aspects of the embodiments described herein. The computing system 500 includes a processing subsystem 70 having one or more processors 74, a system memory 72, and a programmable logic device 25, which communicate via an interconnect path that may include a memory hub 71. The memory hub 71 can be a separate component within a chipset component or can be integrated within one or more of the processors 74. The memory hub 71 is coupled to an input / output (I / O) subsystem 50 via a communication link 76. The I / O subsystem 50 includes an input / output (I / O) hub 51 that enables the computing system 500 to receive input from one or more input devices 62. Additionally, the I / O hub 51 can enable a display controller included within one or more of the processors 74 to provide output to one or more display devices 61. In one embodiment, one or more of the display devices 61 coupled to the I / O hub 51 can include a local, internal, or embedded display device.

[0053] In one embodiment, the processing subsystem 70 includes one or more parallel processors 75 that are coupled to the memory hub 71 via a bus or other communication link 73. The communication link 73 can use any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. In one embodiment, one or more of the parallel processors 75 form a computationally centralized parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In one embodiment, one or more of the parallel processors 75 form a graphics processing subsystem that can output pixels to one of the one or more display devices 61 coupled to the I / O hub 51. One or more of the parallel processors 75 can also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 63.

[0054] Within the I / O subsystem 50, the system storage unit 56 can be connected to the I / O hub 51 to provide a storage mechanism for the computing system 500. The I / O switch 52 can be used to provide an interface mechanism to enable connections between the I / O hub 51 and other components (e.g., the network adapter 54 and / or the wireless network adapter 53 that can be integrated into the platform) as well as various other devices that can be added via one or more additional devices 55. The network adapter 54 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 53 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

[0055] The computing system 500 can include Figure 5 other components not shown, including other port connections, optical storage drives, video capture devices, etc., which can also be connected to the I / O hub 51. Any suitable protocol can be used to implement the communication paths Figure 5 for the various components in, for example, a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol, such as an NV Link high-speed interconnect, or an interconnect protocol known in the art.

[0056] In one embodiment, one or more parallel processors 75 include circuitry optimized for graphics and video processing, such as including video output circuitry, and constitute a Graphics Processing Unit (GPU). In another embodiment, one or more parallel processors 75 include circuitry optimized for general-purpose processing while retaining the underlying computing architecture. In yet another embodiment, the components of the computing system 500 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 75, the memory hub 71, the (one or more) processors 74, and the I / O hub 51 can be integrated into a System on Chip (SoC) integrated circuit. Alternatively, the components of the computing system 500 can be integrated into a single package to form a System in Package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 500 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0057] The computing system 500 shown herein is illustrative. Other variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors 74, and the number of parallel processors 75, can be modified as needed. For example, in some embodiments, the system memory 72 is directly connected to the processors 74 rather than through a bridge, and other devices communicate with the system memory 72 via the memory hub 71 and the processors 74. In other alternative topologies, the parallel processors 75 are connected to the I / O hub 51 or directly to one of the processors 74 rather than to the memory hub 71. In other embodiments, the I / O hub 51 and the memory hub 71 can be integrated into a single chip. Some embodiments may include two or more sets of processors 74 attached via multiple sockets, which can be coupled to two or more instances of the parallel processors 75.

[0058] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 500. For example, any number of additional cards or peripherals can be supported, or some components can be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 5 herein. For example, in some architectures, the memory hub 71 may be referred to as the north bridge, and the I / O hub 51 may be referred to as the south bridge.

[0059] Additional examples are now described. Example 1 is an integrated circuit that includes: logic circuitry configurable by a bitstream of configuration data to perform computational services requested in a computing system, wherein the integrated circuit communicates with a central processing unit in the computing system according to interface characteristics indicated by metadata provided to the central processing unit to perform the computational services.

[0060] In Example 2, the integrated circuit as described in Example 1 may optionally include, wherein the logic circuitry is configurable by the bitstream to perform artificial intelligence services in the computing system.

[0061] In Example 3, the integrated circuit as described in any one of Examples 1-2 may optionally include, wherein the logic circuitry is configurable by the bitstream to perform infrastructure processing unit services in the computing system.

[0062] In Example 4, the integrated circuit as described in any one of Examples 1-3 may optionally include, wherein the interface characteristics include at least one of the following: throughput, latency, power consumption, or security characteristics.

[0063] In Example 5, the integrated circuit as described in any one of Examples 1-4 may optionally include, wherein the logic circuit can be partially reconfigured by additional configuration data to perform a modified computing function.

[0064] In Example 6, the integrated circuit as described in any one of Examples 1-5 may optionally include, wherein the logic circuit can be configured by the bitstream to perform an application acceleration task in the computing system.

[0065] In Example 7, the integrated circuit as described in any one of Examples 1-6 may optionally include, wherein the logic circuit can be configured by the bitstream to perform a firewall service in the computing system.

[0066] In Example 8, the integrated circuit as described in any one of Examples 1-7 may optionally include, wherein the logic circuit can be configured by the bitstream to perform encryption and decryption in the computing system.

[0067] In Example 9, the integrated circuit as described in any one of Examples 1-8 may optionally include, wherein the logic circuit can be configured by the bitstream to perform a user management service for the computing system.

[0068] Example 10 is a method for configuring a computing system to perform a first computing service, the method comprising: receiving, from a main computing node in the computing system, an application request for performing the first computing service; in response to the application request, configuring a configurable integrated circuit in a secondary computing node in the computing system with an image to perform the first computing service; and communicating with the configurable integrated circuit in the secondary computing node according to interface parameters indicated by metadata.

[0069] In Example 11, the method as described in Example 10 further comprises: receiving, from the main computing node, a second request for load balancing the first computing service and a second computing service between the secondary computing node and an additional secondary computing node.

[0070] In Example 12, the method as described in any one of Examples 10-11 further comprises: providing the image and the metadata from a provisioning actuator to the secondary computing node to perform the first computing service.

[0071] In Example 13, the method as described in Example 12 further comprises: in response to receiving the application request for performing the first computing service, using a provisioning manager to select the image and the metadata; and providing the image and the metadata to the provisioning actuator.

[0072] In Example 14, the method as described in any one of Examples 10-13 may optionally include, wherein configuring the configurable integrated circuit in the secondary computing node to perform the first computing service includes: configuring the configurable integrated circuit in the secondary computing node with the image to perform an artificial intelligence service for the computing system.

[0073] In Example 15, the method as described in any one of Examples 10-14 may optionally include, wherein configuring the configurable integrated circuit in the secondary computing node to perform the first computing service includes: configuring the configurable integrated circuit in the secondary computing node with the image to perform an infrastructure processing unit service for the computing system.

[0074] Example 16 is a computing system, which includes: a configurable integrated circuit that can be configured by an image including a bitstream to perform a computing service for the computing system; and a central processing device that communicates with the configurable integrated circuit according to interface characteristics defined by metadata provided to the central processing device.

[0075] In Example 17, the computing system as described in Example 16 may optionally include, wherein the interface characteristics include at least one of the following: throughput, latency, power consumption, or security characteristics.

[0076] In Example 18, the computing system as described in any one of Examples 16-17 may optionally include, wherein the configurable integrated circuit can be configured to perform an artificial intelligence service for the computing system.

[0077] In Example 19, the computing system as described in any one of Examples 16-18 may optionally include, wherein the configurable integrated circuit can be configured to perform an infrastructure processing unit service for the computing system.

[0078] In Example 20, the computing system as described in any one of Examples 16-19 further includes: a provisioning manager that accesses the image from a library of pre-built configuration images or from a synthesis tool that generates the image; and a provisioning executor that provides the metadata to the central processing device and provides the image to the configurable integrated circuit.

[0079] The above description of the exemplary embodiments is given for illustration. The above description is not intended to be exhaustive or to limit the examples disclosed herein. The above merely illustrates the principles of the present disclosure, and those skilled in the art can make various modifications. The above embodiments can be implemented alone or in any combination.

Claims

1. An integrated circuit, comprising: A logic circuit that can be configured by a bitstream of configuration data to perform a computing service requested in a computing system, wherein the integrated circuit communicates with a central processing unit in the computing system to perform the computing service according to interface characteristics indicated by metadata provided to the central processing unit.

2. The integrated circuit of claim 1, wherein: The logic circuitry may be configured by the bitstream to perform artificial intelligence services in the computing system.

3. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuitry is configurable by the bitstream to perform infrastructure processing unit services in the computing system.

4. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The interface characteristics include at least one of the following: throughput, latency, power consumption, or security characteristics.

5. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuit may be partially reconfigured by the additional configuration data to perform a modified computing function.

6. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuit can be configured by the bitstream to perform application acceleration tasks in the computing system.

7. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuitry may be configured by the bitstream to perform a firewall service in the computing system.

8. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuitry is configurable by the bitstream to perform encryption and decryption in the computing system.

9. An integrated circuit as claimed in any one of claims 1 to 2, wherein: The logic circuitry may be configured by the bitstream to perform user management services for the computing system.

10. A method for configuring a computing system to perform a first computing service, the method comprising: receiving, from a master computing node in the computing system, an application request for executing the first computing service; In response to the application request, configuring a configurable integrated circuit in a secondary computing node in the computing system with an image to perform the first computing service; and The method further comprises communicating with the configurable integrated circuit in the secondary computing node according to the interface parameters indicated by the metadata.

11. The method of claim 10, further comprising: A second request is received from the primary computing node to load balance the first computing service and a second computing service between the secondary computing node and an additional secondary computing node.

12. The method according to any one of claims 10 to 11, further comprising: The image and the metadata are provided from a provisioning executor to the secondary computing node to perform the first computing service.

13. The method of claim 12, further comprising: In response to receiving the application request to execute the first computing service, selecting, using a configuration manager, the image and the metadata; and The image and the metadata are provided to the provisioning executor.

14. The method according to any one of claims 10 to 11, wherein: Configuring the configurable integrated circuit in the secondary computing node to perform the first computing service includes: The configurable integrated circuit in the secondary computing node is configured using the image to perform artificial intelligence services for the computing system.

15. The method according to any one of claims 10 to 11, wherein: Configuring the configurable integrated circuit in the secondary computing node to perform the first computing service includes: The configurable integrated circuit in the secondary computing node is configured using the image to perform infrastructure processing unit services for the computing system.

16. A computing system comprising: a configurable integrated circuit configurable by an image including a bitstream to perform computing services for the computing system; as well as A central processing device communicates with the configurable integrated circuit according to interface characteristics defined by metadata provided to the central processing device.

17. The computing system of claim 16, wherein: The interface characteristics include at least one of the following: throughput, latency, power consumption, or security characteristics.

18. The computing system of any one of claims 16-17, wherein: The configurable integrated circuit is configurable to perform artificial intelligence services for the computing system.

19. The computing system of any one of claims 16-17, wherein: The configurable integrated circuit is configurable to perform infrastructure processing unit services for the computing system.

20. The computing system of any one of claims 16-17, further comprising: a configuration manager that accesses the image from a library of pre-built configuration images or from a synthesis tool that generates the image; as well as A configuration executor provides the metadata to the central processing device and provides the image to the configurable integrated circuit.

Images