A test method and system for a chip simulation model

Abstract

The application relates to the technical field of chip design, in particular to a chip simulation model testing method and system. The method comprises the following steps: obtaining chip data, performing chip circuit logic analysis, and obtaining circuit logic data; performing signal transmission simulation based on the circuit logic data, and obtaining signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data; performing particle bombardment on the chip simulation model, and obtaining particle data; performing energy spectrum classification based on the particle data, and obtaining proton data and heavy ion data; performing single-particle flip fault analysis on the chip simulation model according to the proton data, and obtaining single-particle flip data; and performing multi-particle flip fault analysis on the chip simulation model according to the heavy ion data, and obtaining multi-particle flip fault data. The application evaluates and optimizes the reliability of a chip in a radiation environment based on chip design technology, thereby improving the radiation resistance of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a testing method and system for chip simulation models. Background Technology

[0002] Traditional chip simulation testing methods and systems have several drawbacks. They typically focus on single-particle effects (such as single-event upsets) while neglecting the impact of multiple-particle interactions (MPIU), resulting in an inability to comprehensively evaluate chip behavior under complex radiation environments. Traditional methods employ simplistic particle trajectory simulations, lacking accurate modeling of electromagnetic interactions between particles, leading to significant errors in predicting MPIU and interaction effects. Traditional simulation tools often rely on simplified irradiation models, failing to adequately consider the variability of actual radiation environments such as irradiation dose and particle energy distribution, resulting in test results lacking realism and accuracy. Traditional testing methods do not adequately consider the integration of chip redundancy design and error correction mechanisms, failing to react quickly and effectively when chips are affected by radiation, and lacking the ability to dynamically adjust redundancy design and correction strategies. Summary of the Invention

[0003] Therefore, the present invention needs to provide a testing method and system for chip simulation models to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, a testing method for a chip simulation model includes the following steps:

[0005] Step S1: Acquire chip data and perform chip circuit logic analysis to obtain circuit logic data; perform signal transmission simulation based on circuit logic data to obtain signal transmission data; construct a chip simulation model based on circuit logic data and signal transmission data.

[0006] Step S2: Bombard the chip simulation model with particles to obtain particle data; perform energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0007] Step S3: Perform single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; perform multi-event flip fault analysis on the chip simulation model based on heavy ion data to obtain multi-event flip fault data.

[0008] Step S4: Evaluate the chip radiation reliability based on single-event upset (SET) data and multi-event upset (MEI) fault data to obtain the chip radiation reliability; upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

[0009] This invention, by acquiring chip data and performing circuit logic analysis, accurately captures the circuit design characteristics of the chip, thus laying a solid foundation for subsequent simulation model construction. This process avoids the shortcomings of traditional simulation methods in understanding circuit logic and improves the reliability of subsequent simulation results. Furthermore, the introduction of signal transmission simulation enables a comprehensive analysis of the signal propagation process within the chip, making the simulation model closer to the actual operating state and helping to reveal signal transmission delays or distortions neglected in traditional methods. Next, the simulation model built based on circuit logic and signal transmission data combines the chip's circuit characteristics with the actual operating environment, enhancing the accuracy and comprehensiveness of the simulation model and providing a more accurate physical model for subsequent particle irradiation simulations. For particle bombardment and energy spectrum classification, it can accurately acquire particle data and classify them according to their different energies and properties, facilitating more detailed analysis of different radiation sources. This classification method compensates for the overly simplified irradiation models in traditional simulation methods, taking into account the different effects of different particle types (such as protons and heavy ions) on the chip, thus providing more accurate input data for multi-particle flip fault analysis. Furthermore, through single-event and multi-event upset (MEI) fault analysis, the impact of different types of particles on the chip can be comprehensively evaluated. In particular, the introduction of MEIU (Multi-Event Interaction) effects addresses the shortcomings of traditional simulation methods that neglect MEIU, making the simulation results more realistic and operable. Chip radiation reliability assessment allows for a systematic evaluation of the chip's overall performance under radiation environments, providing a comprehensive understanding of its reliability under complex radiation conditions. This assessment method effectively avoids the neglect of redundancy design and repair mechanisms in traditional testing methods, providing a scientific basis and feedback for radiation hardening design. Finally, through the implementation of radiation hardening testing, targeted optimization of the chip can be performed, quickly adjusting redundancy design and repair strategies, and providing real-time responses when affected by radiation, thereby effectively improving the chip's radiation resistance and enhancing its stability and reliability in practical applications.

[0010] Preferably, step S1 specifically includes:

[0011] Step S11: Acquire chip data and extract circuit principle features to obtain circuit principle data;

[0012] Step S12: Detect logic gate relationships based on circuit principle data to obtain logic gate relationship data;

[0013] Step S13: Generate a truth table based on the logic gate relation data to obtain the logic truth table;

[0014] Step S14: Perform logic unit verification based on the logic truth table and generate logic unit verification data;

[0015] Step S15: Based on the logic unit verification data, repair the circuit logic data of the circuit principle data to generate circuit logic data;

[0016] Step S16: Simulate signal transmission based on circuit logic data to obtain signal transmission data;

[0017] Step S17: Construct a chip simulation model based on circuit logic data and signal transmission data.

[0018] This invention, by acquiring chip data and extracting circuit principle features, accurately captures the basic structure and working principle of chip circuits, providing a solid foundation for subsequent simulation and testing. This step ensures that every detail of the chip design is precisely understood, thus avoiding circuit characteristics overlooked in traditional methods. Next, logic gate relationship detection based on circuit principle data helps analyze the connections between various logic units in the circuit, ensuring that the behavior and input-output relationships of each logic gate are fully captured, thereby improving the accuracy and reliability of the simulation model. By generating a logic truth table, the output behavior of the circuit under different input conditions can be accurately recorded, providing comprehensive predictions of the chip's performance under various operating conditions. Furthermore, through logic unit verification, it is possible to check and verify whether the circuit logic meets predetermined design standards, which not only improves the realism of the simulation model but also reduces later problems caused by design defects. Combining logic unit verification data for circuit logic repair can effectively correct potential errors in the circuit design, thereby ensuring the integrity and reliability of the circuit logic and avoiding errors missed in traditional methods. Finally, through signal transmission simulation, the signal propagation process in the circuit and its performance under different conditions can be analyzed in depth, ensuring that the chip's performance in actual use meets requirements. This process can reveal issues such as signal interference, delay, or loss, which are often overlooked in traditional simulations. Ultimately, the chip simulation model built based on circuit logic data and signal transmission data will provide a more realistic and comprehensive circuit representation for subsequent particle irradiation simulations, thereby improving the prediction accuracy of multiple particle effects (MPIU) and better assessing the chip's reliability in complex radiation environments.

[0019] Preferably, step S16 specifically includes:

[0020] Step S161: Extract logic gate connection relationship features based on circuit logic data to obtain logic gate connection relationship data;

[0021] Step S162: Determine the signal propagation path based on the logic gate connection relationship data to obtain the signal propagation path data;

[0022] Step S163: Identify the longest path based on the signal propagation path data to obtain the longest path data;

[0023] Step S164: Evaluate the propagation delay of the longest path data to obtain propagation delay data;

[0024] Step S165: Adjust the routing based on the propagation delay data for the longest path to obtain routing adjustment data;

[0025] Step S166: Based on the propagation delay data, insert the longest path data into the register to obtain the register data;

[0026] Step S167: Simulate signal transmission based on wiring adjustment data and register data to obtain signal transmission data.

[0027] This invention extracts the connection features of logic gates based on circuit logic data, accurately capturing the relationships between logic gates in a circuit. This provides a clear basis for subsequent signal propagation path identification, ensuring a full understanding of the signal flow path. This step helps identify key components in the circuit structure, avoiding the omission of important signal transmission paths. Next, determining the signal propagation path facilitates a comprehensive analysis of the signal flow and impact within the circuit, identifying potential bottlenecks or interference sources, and optimizing subsequent chip design and simulation processes. Furthermore, identifying the longest path helps pinpoint the most critical path in signal propagation, providing insights into the most vulnerable parts of the entire circuit and guiding design optimization. Propagation delay evaluation based on the longest path data effectively measures the signal propagation delay in the circuit, revealing potential signal delays or performance bottlenecks, which is crucial for ensuring chip stability under high load conditions. At this point, routing adjustments based on propagation delay data optimize signal transmission paths, reducing unnecessary delays and improving overall chip performance and response speed. Register insertion further enhances circuit performance stability, ensuring signal propagation is not affected by time constraints and preventing data loss or errors caused by excessive delays. Ultimately, signal transmission simulation can comprehensively verify whether all optimized designs can function properly under real-world conditions, ensuring stable signal transmission in radiated or complex environments and achieving higher simulation accuracy.

[0028] Preferably, the particle bombardment in step S2 includes:

[0029] Set the particle types and particle energy levels in the chip simulation model;

[0030] Particle flow analysis is performed based on particle energy levels to obtain particle flow data.

[0031] The impact frequency is calculated based on the particle flow data to obtain the particle impact frequency;

[0032] The particle impact frequency is uploaded to the chip simulation model, and the particle bombardment module is run to obtain particle data.

[0033] This invention ensures that simulation results are consistent with actual application environments by appropriately setting particle energy levels. Particle flow analysis based on the set energy levels simulates particle distribution from different types of radiation sources, thereby obtaining accurate particle flow data. This data can be used to calculate the number of particles impacting the chip per unit time, thus obtaining the impact frequency. Impact frequency is a key parameter for evaluating chip reliability, characterizing the cumulative damage that may occur under long-term radiation exposure. Especially in high-energy radiation environments, the cumulative effect of particle bombardment can lead to circuit performance degradation or even failure. After uploading the calculated impact frequency to the simulation model, running the particle bombardment module can further obtain detailed particle interaction data, including particle penetration depth and charge deposition distribution. This data is crucial for evaluating the radiation resistance of the chip's internal circuitry and can also be used to optimize circuit layout and improve anti-interference capabilities.

[0034] Preferably, the energy spectrum classification in step S2 includes:

[0035] Extract energy spectral distribution data from particle data;

[0036] High-energy particle data are screened based on energy spectrum distribution data to identify high-energy particle data.

[0037] Positively charged particle data is obtained by identifying positively charged particles from high-energy particle data.

[0038] A magnetic field was applied to the data of positively charged particles, and their trajectories were analyzed to obtain the trajectory data of positively charged particles.

[0039] Spiral trajectory data is obtained by identifying spiral trajectories based on positively charged particle trajectory data.

[0040] Proton determination is performed on particle data based on spiral trajectory data to generate proton data;

[0041] Scattering effect data are obtained by analyzing the scattering effect data based on the trajectory data of positively charged particles;

[0042] Heavy ion data is generated by determining heavy ions from particle data based on scattering effect data.

[0043] This invention helps obtain a comprehensive understanding of particle energy distribution characteristics by extracting energy spectrum distribution data from particle data, providing a necessary foundation for subsequent particle screening and simulation. High-energy particle screening based on energy spectrum distribution data can accurately distinguish particles with higher energy levels, which have a greater impact on the chip and therefore require special attention in simulation. Further identification of positively charged particles ensures that only particles with strong forces are selected for subsequent simulation, improving the accuracy of the analysis. By simulating the application of a magnetic field to positively charged particle data and analyzing their trajectories, the actual motion paths of the particles can be obtained, thus more realistically reproducing their behavior in the real environment. This process helps to accurately predict particle motion in complex magnetic field environments, providing a more precise reference for the radiation-hardened design of the chip. Further spiral trajectory identification reveals the complex trajectory behavior of particles in a magnetic field, providing stronger data support for the analysis of multi-particle effects. Identifying protons based on spiral trajectory data enables more accurate particle classification, ensuring that proton-like particles can be accurately identified and influence the construction of the chip model. Finally, analysis of the scattering effects based on positively charged particles can further reveal the interaction between particles and the internal structure of the chip, obtaining heavy ion data and thus providing a deeper understanding of multi-particle interaction effects. Through the combined effect of these steps, the chip simulation model can more comprehensively and accurately simulate complex effects in the radiation environment, thereby improving the chip's radiation reliability assessment and fault prediction capabilities.

[0044] Preferably, the single-event upset fault analysis in step S3 includes:

[0045] Proton data is input into the chip simulation model, and chip-proton interaction simulation is performed to obtain chip-proton interaction data;

[0046] Impact points are identified by analyzing chip-proton interaction data.

[0047] Based on the impact point, chip memory bit flipping analysis is performed to obtain memory bit flipping data;

[0048] Based on the impact point, the timing error analysis of the chip trigger is performed to obtain the timing error data of the trigger;

[0049] Hotspot regions are identified in the chip-proton interaction data based on memory bit flip data and trigger timing error data.

[0050] Single-event flip (SIF) fault identification is performed on hotspot areas to obtain SIF data.

[0051] This invention provides concrete data support for the chip's response in a radiation environment by inputting proton data into a chip simulation model and performing chip-proton interaction simulation. This process effectively simulates the actual impact of protons on the chip's internal structure, generating chip-proton interaction data. Impact point identification of this data accurately pinpoints the key locations of particle-chip interactions, providing crucial clues for subsequent fault analysis. Analyzing chip memory bit flips based on impact points promptly detects memory cell anomalies caused by particle impacts, thus identifying potential chip fault sources. Simultaneously, analyzing chip trigger timing errors based on impact points helps reveal timing errors caused by radiation and predict timing problems in harsh environments. Combining memory bit flip data with trigger timing error data allows for hotspot identification of chip-proton interaction data, revealing the areas of the chip most susceptible to radiation. Single-event upset fault identification of these hotspot areas accurately identifies the most radiation-affected parts, providing a basis for chip redundancy design and fault tolerance mechanism optimization, ultimately improving the chip's stability and reliability in complex radiation environments. This comprehensive analysis and simulation allows for a more complete and accurate assessment of a chip's radiation resistance in a radiated environment, and provides practical and effective optimization solutions for chip design.

[0052] Preferably, the multi-particle flip fault analysis in step S3 includes:

[0053] Heavy ion data is input into the chip simulation model, and Monte Carlo multi-particle interaction simulation is performed to obtain multi-particle interaction data.

[0054] Electromagnetic interaction analysis was performed on the multi-particle interaction data to obtain multi-particle electromagnetic interaction data;

[0055] Multi-particle electromagnetic trajectory recognition is performed based on electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data.

[0056] The incident position of the chip simulation model is recorded using multi-particle electromagnetic trajectory data to generate particle incident position data.

[0057] Based on the particle incident position data, a collective flip analysis was performed on the chip simulation model to obtain multi-particle flip fault data.

[0058] This invention obtains multi-particle interaction data by inputting heavy ion data into a chip simulation model and performing Monte Carlo multi-particle interaction simulation. This provides more comprehensive simulation results for the chip's behavior under complex radiation environments. Electromagnetic interaction analysis of this multi-particle interaction data helps reveal the electromagnetic interactions between particles, accurately simulating the interaction effects of multiple particles within the chip, thereby improving the accuracy and reliability of the simulation model. Multi-particle electromagnetic trajectory identification using electromagnetic interaction data can further extract the particle trajectories within the chip, providing precise particle path information for subsequent analysis. Recording the incident positions of the chip simulation model based on this trajectory data allows for detailed recording of the incident position of each particle, enabling analysis of the impact of radiation effects on different areas of the chip. Finally, collective flipping analysis based on particle incident position data can identify flipping faults caused by multi-particle interactions, further revealing the potential threat of multi-particle interaction effects to chip reliability. This process allows for a more comprehensive assessment of the chip's radiation resistance and provides a scientific basis for optimizing chip redundancy design and error correction mechanisms, thereby enhancing the chip's anti-interference capability and stability in radiation environments.

[0059] Preferably, step S4 specifically includes:

[0060] Step S41: Evaluate the radiation reliability of the chip based on the single event flip (SIF) data to obtain the radiation reliability of the SIF chip;

[0061] Step S42: Evaluate the radiation reliability of the chip based on the multi-event flip fault data to obtain the radiation reliability of the multi-event flip chip;

[0062] Step S43: Integrate the radiation reliability of the single-event flip chip and the radiation reliability of the particle flip chip to obtain the chip radiation reliability;

[0063] Step S44: Upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

[0064] This invention assesses chip radiation reliability based on single-event upset (SET) data, accurately quantifying the impact of SETs on chip performance and providing fundamental reliability data for chip performance under radiation environments. Next, it assesses chip radiation reliability based on multi-event upset (MEI) failure data, supplementing the limitations of SETs and considering the potential impact of MEI interactions on the chip, ensuring a more comprehensive stability analysis of the chip under complex radiation environments. This process further helps reveal the chip's vulnerability in real-world scenarios involving multiple particle interactions. By integrating SET and MEI chip radiation reliability, a comprehensive chip radiation reliability assessment result is obtained, providing a scientific basis for the long-term stable operation of the chip in high-radiation environments. Finally, the comprehensive chip radiation reliability is uploaded to a chip simulation model and radiation hardening tests are performed, verifying whether the chip can effectively cope with various radiation effects in real-world environments, thus providing feedback on chip hardening strategies. This process not only enhances the reliability assessment of chips in complex radiation environments but also provides guidance for further optimizing redundancy design and error correction mechanisms in chip design.

[0065] Preferably, step S44 specifically includes:

[0066] Step S441: Upload the chip radiation reliability to the chip simulation model and perform chip redundancy design to obtain chip redundancy data;

[0067] Step S442: Perform integration error detection on the chip redundant data to obtain integration error data;

[0068] Step S443: Correct the data based on the integrated error data to obtain corrected data;

[0069] Step S444: Set the irradiation dose for the chip simulation model to obtain irradiation dose data;

[0070] Step S445: Upload the irradiation dose data and correction data to the chip simulation model, and perform radiation hardening test to generate radiation hardening test data.

[0071] This invention, by uploading chip radiation reliability data to a chip simulation model and implementing redundant design, helps provide higher fault tolerance for chip design, ensuring that the chip can maintain normal function even in high-radiation environments. Next, by integrating error detection into the chip redundancy data, errors in the redundant design can be detected in a timely manner, effectively reducing the negative impact of radiation on chip performance. Correction based on the integrated error data provides the chip with the ability to dynamically adjust the redundant design, ensuring that the chip can adapt and react quickly in different radiation scenarios, thereby avoiding major failures. By setting the irradiation dose in the chip simulation model, the chip's performance under different radiation environments can be simulated, accurately capturing the impact of irradiation dose on chip function and providing data support for further hardening strategies. Finally, uploading the irradiation dose data and correction data to the chip simulation model and performing radiation hardening tests verifies the chip's radiation resistance in actual radiation environments, optimizes its design, and ultimately generates reliable radiation hardening test data, providing more scientific hardening strategies and design schemes. The implementation of this process significantly improves the chip's survivability and long-term stability in complex radiation environments, effectively avoiding the limitations of traditional testing methods that neglect multi-particle interaction effects and error correction capabilities.

[0072] Preferably, this specification also provides a test system for a chip simulation model, used to execute the test method for the chip simulation model as described above. The test system for the chip simulation model includes:

[0073] The chip simulation model construction module includes acquiring chip data and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; and constructing a chip simulation model based on the circuit logic data and signal transmission data.

[0074] The particle bombardment module includes bombarding the chip simulation model with particles to obtain particle data; and classifying the energy spectrum based on the particle data to obtain proton data and heavy ion data.

[0075] The fault analysis module includes performing single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; and performing multi-event flip fault analysis on the chip simulation model based on heavy ion data to obtain multi-event flip fault data.

[0076] The radiation hardening test module includes evaluating the chip's radiation reliability based on single-event flip data and multi-event flip failure data to obtain the chip's radiation reliability; uploading the chip's radiation reliability to the chip simulation model and performing radiation hardening tests to generate radiation hardening test data. Attached Figure Description

[0077] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0078] Figure 1 This is a schematic diagram of the steps in the testing method of the chip simulation model of the present invention;

[0079] Figure 2 This is a detailed flowchart of step S1 in the present invention;

[0080] Figure 3 This is a detailed flowchart of step S16 in the present invention;

[0081] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0082] The technical method of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0083] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0084] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0085] To achieve the above objectives, please refer to Figures 1 to 3 This invention provides a testing method for a chip simulation model, the method comprising the following steps:

[0086] Step S1: Acquire chip data and perform chip circuit logic analysis to obtain circuit logic data; perform signal transmission simulation based on circuit logic data to obtain signal transmission data; construct a chip simulation model based on circuit logic data and signal transmission data.

[0087] In this embodiment, raw circuit data, including circuit schematics, gate circuit information, and register configurations, is extracted from the chip using a dedicated hardware interface tool. Circuit design tools (such as Cadence or Altera) are then used to perform circuit logic analysis on the acquired data, determining the working principle of each logic unit and its connection relationships. During the circuit logic analysis, the input-output signal relationships of each logic gate are given special attention. Gate-level simulation techniques (such as Verilog or VHDL simulation) are used to model the circuit behavior, obtaining circuit logic data. Based on the circuit logic data, signal transmission simulation is then performed. Using simulation tools such as Spice, the propagation of signals in the circuit is simulated based on the circuit topology and the parameters of each logic unit, focusing on factors such as signal delay, impedance matching, and noise interference. The signal transmission data obtained from the simulation results mainly includes signal transmission delay, amplitude variation, and its impact on various components in the circuit. Finally, based on the circuit logic data and signal transmission data, a complete simulation model of the chip is constructed. This step combines the logic analysis and transmission simulation results, generating a logic behavior model of the chip by mapping the circuit's input-output behavior to the model.

[0088] Step S2: Bombard the chip simulation model with particles to obtain particle data; perform energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0089] In this embodiment, solar activity cycle data needs to be obtained, which can be extracted from meteorological or astronomical databases (such as NOAA). Then, based on the solar activity cycle, especially the peak periods of solar activity, the radiation intensity during these periods is statistically analyzed. This data can be obtained using dedicated radiation monitoring equipment (such as Space Weather Prediction Center). Based on this, the particle types and energy levels are set according to the radiation intensity, with high-energy protons and heavy ions as the two main particle types. The particle energy levels are set according to the relationship between radiation intensity and the solar activity cycle, with standard energy levels of 1-10 MeV for protons and 10-100 MeV for heavy ions. Subsequently, the particle flow is analyzed using a particle flow analysis tool (such as Geant4 simulation software) to simulate the flow direction and frequency of particles. Based on the particle flow data, the frequency of each particle impacting the chip is calculated. This frequency is calculated based on the solar radiation intensity and flow model, and the result is provided in the form of impact frequency. Finally, the calculated impact frequencies are uploaded to the chip simulation model, and the particle bombardment module is run to simulate the interaction between particles and the chip, obtaining particle data and recording the collisions and interactions between particles and the chip.

[0090] Step S3: Perform single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; perform multi-event flip fault analysis on the chip simulation model based on heavy ion data to obtain multi-event flip fault data.

[0091] In this embodiment, data obtained from the proton particle stream is input into the chip simulation model. Chip simulation software (such as SPICE or VHDL simulation tools) is used to perform an interaction simulation between the chip and the proton particles, acquiring interaction data between the protons and the chip. This process generates chip-proton interaction data based on the proton's energy, incident angle, and the chip's circuit characteristics (such as memory cells and flip-flop timing). This data is used to further identify memory bit flips at the proton impact point and analyze the resulting flip-flop timing errors. Combining the proton's incident path and velocity, potential "hot spots" in the chip are identified, i.e., locations susceptible to proton influence. Finally, single-event flip faults are identified based on this data, recording the location and type of fault, thus obtaining single-event flip data. For heavy ion data analysis, after the heavy ion particle stream is input into the chip simulation model, a Monte Carlo multi-particle interaction simulation is performed to simulate the impact of multiple particles on the chip. During this simulation, the electromagnetic trajectories of heavy ions and the electromagnetic interactions between multiple particles are analyzed in detail. The multi-particle interaction data is tracked through the electromagnetic interaction model, identifying the trajectories of different particles in the circuit and recording the multi-particle electromagnetic trajectory data. Subsequently, based on these trajectory data, a multi-particle collective flip analysis was further conducted to record the results of the combined action of multiple particles in the chip, thus obtaining multi-particle flip fault data.

[0092] Step S4: Evaluate the chip radiation reliability based on single-event upset (SET) data and multi-event upset (MEI) fault data to obtain the chip radiation reliability; upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

[0093] In this embodiment, radiated reliability is assessed based on data obtained from single-event upset (SEE) failure analysis. The assessment criteria are based on the frequency of failure occurrence, severity of failure, and the circuit region where the failure occurs. For example, for circuit failures caused by SEE, the radiated reliability of SEE is determined by calculating the toggle rate of each memory bit using a model. Then, combined with multi-event upset (MEI) failure data, the impact of MEI failures on circuit reliability is assessed, yielding the chip's radiated reliability in a MEI environment. After the radiated reliability assessment, the chip is hardened using radiation hardening design tools (such as hardened circuit design tools). Based on the assessment results, the chip's radiation tolerance is improved by modifying its redundancy design and increasing fault tolerance. During radiation hardening testing, the chip is simulated using pre-set radiation dose data, and its performance in this environment is tested. Finally, the radiation hardening test data is recorded to determine whether the chip meets the expected radiation hardening standards.

[0094] Preferably, step S1 specifically includes:

[0095] Step S11: Acquire chip data and extract circuit principle features to obtain circuit principle data;

[0096] In this embodiment, raw circuit data, including the circuit schematic, parameters of each circuit element, and interconnection relationships, is extracted from the chip via a dedicated hardware interface. This data is typically stored in chip design files, such as GDSII or LEF file formats, or exported using design software such as EAGLE or Allegro. Circuit analysis tools (such as Cadence Virtuoso or Mentor Graphics) are used to read and analyze the chip's circuit design, extracting the electrical parameters (such as resistance, capacitance, and gain) of each circuit element and their connections. The extraction of circuit principle features includes the types of logic gates, the topology of the wiring, and basic information such as current and voltage. All extracted data is organized into standard-format circuit principle data for subsequent processing.

[0097] Step S12: Detect logic gate relationships based on circuit principle data to obtain logic gate relationship data;

[0098] In this embodiment, based on circuit principle data, circuit logic analysis tools (such as Xilinx Vivado and Cadence Design Systems' RTL compiler tools) are used to detect the relationships between logic gates in the circuit. This process includes identifying each logic gate in the circuit (such as AND gates, OR gates, NOT gates, XOR gates, etc.) and their input and output signals, determining the function of the logic gates, and identifying the signal flow between different logic gates. For this purpose, a standard input / output threshold must first be set, typically 0V for low level and 3.3V for high level. Through logic analysis simulation, the relationship between the output of each logic gate and the input of other logic gates is obtained, generating connection relationship data between logic gates, ultimately forming logic gate relationship data. This data includes the input and output signals of each gate, the electrical connections between gates, and the logic state.

[0099] Step S13: Generate a truth table based on the logic gate relation data to obtain the logic truth table;

[0100] In this embodiment, based on the logic gate relationship data obtained in step S12, a truth table generation tool (such as Boolean Algebra analysis tool or Verilog / VHDL simulator) is used to generate the logic truth table of the chip circuit. Specifically, the input and output of each logic gate are analyzed first, and all input combinations are derived through the combination rules of the logic gates, and the output result under each combination is calculated. The generation of the truth table requires listing all permutations and combinations of inputs. Assuming there are n input signals in a circuit, the number of rows in the truth table will be 2^n, and each row represents the output state under one input combination. Based on the logic gate connection relationship in the circuit principle data, the truth table is automatically generated, recording the output result corresponding to each group of inputs, and finally obtaining the complete logic truth table data.

[0101] Step S14: Perform logic unit verification based on the logic truth table and generate logic unit verification data;

[0102] In this embodiment, each logic unit in the circuit is verified using a generated logic truth table. This step can be performed using automated verification tools (such as ModelSim, VCS, etc.). The verification process involves comparing different combinations of input signals with the truth table to check whether the logic gate outputs match the expected results. Verification of each logic unit requires setting specific test vectors, which are input combinations extracted from the truth table, to verify whether each unit works as intended. During verification, simulation results are compared with theoretical results to determine if there are any logical errors or inconsistencies. The generated verification data includes the input and output results under each test vector, as well as a flag indicating whether the verification passed, ultimately yielding the logic unit verification data.

[0103] Step S15: Based on the logic unit verification data, repair the circuit logic data of the circuit principle data to generate circuit logic data;

[0104] In this embodiment, circuit logic is adjusted and repaired based on errors or inconsistencies recorded in the verification data. For example, if the output of a logic gate does not match the expected result, the logic relationship of its input signals is checked, and the connection of that part of the circuit is corrected or its gate circuit type is changed. During the repair process, circuit design tools (such as CadenceVirtuoso, Synopsys Design Compiler, etc.) automatically recalculate the circuit behavior based on the corrected logic gate relationships, updating the connection method and parameters of each component in the circuit. After the repair is completed, new circuit logic data is generated, containing the repaired circuit logic relationships, and the entire circuit is re-verified to ensure that the repaired circuit can function normally as expected.

[0105] Step S16: Simulate signal transmission based on circuit logic data to obtain signal transmission data;

[0106] In this embodiment, circuit simulation tools (such as SPICE, LTspice, Spectre, etc.) are used to simulate signal transmission based on the repaired circuit logic data. First, the waveform and frequency of the input signal are set to simulate the impact of different input signals on various circuit components. During the simulation, the focus is on analyzing signal delay, transmission rate, signal attenuation, and noise effects in the circuit. Based on the wiring and component parameters in the circuit, the propagation of the signal in the circuit is simulated, calculating the time delay, amplitude, and frequency response of the signal as it passes through each logic gate and component. Through signal transmission simulation, detailed data on signal propagation in the circuit is obtained, including voltage changes and time response data at each node. This data will be used for subsequent chip performance analysis and optimization.

[0107] Step S17: Construct a chip simulation model based on circuit logic data and signal transmission data.

[0108] In this embodiment, firstly, based on the repaired circuit logic data obtained in step S15 and the signal transmission data obtained in step S16, a complete chip simulation model is constructed using simulation modeling tools (such as Cadence Virtuoso, Synopsys HSPICE, etc.). This simulation model includes the circuit structure, the electrical characteristics of components, the connection relationships between logic gates, and detailed parameters of signal transmission. By combining the simulation results of circuit logic and signal transmission in the simulation environment, a complete simulation model that reflects the actual behavior of the chip is constructed. This model can be used for subsequent performance evaluation, fault diagnosis, and optimization design.

[0109] Preferably, step S16 specifically includes:

[0110] Step S161: Extract logic gate connection relationship features based on circuit logic data to obtain logic gate connection relationship data;

[0111] In this embodiment, based on the connection information of each logic gate in the circuit logic data, circuit design software (such as Cadence Virtuoso or Synopsys Design Compiler) is used to parse the logic gates in the circuit and extract their connection relationships. This process includes identifying the input and output signals of each logic gate, analyzing the electrical connections between different logic gates, and determining which signals are transmitted through which logic gates. By extracting all electrical connection information using the circuit design tool, connection relationship data for each logic gate is constructed. The connection relationship data includes detailed information such as the input and output ports of each logic gate, the ID of the logic gate it is connected to, the signal transmission direction, and the topology of the signal lines. To ensure the accuracy of the data, the connection of each logic gate needs to be precisely calibrated, typically by setting input and output signal voltage standards, such as 0V for low level and 3.3V for high level. The final logic gate connection relationship data provides the basis for subsequent steps.

[0112] Step S162: Determine the signal propagation path based on the logic gate connection relationship data to obtain the signal propagation path data;

[0113] In this embodiment, the signal propagation path is determined using logic gate connection relationship data and a signal propagation analysis algorithm. This process involves tracing each signal in the circuit and identifying the transmission path from the input to the output. The determination of the signal propagation path is typically performed using path search algorithms in graph theory, such as Depth-First Search (DFS) or Breadth-First Search (BFS). First, the starting point of the signal is located in the circuit diagram based on its input port. Then, the connection relationships of the signals are used to trace each intermediate and terminal node. During this process, all logic gates and their connected electrical parameters (such as propagation delay, signal attenuation, etc.) need to be recorded and used as characteristics of the signal propagation path. The data for each signal path includes information such as the logic gates traversed, the signal transmission order, and the path length. The signal propagation path data describes the flow of the signal in the circuit, providing a basis for subsequent delay calculations and wiring adjustments.

[0114] Step S163: Identify the longest path based on the signal propagation path data to obtain the longest path data;

[0115] In this embodiment, the longest path in the circuit is identified based on signal propagation path data using a path analysis algorithm (such as Dijkstra's algorithm or Bellman-Ford algorithm). The longest path is the path with the longest signal propagation time from the input to the output. Calculating the longest path requires considering the electrical parameters (such as delay and impedance) of each logic gate and connection in the circuit, and identifying the path with the longest delay by comparing the propagation delay of each path. During the calculation, a threshold standard for propagation delay needs to be set, typically based on a common signal propagation delay range in the circuit (e.g., between 10ns and 50ns). The longest path data includes the starting point, ending point, logic gates traversed, the delay of each gate, and the total cumulative delay. This data provides the foundation for subsequent delay evaluation and routing optimization.

[0116] Step S164: Evaluate the propagation delay of the longest path data to obtain propagation delay data;

[0117] In this embodiment, the process calculates the propagation delay of the signal through each logic gate and its connections in the path to obtain the propagation delay data for the entire path. Delay evaluation is typically performed using circuit simulation tools (such as SPICE simulators or HSPICE). During the evaluation process, delay parameters are first set for each connecting element in the circuit (such as gate circuits, transmission lines, etc.). These parameters can be obtained through circuit model parameters (such as capacitors, inductors, loads, etc.) and process parameters (such as linewidth, line length, etc.). During the evaluation process, the delay of each logic gate is determined by its electrical characteristics, such as drive current and load capacitance. For each signal path, the delay of each element is calculated sequentially, ultimately obtaining the total delay of the entire path. The delay data will include the start time, propagation time, and total delay of each path, and further optimization will be performed based on this data.

[0118] Step S165: Adjust the routing based on the propagation delay data for the longest path to obtain routing adjustment data;

[0119] In this embodiment, the purpose of wiring adjustment is to optimize signal transmission delay and ensure that the circuit can operate normally within a specified clock cycle. During the adjustment process, paths with large delays are first identified based on delay data, and the delay is reduced by changing the layout of the signal lines or adding additional signal amplifiers or drivers. For example, transmission delay can be reduced by shortening the length of long cables, adding buffer circuits, or optimizing the impedance matching of signal channels. During wiring adjustment, an adjustment threshold needs to be set based on the delay calculation results for each path. For example, paths with delays greater than a certain value (e.g., 100ns) need to be adjusted. The final wiring adjustment data will record the adjustment scheme for each path, including the adjusted components, the changed connection methods, and the new delay value.

[0120] Step S166: Based on the propagation delay data, insert the longest path data into the register to obtain the register data;

[0121] In this embodiment, register insertion is performed on the longest path based on the delay data of the signal propagation path. The purpose of register insertion is to reduce delay and enhance signal stability by inserting triggers or registers. First, based on the delay data of each path, paths with excessively long delays are identified, especially those whose delays exceed the system clock cycle. Adding registers to these paths effectively segments the signal transmission, thereby reducing the delay of each segment and avoiding timing errors caused by excessive delays. The register insertion position is usually selected at a suitable point on the path with the longest delay. After the register is inserted, the path is divided into two segments, and the signal is synchronized between the two segments. The register data includes the node position of each inserted register, the type of register, and its control signals, ultimately forming complete register insertion data.

[0122] Step S167: Simulate signal transmission based on wiring adjustment data and register data to obtain signal transmission data.

[0123] In this embodiment, wiring adjustment data and register data are used to simulate signal transmission using a circuit simulation tool. First, the wiring adjustment data obtained in step S165 and the register data obtained in step S166 are input into the simulation model to perform a complete signal transmission simulation. During the simulation, the input signal propagates through the adjusted wiring path and the path through which the registers are inserted. The simulation tool (such as SPICE or Cadence simulator) calculates the voltage change at each node, signal delay, waveform quality, etc. The final signal transmission data includes parameters such as the transmission time, waveform, and signal quality of each signal, used to analyze circuit performance and provide data support for subsequent optimization.

[0124] Preferably, the particle bombardment in step S2 includes:

[0125] Set the particle types and particle energy levels in the chip simulation model;

[0126] In this embodiment, it is necessary to determine the particle type and energy level to accurately simulate the impact of the radiation environment on the chip. Particle types include protons and heavy ions, each corresponding to different radiation sources, such as particle accelerators. The particle energy level needs to be set based on the experimental environment or actual application scenario. For example, the energy level of protons is typically in the range of 1 MeV to 100 MeV, while the energy of heavy ions can reach hundreds of MeV to GeV levels. Energy parameters can be obtained by referring to radiation testing standards, such as NASA's radiation testing specifications or JEDEC's single-event effect (SEE) testing standards. During the simulation, the Monte Carlo method or SRIM (Stopping and Range of Ions in Matter) software is used to calculate the penetration depth and energy deposition of particles in the chip material. For different particle types, the energy loss in the silicon-based material needs to be calculated separately, and the impact of particle energy levels on different circuit components needs to be determined in conjunction with the chip's process node (e.g., 28nm, 16nm, or 7nm).

[0127] Particle flow analysis is performed based on particle energy levels to obtain particle flow data.

[0128] In this embodiment, particle flow analysis tools (such as Geant4 and SRIM) are used to analyze particle flow based on particle type and energy level. A simulation model is used, inputting particle type and energy parameters to simulate the particle propagation process on and within the chip surface. The key to particle flow analysis is calculating the penetration depth, attenuation effect, and interaction with materials in different materials (such as silicon and metals). The analysis requires setting specific material parameters for the chip, such as chip thickness and surface coating type. Particle flow data typically includes information such as particle distribution density, flux, and penetration depth, which provide crucial information for calculating particle impact frequencies.

[0129] The impact frequency is calculated based on the particle flow data to obtain the particle impact frequency;

[0130] In this embodiment, particle flow data is used to calculate the particle impact frequency. The particle impact frequency refers to the number of times a particle impacts the chip surface and its internal electronic structure per unit time. First, using information such as particle flux and particle energy from the particle flow data, combined with the chip's surface characteristics (such as area and material thickness), the total number of particle impacts is calculated. Specifically, the number of impacts can be determined using the geometric relationship between the particle flow density and the chip surface contact. For example, when the particle flow density is a certain value, the impact frequency per unit time is calculated based on the chip area, combined with the particle velocity and energy. This process involves simulating the interaction between particles and the chip surface to obtain accurate impact frequency data.

[0131] The particle impact frequency is uploaded to the chip simulation model, and the particle bombardment module is run to obtain particle data.

[0132] In this embodiment, the chip simulation model is typically created using circuit simulation tools (such as Cadence, Synopsys, etc.) and combined with a particle flow analysis module to simulate particle bombardment. When uploading the particle impact frequency, it needs to be specified as an input parameter to the chip's physical simulation module. When running the particle bombardment module, the simulation tool will simulate the interaction between particles and chip materials, including particle scattering, damage, and energy transfer. Based on the simulation results, data on the impact of particles on the chip are obtained, typically with energy loss, scattering angle, and damage area as the main output parameters. Finally, the obtained particle data can be used to further evaluate the chip's radiation hardness or for process optimization.

[0133] Preferably, the energy spectrum classification in step S2 includes:

[0134] Extract energy spectral distribution data from particle data;

[0135] In this embodiment, the particle stream data contains energy information for each particle type. By statistically analyzing and classifying this data, the energy spectrum distribution is obtained. Specifically, an energy range (e.g., 1 MeV to 100 MeV) is defined, and the number of particles within each energy range is counted. Data processing software (e.g., Matlab, or the NumPy library in Python) is used to group the data and calculate the number of particles within each energy range, thus obtaining the energy spectrum distribution data. The criteria for dividing the energy ranges can refer to physics literature or experimental data, and the number of particles in each range is set to a fixed step size (e.g., every 5 MeV is one range). The obtained energy spectrum data can be visualized using histograms or graphs for further analysis of the particle energy distribution.

[0136] High-energy particle data are screened based on energy spectrum distribution data to identify high-energy particle data.

[0137] In this embodiment, an energy screening threshold is set when screening high-energy particles based on energy spectrum distribution data. For example, particles with energies greater than 50 MeV are defined as high-energy particles. By screening the energy spectrum distribution data, particles with energies higher than the set threshold are selected to form high-energy particle data. In practice, a programming language (such as Python or Matlab) is used to implement the screening function, iterating through each particle data and determining whether its energy is greater than the set 50 MeV threshold. If so, the particle data is added to the high-energy particle data set. Through this process, high-energy particles can be distinguished from low-energy particles, laying the foundation for subsequent particle type analysis.

[0138] Positively charged particle data is obtained by identifying positively charged particles from high-energy particle data.

[0139] In this embodiment, when identifying positively charged particles in high-energy particle data, the particles are filtered based on their charge number. Particles can be identified based on their charge characteristics (e.g., protons, electrons, etc.) by their physical properties. Specifically, the particle type information (e.g., protons, electrons, alpha particles, etc.) in the high-energy particle data is first used to filter out positively charged particles. For each particle, its charge number is checked for a positive value (e.g., a proton's charge is +1). If the particle's charge is positive, it is classified as a positively charged particle, and its relevant data, including particle energy, type, and velocity, is stored. The resulting set of positively charged particle data can provide foundational data for subsequent magnetic field simulation and trajectory analysis.

[0140] A magnetic field was applied to the data of positively charged particles, and their trajectories were analyzed to obtain the trajectory data of positively charged particles.

[0141] In this embodiment, a magnetic field model is established, typically using a uniform or non-uniform magnetic field model. The magnetic field strength and direction are set according to the actual application requirements. For example, the magnetic field strength is set to 0.5T, and the direction is perpendicular to the particle's motion direction. A physical simulation software (such as Geant4 or COMSOL) is used to simulate the magnetic field. The initial state of the positively charged particles (such as velocity, direction, and energy) is input into the simulation system to simulate the particle's trajectory in the magnetic field. During the simulation, the influence of the magnetic field force on the particle's motion is calculated. The force on the particle is calculated using the Lorentz force formula (F = q(v × B)), thus obtaining the particle's trajectory in the magnetic field. By analyzing the particle's trajectory, data such as the motion path, velocity change, and trajectory curvature of each particle can be obtained, ultimately generating the trajectory data of the positively charged particles.

[0142] Spiral trajectory data is obtained by identifying spiral trajectories based on positively charged particle trajectory data.

[0143] In this embodiment, during the spiral trajectory recognition process based on positively charged particle trajectory data, the positional information of the particle trajectory needs to be extracted first to obtain the three-dimensional coordinates of the particle at different time steps. By analyzing the differences between two adjacent positions, the direction of particle motion, i.e., the tangent direction, can be determined. To capture the geometric characteristics of particle motion, the angle between adjacent tangents also needs to be calculated to determine whether the particle exhibits periodic rotational behavior. If the angle between adjacent tangents changes significantly, it can be inferred that the particle is undergoing rotational motion. Next, by analyzing the angle changes of the particle trajectory in detail, it is determined whether there is continuous rotation and whether these rotations form a spiral trajectory. Specifically, the threshold for rotation angle change is usually set to 15° to 25°, that is, when the angle change between adjacent positions exceeds this range, it can be determined as a spiral trajectory. If the particle trajectory exhibits consistent rotational characteristics over multiple periods, and these rotations present a spiral shape in the plane, the trajectory can be confirmed as a spiral trajectory. After confirming the spiral trajectory, the rotation period and trajectory length also need to be calculated. The rotation period can be obtained by analyzing the periodic changes of rotational motion in the particle trajectory. Common period thresholds are 50 to 200 time steps, with the specific value depending on the particle's motion characteristics. The trajectory length is calculated by summing the spatial distances between the particle's various points during its motion. A minimum trajectory length threshold of 10 to 50 meters is typically set to ensure the trajectory forms a complete spiral shape. Ultimately, this information, including the rotation period and trajectory length, will be stored and used for subsequent analysis and applications.

[0144] Proton determination is performed on particle data based on spiral trajectory data to generate proton data;

[0145] In this embodiment, the mass and charge characteristics of particles in the spiral trajectory data are examined. A proton is a positively charged particle with a mass of 1.67 × 10^-27 kg. By judging the mass and charge of a particle, if it matches the physical parameters of a proton, the particle is identified as a proton. During implementation, combined with the parameters of the proton model, based on the particle velocity, trajectory radius, rotation period, and other characteristics in the spiral trajectory data, it is further determined whether it is a proton particle. All particle data that meets the conditions will be classified as proton data, generating a proton dataset containing the velocity, position, trajectory information, etc., of each proton.

[0146] Scattering effect data are obtained by analyzing the scattering effect data based on the trajectory data of positively charged particles;

[0147] In this embodiment, the propagation of particles in different substances is simulated, and the scattering probability of particles interacting with atomic nuclei is calculated. The Monte Carlo method is used to simulate the particle trajectory multiple times, recording the scattering angle and the energy of the scattered particle after each interaction. During implementation, a scattering threshold is set; if the collision angle between the particle and the atomic nucleus exceeds a certain set value, scattering is considered to have occurred. By progressively analyzing the particle trajectory, data such as energy loss and angle changes for each particle during scattering are obtained, ultimately generating scattering effect data, including information on trajectory changes and energy changes during scattering.

[0148] Heavy ion data is generated by determining heavy ions from particle data based on scattering effect data.

[0149] In this embodiment, particle type identification is performed by analyzing energy loss and trajectory changes in scattering effect data, combined with the physical characteristics of heavy ions (such as mass and energy loss rate). Heavy ions have a large mass and a low velocity, and typically have a greater energy loss compared to electrons and protons. In practice, based on the energy loss rate of particles in the scattering effect data, if a particle has a large energy loss and a small trajectory curvature, it is considered a heavy ion. Finally, particles that meet the criteria are classified as heavy ion data, and a corresponding heavy ion dataset is generated, containing information such as particle mass, energy, and trajectory.

[0150] Preferably, the single-event upset fault analysis in step S3 includes:

[0151] Proton data is input into the chip simulation model, and chip-proton interaction simulation is performed to obtain chip-proton interaction data;

[0152] In this embodiment, it is necessary to obtain the physical parameters of the protons, such as energy, incident angle, and the number density of the proton stream. These parameters can be obtained through particle accelerator experiments or by querying existing databases. In the chip simulation model, the initial conditions for the protons are set, including their velocity, mass, angle, and the calculation interval for each time step. The simulation model uses the Monte Carlo method to simulate the interaction between the protons and the chip, calculating the proton's penetration path within the chip. Through numerical integration, the collisions of protons with silicon atoms within the chip are simulated, calculating the energy transfer and particle trajectory changes after each collision. The simulation results are output as proton-chip interaction data, including the proton's energy loss within the chip, particle trajectory, and secondary particle generation information.

[0153] Impact points are identified by analyzing chip-proton interaction data.

[0154] In this embodiment, the chip structure through which protons penetrate is meshed. Each mesh cell is set to 1mm × 1mm in size, and the intersection points between the protons and the chip surface or internal structure are extracted using simulation data. For each collision, the relative positional relationship between the proton incident position and the chip surface or structure is calculated. By determining whether the proton energy at that point has undergone sufficient attenuation, a valid impact point is determined. An impact point is defined as a collision location with energy greater than a set threshold (e.g., 10keV), and regions meeting this condition are recorded as impact points. If multiple proton collisions occur at a location, that location is recorded as a repeated impact point. The impact points are ultimately saved as a dataset containing the coordinates and corresponding energy value of each valid impact point.

[0155] Based on the impact point, chip memory bit flipping analysis is performed to obtain memory bit flipping data;

[0156] In this embodiment, the physical location of each memory cell is extracted based on the chip structure diagram, and these memory cells are matched with impact points. When an impact point lands on a memory cell, the memory bits of that cell flip. The probability of flipping depends on the magnitude and location of the impact energy, as well as the sensitivity of the memory cell (e.g., a threshold of 50 keV / cm). 2 The impact energy density is relevant. If the energy at the impact point is greater than a set flip threshold, the memory bit of that memory cell is considered to have flipped. Flip data records the state change of each memory cell (from 0 to 1 or from 1 to 0) and is marked with a timestamp and location. The memory bit flip data is stored as a structured dataset, including the state of each memory cell and the specific time the flip occurred.

[0157] Based on the impact point, the timing error analysis of the chip trigger is performed to obtain the timing error data of the trigger;

[0158] In this embodiment, timing error analysis of the chip flip-flop is implemented by identifying the spatial relationship between the impact point and the flip-flop. Timing errors in the flip-flops are caused by voltage fluctuations due to proton collisions, typically occurring near the rising or falling edge of the clock signal. Based on the chip design, the physical location and timing characteristics of each flip-flop (e.g., a clock frequency of 2GHz) are extracted. Then, the energy of the impact point is compared with the flip-flop's sensitivity (e.g., 10keV / cm²). 2 The system compares the energy threshold of the trigger with the energy level of the trigger to determine if the impact is strong enough to affect the timing of the trigger. If the energy of an impact point exceeds the timing error threshold and its location spatially overlaps with the trigger, a timing error is recorded for that trigger. Specific data for the timing error includes the time of the erroneous trigger, the location of the relevant trigger, the error type (such as rising edge error or falling edge error), and the original timing data of the trigger.

[0159] Hotspot regions are identified in the chip-proton interaction data based on memory bit flip data and trigger timing error data.

[0160] In this embodiment, memory bit flip-flop data and trigger timing error data are mapped to the physical regions of the chip, and the frequency of flip-flops and errors in each region is calculated. Hotspot regions refer to areas where flip-flops and timing errors frequently occur within the same region. These regions typically appear in specific locations on the chip (such as near the chip edge or the core processing area). Because these regions are significantly affected by proton flux density and energy distribution, flip-flop and error events are concentrated. Based on a set threshold (e.g., regions with more than 5 flip-flops and more than 10 timing errors), the physical regions of the chip are divided into blocks, and hotspot regions are marked. The identification results for each hotspot region include the region's coordinate range, the total number of flip-flop and timing error events, and the energy distribution characteristics of the region.

[0161] Single-event flip (SIF) fault identification is performed on hotspot areas to obtain SIF data.

[0162] In this embodiment, the memory cells and triggers within each hotspot region are refined according to their physical locations, and the flip-flop data of each region is compared to determine whether each flip-flop is caused by a single particle. Based on the energy and location of the proton impact point and the characteristics of the chip, it is determined whether each flip-flop meets the criteria for a single-event flip-flop (SIF) fault. If flip-flops are frequent and concentrated within a hotspot region, and the occurrence time of each flip-flop is close, it can be inferred that a SIF fault exists in that region. The SIF data record includes the location, time, fault type (such as memory bit flip-flop or trigger timing error), and energy characteristics of the proton incident for each fault. The SIF fault data is ultimately stored in structured data format for easy subsequent analysis and fault diagnosis.

[0163] Preferably, the multi-particle flip fault analysis in step S3 includes:

[0164] Heavy ion data is input into the chip simulation model, and Monte Carlo multi-particle interaction simulation is performed to obtain multi-particle interaction data.

[0165] In this embodiment, the physical parameters of heavy ions are acquired, including particle energy, velocity, mass, and particle density. These parameters can be obtained through particle accelerator experiments or by querying existing databases. The initial incident conditions of heavy ions, such as the incident angle and the number of particles, need to be set according to the simulation requirements. These parameters are input into the chip simulation model, which uses the Monte Carlo method to simulate multi-particle interactions. The Monte Carlo method simulates the propagation path of particles in the chip and their interaction with material atoms through random sampling. The model calculates the collision events between each heavy ion and silicon atoms as it penetrates the chip, recording the energy loss and location of each collision. Through multiple simulations, multi-particle interaction data is generated, which includes details of the interaction between heavy ions and chip materials, such as the energy loss, scattering angle, and penetration depth of each particle.

[0166] Electromagnetic interaction analysis was performed on the multi-particle interaction data to obtain multi-particle electromagnetic interaction data;

[0167] In this embodiment, information such as the path, energy loss, and incident angle of heavy ion particles is extracted and analyzed in conjunction with the electromagnetic properties of the chip. Using an electromagnetic field solver (such as the finite element method or boundary element method), the electromagnetic effects generated by each particle in the chip are calculated, particularly the electric and magnetic fields generated during heavy ion penetration. To accurately describe the electromagnetic effects, the electrical properties of the chip (e.g., dielectric constant, conductivity) need to be obtained experimentally or from materials databases. During the electromagnetic interaction analysis, special attention is paid to the interaction between particles and electrons in the chip, which leads to phenomena such as charge excitation and recombination. Ultimately, the obtained electromagnetic interaction data includes information such as the electromagnetic field strength, magnetic field direction, and source distribution generated during the penetration of each particle. This data provides the basis for subsequent analysis of electromagnetic interference.

[0168] Multi-particle electromagnetic trajectory recognition is performed based on electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data.

[0169] In this embodiment, an algorithm for electromagnetic trajectory recognition is set up. Using known electromagnetic field strength and information such as particle mass and charge, the trajectory of each particle under the action of electromagnetic force is calculated. This process employs the particle motion equation, combined with the electromagnetic field strength, and uses the Euler method or the fourth-order Runge-Kutta method for numerical integration. By repeatedly calculating the particle's trajectory in the electromagnetic field, the actual motion path of each particle inside the chip is obtained, and its specific penetration position within the chip is determined. For each particle, the electromagnetic trajectory data records its motion time, position, and the process of interaction with the electric and magnetic fields. The trajectory data includes the complete path of each particle from the incident point to the penetration point. If a trajectory shows curvature or deviates from its original path, it indicates that the particle has undergone significant deviation under the action of the electromagnetic field, and this information is specifically marked.

[0170] The incident position of the chip simulation model is recorded using multi-particle electromagnetic trajectory data to generate particle incident position data.

[0171] In this embodiment, multi-particle electromagnetic trajectory data is recorded by analyzing the initial incident positions of the particles. When each particle enters the chip from the outside, its incident position needs to be aligned with the coordinate system of the chip model to obtain the three-dimensional coordinates of the incident point. The starting position of each particle's trajectory is calculated, and the incident point data is stored according to the geometry of the chip model. The incident position data is recorded as a three-dimensional coordinate set, including the position of the particle incident on the chip surface, the angle of particle incident, and the angle between the particle and the chip surface normal. The incident angle is calculated based on the angle between the direction of particle incident and the chip surface normal; the data accuracy of the incident position needs to reach 0.1 mm. The incident position of each particle is recorded in the corresponding coordinate system of the chip model, providing a basis for subsequent flip analysis.

[0172] Based on the particle incident position data, a collective flip analysis was performed on the chip simulation model to obtain multi-particle flip fault data.

[0173] In this embodiment, the incident position of each particle is spatially matched with the chip's memory cell to determine whether the particle has collided with the memory cell. If the incident point is located within the memory cell region, the particle will trigger a memory bit flip. The flip analysis relies on the sensitivity parameters of the chip's memory cell, such as the energy flip threshold of the memory cell (typically set to 50 keV / cm). 2 If the energy density at the particle impact point exceeds a certain threshold, the memory bit of that memory cell will flip. Collective flip analysis calculates the flip probability of each memory cell based on multiple particle incident data and identifies collective flip events, i.e., flip failures caused by multiple particles in the same area. Collective flip data records include the location, frequency, type of affected memory cell, and time of the flip. This data helps identify high-risk areas in the chip and provides a basis for subsequent troubleshooting.

[0174] Preferably, step S4 specifically includes:

[0175] Step S41: Evaluate the radiation reliability of the chip based on the single event flip (SIF) data to obtain the radiation reliability of the SIF chip;

[0176] In this embodiment, the data is obtained from a chip simulation model. This data records information such as the interaction events between each particle and the chip material, the incident position, and the energy. When evaluating the radiation reliability of the chip, it is necessary to calculate the impact of each single-particle flip on the chip's stability. First, the flip threshold of the memory cell is determined. This threshold is determined by the electrical characteristics of the chip design and is typically set to 50 keV / cm².2 Then, based on single-event upset (SET) data, the flip probability of each particle impact on the memory cell is analyzed. Specifically, the probability of a memory bit flip is calculated by comparing the particle's energy density with the memory cell's sensitivity parameter. Further, based on the flip probability of each memory cell, a weighted average method is used to evaluate the overall chip's radiation reliability, yielding the chip's radiation reliability under SET conditions. During the calculation, the occurrence rates of all flip events are weighted according to the type, number, and distribution of the memory cells, finally obtaining a comprehensive radiation reliability value.

[0177] Step S42: Evaluate the radiation reliability of the chip based on the multi-event flip fault data to obtain the radiation reliability of the multi-event flip chip;

[0178] In this embodiment, multi-event upset (MEI) fault data is analyzed based on the impact of multiple particles on memory cells within the same region. When assessing the radiation reliability of the chip due to MEI, it is necessary to calculate the collective flip probability of the memory cells caused by the particle swarm. First, the affected area of ​​each memory cell in the MEI data is identified. For each memory cell, the probability of MEI occurring under given conditions is calculated, taking into account the energy distribution, incident angle, and number of particles. The flip probability of different particle swarms is calculated using a weighted average method to obtain the flip frequency of the memory cells. Based on this, the overall radiation reliability of the chip is calculated using the chip's overall design rules and fault tolerance capabilities. The impact of MEI differs from that of single-event upsets (SE), requiring greater consideration of collective effects; therefore, the interaction effects between particles are added during the calculation. The final radiation reliability assessment value reflects the chip's vulnerability to MEI.

[0179] Step S43: Integrate the radiation reliability of the single-event flip chip and the radiation reliability of the particle flip chip to obtain the chip radiation reliability;

[0180] In this embodiment, single-event upset (SET) radiation reliability and multiple-event upset (MEI) radiation reliability are set as two independent parameters. The importance weights of these two parameters are determined based on the chip's operating environment, radiation conditions, and external factors. For example, in certain high-radiation environments, the impact of MEI is more significant, therefore, MEI radiation reliability is assigned a higher weight. Then, the two reliability values ​​are combined using a weighted average method to obtain a comprehensive radiation reliability value. This value reflects the overall radiation reliability of the chip under different particle upset conditions. During the synthesis, considering that different types of faults have different impacts on chip functionality, different weights need to be set for different fault types. For example, SET has a greater impact on low-power memory cells, while MEI poses a greater risk to high-frequency logic cells.

[0181] Step S44: Upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

[0182] In this embodiment, the comprehensive radiation reliability value needs to be input into the chip simulation software. This data serves as input to the model and affects the chip's performance in a radiation environment during simulation. During upload, it is crucial to ensure that the simulation model matches the actual hardware design, and all relevant physical parameters, such as chip material properties, electrical parameters, and memory cell characteristics, must be accurately imported. In the simulation, radiation hardening tests are performed based on the radiation reliability value. This test simulates the chip's response under different radiation intensities and types (such as heavy ion or neutron radiation). During the test, the chip simulation model will simulate the impact of radiation on memory cells, logic circuits, and other critical functional units. Special attention is paid to whether the chip experiences fatal failures or performance degradation under high radiation environments. The test results record the chip's reliability data under different radiation conditions, such as the number of flip-flops and performance degradation. This data will serve as the basis for chip hardening design and future optimization. After the test is completed, detailed radiation hardening test data will be generated, including chip performance, failure types, and failure distribution information under each radiation condition.

[0183] Preferably, step S44 specifically includes:

[0184] Step S441: Upload the chip radiation reliability to the chip simulation model and perform chip redundancy design to obtain chip redundancy data;

[0185] In this embodiment, the uploaded radiation reliability data includes a comprehensive evaluation value of single-event and multi-event flips (SETs). Based on this data, chip redundancy design is performed. First, the key modules of the chip are identified, including memory cells, logic circuits, and communication interfaces. Then, based on the radiation reliability of each module, redundancy design is applied to high-risk modules. For example, if the flip probability of a memory cell is high (e.g., exceeding 0.5%), a redundant backup unit is designed near that cell. Redundancy design can be achieved by increasing the number of memory bits, replicating memory cells, or using bit error correction mechanisms. The parameters for redundancy design include redundancy coefficients (e.g., 2×redundancy or 3×redundancy) and the physical location of the redundant modules to ensure they do not interact with the main module. Finally, after completing the chip redundancy design, chip redundancy data is generated, which contains the specific content and structural layout of the redundancy design for each module.

[0186] Step S442: Perform integration error detection on the chip redundant data to obtain integration error data;

[0187] In this embodiment, a fault tolerance threshold is set for each redundant module, such as setting the maximum number of flips each redundant storage unit can tolerate (e.g., 10 flips). Next, simulation tests are conducted to simulate the operation of the redundant modules under various radiation environments, checking whether the redundant modules perform backups as expected. The following aspects are keyly checked: 1) Whether the redundant modules can successfully take over tasks when the main module fails; 2) Whether the redundant modules can effectively handle errors and prevent system crashes; 3) Whether there is mutual interference between redundant modules. By testing each function of the redundant modules one by one, the types of errors that occur are detected and recorded, such as storage unit flips or logic circuit failures. Finally, integrated error data is obtained, including the error types, frequency of occurrence, and scope of impact of the redundant modules.

[0188] Step S443: Correct the data based on the integrated error data to obtain corrected data;

[0189] In this embodiment, errors in each redundant module are categorized to determine which errors are caused by design flaws in the redundant modules and which are caused by other factors (such as changes in the radiation environment). Design flaws, such as resource conflicts or hardware failures between redundant modules, are corrected by adjusting the structure of the redundant modules. Correction methods include: 1) adding more redundant modules; 2) adjusting the physical layout of the redundant modules to ensure that different redundant units do not interfere with each other; and 3) introducing more fault-tolerant mechanisms, such as using error-correcting codes (ECC). After correction, the effectiveness of the correction is verified through re-simulation testing, and the error types and frequencies of the redundant modules are re-recorded. Through this process, corrected data is finally obtained, which includes all corrected redundant module configurations, structural adjustments, and corrected redundant module performance indicators.

[0190] Step S444: Set the irradiation dose for the chip simulation model to obtain irradiation dose data;

[0191] In this embodiment, the initial irradiation dose is determined based on the chip's operating environment and the expected radiation level. For example, a dose of 1×10⁻⁶ is set. 14Radius (rad) is used as the baseline irradiance dose. Then, in the simulation model, adjustments are made based on different operating conditions, such as chip operating temperature and expected radiation type (e.g., neutrons, protons, or heavy ions). Each radiation type has a different impact on the chip; therefore, the irradiance dose should be allocated according to the radiation type and the sensitivity of the chip materials to ensure the simulation model can realistically simulate the actual radiation environment. For example, when the chip is in a space environment, due to the stronger space radiation, a higher irradiance dose needs to be set, usually dynamically adjusted according to time, radiation type, and environmental changes. Furthermore, chip design includes radiation shielding measures; these shielding materials reduce the impact of radiation on the chip, so the shielding effect should be considered when setting the irradiance dose. Redundant system design also affects the irradiance dose, as different modules withstand different irradiance levels. Therefore, the irradiance dose should be allocated reasonably to ensure the effectiveness of the redundancy design.

[0192] Step S445: Upload the irradiation dose data and correction data to the chip simulation model, and perform radiation hardening test to generate radiation hardening test data.

[0193] In this embodiment, irradiation dose data and correction data are uploaded to the chip simulation model. After uploading, radiation hardening testing is performed. During the test, the simulation model simulates the chip's operating state under a set irradiation dose, taking into account the impact of all redundancy designs and correction measures. During the test, a specific radiation environment simulation tool is used to apply the irradiation dose to each chip module, including memory units, logic circuits, and interface modules. The focus of the radiation hardening test is to evaluate the effectiveness of redundancy designs and correction data in a high-radiation environment and observe whether the chip can maintain stable operation under various radiation conditions. During the simulation, information such as the fault type, fault time point, and module performance changes for each module is recorded. Finally, radiation hardening test data is generated, including the chip's performance under different irradiation doses and radiation types. The test results will provide a basis for further hardening design optimization.

[0194] Preferably, this specification also provides a test system for a chip simulation model, used to execute the test method for the chip simulation model as described above. The test system for the chip simulation model includes:

[0195] The chip simulation model construction module includes acquiring chip data and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; and constructing a chip simulation model based on the circuit logic data and signal transmission data.

[0196] The particle bombardment module includes bombarding the chip simulation model with particles to obtain particle data; and classifying the energy spectrum based on the particle data to obtain proton data and heavy ion data.

[0197] The fault analysis module includes performing single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; and performing multi-event flip fault analysis on the chip simulation model based on heavy ion data to obtain multi-event flip fault data.

[0198] The radiation hardening test module includes evaluating the chip's radiation reliability based on single-event flip data and multi-event flip failure data to obtain the chip's radiation reliability; uploading the chip's radiation reliability to the chip simulation model and performing radiation hardening tests to generate radiation hardening test data.

[0199] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0200] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A testing method for a chip simulation model, characterized in that, Includes the following steps: Step S1: Acquire chip data and perform chip circuit logic analysis to obtain circuit logic data; Signal transmission data is obtained by simulating signal transmission based on circuit logic data. A chip simulation model is constructed based on circuit logic data and signal transmission data; Step S2: Bombard the chip simulation model with particles to obtain particle data; perform energy spectrum classification based on the particle data to obtain proton data and heavy ion data; Step S3: Perform single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; Multi-particle flip-flop (MPF) fault analysis was performed on the chip simulation model based on heavy ion data, yielding MPF fault data, including: Heavy ion data is input into the chip simulation model, and Monte Carlo multi-particle interaction simulation is performed to obtain multi-particle interaction data. Electromagnetic interaction analysis was performed on the multi-particle interaction data to obtain multi-particle electromagnetic interaction data; Multi-particle electromagnetic trajectory recognition is performed based on electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data. The incident position of the chip simulation model is recorded using multi-particle electromagnetic trajectory data to generate particle incident position data. Based on the particle incident position data, a collective flip analysis was performed on the chip simulation model to obtain multi-particle flip fault data. Step S4: Evaluate the chip radiation reliability based on single-event upset (SET) data and multi-event upset (MEI) fault data to obtain the chip radiation reliability; upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

2. The testing method for the chip simulation model according to claim 1, characterized in that, Step S1 is as follows: Step S11: Acquire chip data and extract circuit principle features to obtain circuit principle data; Step S12: Detect logic gate relationships based on circuit principle data to obtain logic gate relationship data; Step S13: Generate a truth table based on the logic gate relation data to obtain the logic truth table; Step S14: Perform logic unit verification based on the logic truth table and generate logic unit verification data; Step S15: Based on the logic unit verification data, repair the circuit logic data of the circuit principle data to generate circuit logic data; Step S16: Simulate signal transmission based on circuit logic data to obtain signal transmission data; Step S17: Construct a chip simulation model based on circuit logic data and signal transmission data.

3. The testing method for the chip simulation model according to claim 2, characterized in that, Step S16 is as follows: Step S161: Extract logic gate connection relationship features based on circuit logic data to obtain logic gate connection relationship data; Step S162: Determine the signal propagation path based on the logic gate connection relationship data to obtain the signal propagation path data; Step S163: Identify the longest path based on the signal propagation path data to obtain the longest path data; Step S164: Evaluate the propagation delay of the longest path data to obtain propagation delay data; Step S165: Adjust the routing based on the propagation delay data for the longest path to obtain routing adjustment data; Step S166: Based on the propagation delay data, insert the longest path data into the register to obtain the register data; Step S167: Simulate signal transmission based on wiring adjustment data and register data to obtain signal transmission data.

4. The testing method for the chip simulation model according to claim 1, characterized in that, The particle bombardment described in step S2 includes: Set the particle types and particle energy levels in the chip simulation model; Particle flow analysis is performed based on particle energy levels to obtain particle flow data. The impact frequency is calculated based on the particle flow data to obtain the particle impact frequency; The particle impact frequency is uploaded to the chip simulation model, and the particle bombardment module is run to obtain particle data.

5. The testing method for the chip simulation model according to claim 1, characterized in that, The energy spectrum classification mentioned in step S2 includes: Extract energy spectral distribution data from particle data; High-energy particle data are screened based on energy spectrum distribution data to identify high-energy particle data. Positively charged particle data is obtained by identifying positively charged particles from high-energy particle data. A magnetic field was applied to the data of positively charged particles, and their trajectories were analyzed to obtain the trajectory data of positively charged particles. Spiral trajectory data is obtained by identifying spiral trajectories based on positively charged particle trajectory data. Proton determination is performed on particle data based on spiral trajectory data to generate proton data; Scattering effect data are obtained by analyzing the scattering effect data based on the trajectory data of positively charged particles; Heavy ion data is generated by determining heavy ions from particle data based on scattering effect data.

6. The testing method for the chip simulation model according to claim 1, characterized in that, The single-event upset fault analysis in step S3 includes: Proton data is input into the chip simulation model, and chip-proton interaction simulation is performed to obtain chip-proton interaction data; Impact points are identified by analyzing chip-proton interaction data. Based on the impact point, chip memory bit flipping analysis is performed to obtain memory bit flipping data; Based on the impact point, the timing error analysis of the chip trigger is performed to obtain the timing error data of the trigger; Hotspot regions are identified in the chip-proton interaction data based on memory bit flip data and trigger timing error data. Single-event flip (SIF) fault identification is performed on hotspot areas to obtain SIF data.

7. The testing method for the chip simulation model according to claim 1, characterized in that, Step S4 is as follows: Step S41: Evaluate the radiation reliability of the chip based on the single event flip (SIF) data to obtain the radiation reliability of the SIF chip; Step S42: Evaluate the radiation reliability of the chip based on the multi-event flip fault data to obtain the radiation reliability of the multi-event flip chip; Step S43: Integrate the radiation reliability of the single-event flip chip and the radiation reliability of the multi-event flip chip to obtain the chip radiation reliability; Step S44: Upload the chip radiation reliability to the chip simulation model and perform radiation hardening test to generate radiation hardening test data.

8. The testing method for the chip simulation model according to claim 7, characterized in that, Step S44 is as follows: Step S441: Upload the chip radiation reliability to the chip simulation model and perform chip redundancy design to obtain chip redundancy data; Step S442: Perform integration error detection on the chip redundant data to obtain integration error data; Step S443: Correct the data based on the integrated error data to obtain corrected data; Step S444: Set the irradiation dose for the chip simulation model to obtain irradiation dose data; Step S445: Upload the irradiation dose data and correction data to the chip simulation model, and perform radiation hardening test to generate radiation hardening test data.

9. A testing system for a chip simulation model, characterized in that, The test system for executing the chip simulation model as described in claim 1 includes: The chip simulation model construction module includes acquiring chip data and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; and constructing a chip simulation model based on the circuit logic data and signal transmission data. The particle bombardment module includes bombarding the chip simulation model with particles to obtain particle data; and classifying the energy spectrum based on the particle data to obtain proton data and heavy ion data. The fault analysis module includes performing single-event flip fault analysis on the chip simulation model based on proton data to obtain single-event flip data; and performing multi-event flip fault analysis on the chip simulation model based on heavy ion data to obtain multi-event flip fault data. The radiation hardening test module includes evaluating the chip's radiation reliability based on single-event flip data and multi-event flip failure data to obtain the chip's radiation reliability; uploading the chip's radiation reliability to the chip simulation model and performing radiation hardening tests to generate radiation hardening test data.

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