Power semiconductor chip reflow method and system

Abstract

The present invention provides a power semiconductor chip reflow soldering method and system. The power semiconductor chip reflow soldering method includes: placing a power semiconductor chip to be soldered in a reflow furnace, and allowing the power semiconductor chip to be soldered to adhere to the solder; performing a heating operation; performing a vacuum operation; performing a cooling operation; and taking out the power semiconductor module. After performing the i-th vacuum operation, the air pressure value P(i) is reached; the interval time between two vacuum operations is in the range of [3s, 10s]; 2≤N≤4; P(1) is in the range of [40000Pa, 65000Pa]; P(N) is in the range of [50Pa, 45000Pa]; P(1)>P(2)>……>P(N); the first, second, …, and N-1 vacuum operations result in the air pressure drop amplitude in the reflow furnace being in the range of [1000Pa, 60000Pa].

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor chip welding, and in particular to a power semiconductor chip reflow soldering method and system. Background Art

[0002] The packaging structure of a power semiconductor module includes, from top to bottom, a power semiconductor chip, a chip solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, and a copper-nickel-plated substrate. The upper copper layer, ceramic layer, and lower copper layer constitute the power semiconductor module's ceramic copper-clad substrate (DBC substrate). During the packaging process of this packaging structure, the power semiconductor chip is soldered to the DBC substrate to form the power semiconductor module. The solder between the power semiconductor chip and the DBC substrate forms the chip solder layer.

[0003] The packaging process for power semiconductor devices requires vacuum reflow soldering. During this process, volatilization of some solder and flux inevitably generates gases. Unvented gases remain in the solder, forming solder voids within the chip's solder layer upon cooling. For high-demand applications, the void rate within the solder layer of power semiconductor chips must be less than 50%. The presence of voids in the chip's solder layer can significantly impact the thermal conductivity of power semiconductor modules, particularly in the longitudinal direction. Specifically, voids can alter the direction of heat flow within the module, increase the thermal resistance of the solder interface, exacerbate uneven chip temperature distribution, and even induce localized heat clustering. These phenomena not only degrade the thermal management performance of the power semiconductor chip but can also pose a serious threat to the module's long-term reliability. To minimize these adverse effects and extend the lifespan of power semiconductor chips, optimized process methods are needed to limit the void rate within the chip's solder layer to a minimum. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a power semiconductor chip reflow soldering method and system to address the problem that the chip solder layer formed during the existing power semiconductor chip soldering has a high void rate, which in turn affects the reliability of the power semiconductor module.

[0005] To solve the above technical problems, the present invention adopts a technical solution: a power semiconductor chip reflow method, comprising the following steps:

[0006] Step S1: placing the power semiconductor chip to be soldered in a reflow furnace, and allowing the power semiconductor chip to be soldered to adhere to the solder on the ceramic copper clad substrate;

[0007] Step S2: performing a heating operation to make the temperature in the reflow furnace reach the soldering temperature;

[0008] Step S3: performing an exhaust operation and maintaining the temperature in the reflow furnace at a soldering temperature, thereby soldering the power semiconductor chip to obtain a power semiconductor module;

[0009] Step S4: performing a cooling operation;

[0010] Step S5: Take out the power semiconductor module.

[0011] Wherein: the specific operation of performing the exhaust operation in step S3 is: perform N exhaust operations; after performing the i-th exhaust operation, the air pressure in the reflow furnace reaches the air pressure value P(i); and the interval time △T between the two exhaust operations is in the range of [3s, 10s]; 1≤i≤N; the value range of N is [2, 4]; P(1)>P(2)>……>P(N); the value range of P(1) is [40000Pa, 65000Pa]; the value range of P(N) is [50Pa, 45000Pa]; from performing the first exhaust operation to performing the N-1-th exhaust operation, the value range of the pressure drop amplitude in the reflow furnace caused by each exhaust operation is [1000Pa, 60000Pa].

[0012] According to the above technical solution of the present invention, the process of the exhaust operation after reaching the welding temperature is set, that is, the number of exhaust operations, the air pressure value reached after each exhaust operation, and the interval time between two adjacent exhaust operations are set, so that the gas generated by the volatilization of part of the solder and flux in the chip solder layer can be effectively discharged, thereby achieving the effect of a smaller void rate. By adjusting the reflow soldering process by the method proposed by the present invention, the numerical range of the void rate of the chip solder layer can be effectively reduced and limited, so that a power semiconductor chip with a lower actual void characteristic can be obtained. When the one-time air pressure extraction is too large (that is, the air pressure value drops too much), the chip solder layer will be explosively exhausted, resulting in the occurrence of undesirable problems such as solder bead splashing. By setting the value range of the difference in the air pressure value reached in the reflow furnace after two adjacent exhaust operations in step S3, the occurrence of this problem can be avoided.

[0013] In the above technical solution:

[0014] If P(N)≥10000Pa, then from the first pumping operation to the N-1th pumping operation, the pressure drop amplitude in the reflow furnace during each pumping operation is in the range of [20000Pa, 60000Pa];

[0015] If 1000Pa≤P(N)<10000Pa, then the value range of P(N-1)-P(N) is [10000Pa, 60000Pa]. From the first pumping operation to the N-1 pumping operation, the pressure drop amplitude in the reflow furnace caused by each pumping operation is in the range of [20000Pa, 60000Pa].

[0016] If 50Pa≤P(N)<1000Pa, then the value range of P(N-1)-P(N) is [1000Pa, 60000Pa];

[0017] If 50Pa≤P(N)<1000Pa, and 1000Pa≤P(N-1)<10000Pa, then the value range of P(N-2)-P(N-1) is [10000Pa, 60000Pa]. From the first vacuum operation to the N-2 vacuum operation, the value range of the pressure drop in the reflow furnace caused by each vacuum operation is [20000Pa, 60000Pa].

[0018] By setting the pressure difference range to [20,000Pa, 60,000Pa], explosive exhaust can be prevented. In this application, the difference range can be widened when the pressure is low. This is because when the pressure is low, the density and energy of the gas molecules decrease, resulting in a lower pumping speed compared to when the pressure is high, thus preventing explosive exhaust.

[0019] In the above technical solution, in step S3, the value of N, the pressure value reached in the reflow furnace after each vacuum operation, and the value of ΔT are determined based on the target void ratio of the chip solder layer; the chip solder layer is formed between the power semiconductor chip and the ceramic copper-clad substrate.

[0020] To study the impact of chip solder layer voiding on IGBT power modules, it is necessary to obtain power semiconductor modules with a set chip solder layer voiding rate range. However, existing reflow soldering methods cannot produce power semiconductor modules that meet the required chip solder layer voiding rate. According to the above technical solution of the present invention, based on the target chip solder layer voiding rate, the corresponding parameter values during the vacuum operation can be determined, thereby obtaining a power semiconductor module with the corresponding target voiding rate.

[0021] In the above technical solution:

[0022] When the target void ratio range is [20%, 25%], N=2, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, and △T=6s;

[0023] When the target void ratio range is [10%, 15%], N=3, the value range of P(1) is 60000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 20000Pa±500Pa, and △T=3s;

[0024] When the target void ratio range is [3%, 6%], N=3, the value range of P(1) is 40000Pa±500Pa, the value range of P(2) is 20000Pa±500Pa, the value range of P(3) is 6000Pa±500Pa, and △T=6s;

[0025] When the target void ratio range is [1.5%, 2.5%], N=4, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 15000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=4s;

[0026] When the target void ratio range is [0.5%, 1.5%], N=4, the value range of P(1) is 50000Pa±500Pa, the value range of P(2) is 25000Pa±500Pa, the value range of P(3) is 5000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=10s.

[0027] According to the above technical solution of the present invention, when the target void ratio requirement of the chip solder layer is within the corresponding numerical range, the power semiconductor chip solder layer with the corresponding void ratio numerical range can be obtained by adjusting the number of vacuum operations, the time interval between two adjacent vacuum operations, and the target air pressure value reached in the reflow furnace after each vacuum operation, thereby meeting actual research needs.

[0028] In the above technical solution, N=4, the value range of P(1) is 50000Pa±500Pa, the value range of P(2) is 25000Pa±500Pa, the value range of P(3) is 5000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=10s.

[0029] According to the setting of the above-mentioned optimal parameters of the present invention, the void rate of the chip solder layer can be reduced.

[0030] In the above technical solution, the following steps are further included between step S1 and step S2:

[0031] Step SA1: Perform at least one purge operation to create an oxygen-free environment in the reflow furnace.

[0032] In the above technical solution, the scrubbing operation specifically includes:

[0033] Perform vacuum operation to reduce the pressure in the reflow furnace to a value not greater than 50Pa;

[0034] Fill with nitrogen until the pressure in the reflow oven reaches atmospheric pressure.

[0035] In the above technical solution, step S2 specifically includes:

[0036] Step S21: After a first preset time T1, the temperature in the reflow furnace is heated to a first temperature TA1;

[0037] Step S22: After a second preset time T2, the temperature in the reflow furnace is heated from the first temperature TA1 to the second temperature TA2;

[0038] Step S23: After a third preset time T3, the temperature in the reflow furnace is heated from the second temperature TA2 to the soldering temperature.

[0039] Wherein, T1>T2>T3, the second temperature TA2 is greater than the first temperature TA1 and lower than the welding temperature.

[0040] According to the above technical solution of the present invention, in step S2, the temperature in the reflow furnace is heated from the first temperature and the second temperature to the welding temperature through the first, second and third preset times of different lengths, so that the heating effect is better.

[0041] In the above technical solution: T1=180s; T2=120s; T3=60s; TA1=150℃; TA2=180℃;

[0042] The welding temperature is 245°C.

[0043] In the above technical solution, in the cooling operation of step S4, the temperature in the reflow furnace is reduced to 50°C at a rate of 2°C / s.

[0044] According to the same inventive concept, the present invention further provides a power semiconductor chip reflow system, comprising a processor, wherein the processor is configured to execute the steps of any one of the above-mentioned power semiconductor chip reflow methods.

[0045] The advantages and positive effects of the present invention are as follows: the present invention reduces the void rate of the solder layer of the power semiconductor chip by setting the number of vacuuming times, the target air pressure value to be reached after each vacuuming period, and the interval time between two adjacent vacuuming operations. By adjusting the above three parameters, the generation of the void rate of the solder layer of the power semiconductor chip can be regulated. This method can be completed only by adjusting the reflow process, without adding additional manufacturing steps, is simple to operate, and does not conflict with subsequent bonding processes. It is fully compatible with existing semiconductor packaging processes and has good versatility. While the present invention can control the void rate, it effectively reduces and limits the generation range of the initial void rate of the chip solder layer through parameter optimization. It has good versatility and is conducive to the production and manufacturing of power semiconductor chips with high welding quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 This is a flow chart of a power semiconductor chip reflow method according to an embodiment of the present invention.

[0048] Figure 2 Schematic diagram of temperature and pressure changes in a reflow furnace during soldering of a power semiconductor chip according to an embodiment of the present invention; wherein the horizontal axis represents time, the vertical axis on the left represents temperature, and the vertical axis on the right represents pressure.

[0049] Figure 3 yes Figure 2 Schematic diagram of the changes in air pressure values in the second stage Z22 of the heating zone and the recirculation zone Z3.

[0050] Figure 4 This is a schematic diagram of the chip solder layer appearance and void situation obtained during the first test.

[0051] Figure 5 This is a schematic diagram of the chip solder layer appearance and void situation obtained during the second test.

[0052] Figure 6 This is a schematic diagram of the chip solder layer appearance and void situation obtained during the third test.

[0053] Figure 7 This is a schematic diagram of the chip solder layer appearance and void situation obtained during the fourth test.

[0054] Figure 8This is a schematic diagram of the chip solder layer appearance and void situation obtained during the fifth test. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] Example 1

[0057] This embodiment 1 provides a power semiconductor chip reflow method, comprising the following steps:

[0058] Step S1: placing the power semiconductor chip to be soldered in a reflow furnace, and allowing the power semiconductor chip to be soldered to adhere to the solder on the ceramic copper clad substrate;

[0059] Step S2: performing a heating operation to make the temperature in the reflow furnace reach the soldering temperature;

[0060] Step S3: performing N times of vacuuming operations to gradually reduce the pressure in the reflow furnace to a pressure value P(N), thereby soldering the power semiconductor chip to the ceramic copper-clad substrate through solder to obtain a power semiconductor module;

[0061] Step S4: performing a cooling operation;

[0062] Step S5: Take out the power semiconductor module.

[0063] in:

[0064] In step S3, heating is continued to keep the temperature in the reflow oven at the soldering temperature; that is, heating is continued during the vacuuming in step S3 and the time between two vacuuming operations to ensure that the temperature in the reflow oven is maintained at the soldering temperature.

[0065] In step S3, after the i-th vacuum operation is performed, the air pressure in the reflow furnace reaches the air pressure value P(i); and the interval time △T between the two vacuum operations is in the range of [3s, 10s]; 1≤i≤N; the value range of N is [2, 4]; P(1)>P(2)>……>P(N); the value range of P(1) is [40000Pa, 65000Pa]; the value range of P(N) is [50Pa, 45000Pa]; the first vacuum operation, the second vacuum operation, ..., the N-1th vacuum operation are performed so that the value range of the pressure drop amplitude in the reflow furnace is [1000Pa, 60000Pa].

[0066] In step S3, if P(N)≥10000Pa, the first pumping operation, the second pumping operation, ... the N-1th pumping operation are performed so that the pressure drop amplitude in the reflow furnace is in the range of [20000Pa, 60000Pa].

[0067] If 1000Pa≤P(N)<10000Pa, then the value range of P(N-1)-P(N) is [10000Pa, 60000Pa], and the first vacuum operation, the second operation, ..., the N-1 vacuum operation are performed so that the value range of the pressure drop in the reflow furnace is [20000Pa, 60000Pa].

[0068] If 50Pa≤P(N)<1000Pa, then the value range of P(N-1)-P(N) is [1000Pa, 60000pa].

[0069] If 50Pa≤P(N)<1000Pa, and 1000Pa≤P(N-1)<10000Pa, then the value range of P(N-2)-P(N-1) is [10000Pa, 60000Pa], and the first pumping operation, the second pumping operation, ..., the N-2 pumping operation are performed so that the value range of the pressure drop in the reflow furnace is [20000Pa, 60000Pa].

[0070] In this application, the air pressure value reached after the first pumping operation can be determined first, and then the air pressure values reached after the second, third, ..., and Nth pumping operations can be determined in sequence. Alternatively, the air pressure value reached after the Nth pumping operation can be determined first, and then the air pressure values reached after the N-1th, N-2th, ..., and 1st pumping operations can be determined in sequence. In this embodiment, the vacuum environment is considered to be achieved when the air pressure in the furnace reaches 50 Pa.

[0071] In step S3, the value of N, the pressure value reached in the reflow furnace after each vacuum operation, and the value range of ΔT are determined based on the target void ratio of the chip solder layer formed between the power semiconductor chip and the ceramic copper-clad substrate.

[0072] The steps between step S1 and step S2 also include:

[0073] Step SA1: Perform at least one purge operation to create an oxygen-free environment in the reflow furnace.

[0074] The scrubbing operation specifically includes:

[0075] Perform vacuum operation to reduce the pressure in the reflow furnace to a value not greater than 50Pa;

[0076] Fill with nitrogen until the pressure in the reflow oven reaches atmospheric pressure.

[0077] Step S2 specifically includes:

[0078] Step S21: After a first preset time T1, the temperature in the reflow furnace is heated to a first temperature TA1;

[0079] Step S22: After a second preset time T2, the temperature in the reflow furnace is heated from the first temperature TA1 to the second temperature TA2;

[0080] Step S23: After a third preset time T3, the temperature in the reflow furnace is heated from the second temperature TA2 to the soldering temperature.

[0081] T1>T2>T3, the second temperature TA2 is higher than the first temperature TA1 and lower than the welding temperature.

[0082] Preferably, T1=180s; T2=120s; T3=60s; TA1=150°C; TA2=180°C; and the welding temperature is 245°C.

[0083] In the cooling operation of step S4 , the temperature in the reflow furnace is lowered to 50° C. at a rate of 2° C. / s.

[0084] According to the same inventive concept, the present invention further provides a power semiconductor chip reflow system, comprising a processor, wherein the processor is configured to execute the steps of the power semiconductor chip reflow method described above.

[0085] The following is a further detailed description of the first embodiment of the present invention. In this embodiment, the power semiconductor chip is an IGBT chip.

[0086] like Figure 1 As shown, the present invention proposes a high-quality reflow soldering process method for power semiconductor chips, which has the following process steps:

[0087] S1: Place the power semiconductor chip to be soldered in a reflow oven and allow the power semiconductor chip to be soldered to adhere to the solder. Step S1 specifically includes:

[0088] S11: Design a suitable printing stencil, including the size of the welding surface and the thickness of the solder. After reasonably adjusting the parameters of the printer, the selected solder is attached to the DBC substrate through the printing process (i.e. Figure 1 The thickness of the printed stencil is the same as the thickness of the chip solder layer, which is 0.12 mm. The solder used is Sn-Ag-Cu solder, in which the contents of Sn, Cu, and Ag are 96.5%, 0.5%, and 3.0%, respectively.

[0089] S12: Reasonably adjust the parameters of the placement machine, accurately position the IGBT chip to the solder area according to the direction and position, and use the placement process to fit the IGBT chip and the solder well (i.e. Figure 1 In step S2, in order to keep the solder wettable, the bonding machine always keeps the backing plate preheated. After completing this step, the sample preparation is completed.

[0090] SA1: Perform two rounds of gas washing operations, reduce the pressure in the reflow furnace to below 50Pa through the vacuum exhaust valve, and then fill it with nitrogen to atmospheric pressure. Repeat this operation twice to create an oxygen-free environment in the furnace. Figure 2 The figure shows the changes in the gas pressure in the furnace during two rounds of scrubbing operations.

[0091] SA2: Perform an air purge to drain the coolant from the condenser tube below the reflow furnace, allowing subsequent heating operations to proceed normally. The condenser tube generates condensate, which circulates after soldering to cool the soldered material. Installing a condenser tube in a reflow furnace is conventional technology.

[0092] S2: Perform heating operation.

[0093] In the preheating zone Z1, the furnace is preheated to 150°C after 180s to make the temperature of each component uniform; in the first stage of the heating zone Z21, the furnace temperature is raised from 150°C to 180°C after 120s, and in the second stage of the heating zone Z22, it is heated to 245°C after 60s to reach the welding temperature. Figure 2 The figure shows the temperature changes in the preheating zone and the heating zone of the furnace.

[0094] S3: In the reflow zone Z3 (i.e., the time range during which heating is performed to maintain the soldering temperature), heating is continued to maintain the soldering temperature constant throughout the entire exhaust process.

[0095] The pumping gradient (i.e. the number of pumping operations), the holding time between two pumping operations, and the air pressure value reached after each pumping operation can be set.

[0096] like Figure 3 The following is an example of setting the maximum air pressure when N=4. Figure 3As shown, the time from T_0 to T_1 corresponds to the second stage Z22 of the heating zone, and the reflow zone Z3 is entered from time T_1. At time T_1, the reflow furnace reaches the soldering temperature, and the first exhaust operation is performed, so that the pressure in the reflow furnace drops from the atmospheric pressure value P(0) to the pressure value P(1); at time T_2, the second exhaust operation is performed, so that the pressure in the reflow furnace drops from the pressure value P(1) to the pressure value P(2); at time T_3, the third exhaust operation is performed, so that the pressure in the reflow furnace drops from the pressure value P(2) to the pressure value P(3), and the fourth exhaust operation is performed, so that the pressure in the reflow furnace drops from the pressure value P(3) to the pressure value P(4). The interval between the first and second pumping operations is T_2-T_1, the interval between the second and third pumping operations is T_3-T_2, and the interval between the third and fourth pumping operations is T_4-T_3. Figure 2 The change of the gas pressure in the furnace during the scrubbing operation in step SA1 before step S3 is not shown in FIG. The change of the gas pressure in the furnace during the scrubbing operation can be referred to Figure 2 Among them, between time T_1 and time T_2, between time T_2 and time T_3, and between time T_3 and time T_4, a heating operation is performed so that the temperature in the reflow furnace is maintained at the soldering temperature.

[0097] When the target void ratio range is [20%, 25%], N=2, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, and △T=6s;

[0098] Alternatively, when the target void ratio range is [10%, 15%], N = 3, the value range of P(1) is 60000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 20000Pa±500Pa, and △T = 3s;

[0099] Alternatively, when the target void ratio range is [3%, 6%], N = 3, the range of P(1) is 40000Pa±500Pa, the range of P(2) is 20000Pa±500Pa, the range of P(3) is 6000Pa±500Pa, and △T = 6s;

[0100] Alternatively, when the target void ratio range is [1.5%, 2.5%], N = 4, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 15000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T = 4s;

[0101] When the target void ratio range is [0.5%, 1.5%], N=4, the value range of P(1) is 50000Pa±500Pa, the value range of P(2) is 25000Pa±500Pa, the value range of P(3) is 5000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=10s. Figure 2 The air pressure values after each pumping operation are displayed when the target void ratio range is [0.5%, 1.5%]. Figure 2 In the figure, the left side is the vertical axis showing the temperature, the right side is the vertical axis showing the air pressure value, and the two vertical axes share the horizontal axis showing the time below.

[0102] In this embodiment, at the moment of starting the first exhaust operation, the atmospheric pressure in the reflow furnace is .

[0103] S4: Fill the reflow oven with nitrogen to atmospheric pressure to start the circulation of the condensate and perform liquid cooling to dissipate heat. Cool the reflow oven to 50°C at a rate of 2°C / s. Figure 2 The cooling zone shown is Z4.

[0104] S5: After the reflow oven cools down and the soldering process is completed, the sample (i.e., the power semiconductor module obtained after the power semiconductor chip is soldered to the DBC substrate) is taken out and the sample is further cooled to room temperature;

[0105] S6: Scan the sample using a scanning ultrasonic microscope (SAM) to obtain an image of the solder layer of the power semiconductor module chip, calculate the void rate, and verify the process results. Step S6 is not shown in the figure.

[0106] Figure 4-Figure 8 This is a schematic diagram of the solder layer image obtained when scanning the sample obtained according to the embodiment of the present invention. Figure 4-Figure 8 The shaded area except for the chip solder is caused by the total reflection of the sound wave on the voids in the substrate solder layer during the SAM scanning process, as well as the insulating trench on the DBC substrate.

[0107] In the first test, N=2, P(1) value is 65000Pa, P(2) value is 40000Pa, △T=6s, and the image of the solder layer of the sample chip is obtained as follows: Figure 4 As shown. Figure 4 The void rate statistics of the chip solder layer show that the void rate of the chip solder layer is 22.53%, which meets the target void rate requirement of the chip solder layer at [20%, 25%].

[0108] In the second test, N=3, P(1) value is 60000Pa, P(2) value is 40000Pa, P(3) value is 20000Pa, △T=3s, and the image of the solder layer of the sample chip is obtained as follows Figure 5 As shown. Figure 5 The void rate statistics of the chip solder layer show that the void rate of the chip solder layer is 11.61%, which meets the target void rate requirement of the chip solder layer at [10%, 15%].

[0109] In the third test, N=3 was set, the value of P(1) was 40000Pa, the value of P(2) was 20000Pa, the value of P(3) was 6000Pa, △T=6s, and the image of the solder layer of the sample chip was obtained as follows: Figure 6 As shown. Figure 6 The void rate statistics of the chip solder layer show that the void rate of the chip solder layer is 3.91%, which meets the target void rate requirement of the chip solder layer at [3%, 6%].

[0110] In the fourth and fifth tests, N=4, P(1) is set to 50000Pa, P(2) is set to 25000Pa, P(3) is set to 5000Pa, P(4) is set to 50Pa, and △T=10s:

[0111] (1) During the fourth test, the image of the solder layer of the sample chip was obtained as follows Figure 7 As shown. Figure 7 The void rate statistics of the chip solder layer show that the void rate of the chip solder layer is 0.62%, which meets the target void rate requirement of the chip solder layer between [0.5%, 1.5%];

[0112] (2) During the fifth test, the image of the solder layer of the sample chip was obtained as follows Figure 8 As shown. Figure 8 The void rate statistics of the chip solder layer show that the void rate of the chip solder layer is 0.77%, which meets the target void rate requirement of the chip solder layer between [0.5%, 1.5%].

[0113] Preferably, before the printing process begins, the DBC substrate and the chip surface can be wiped with anhydrous ethanol to remove dust, sweat stains, oil stains, etc. that may exist on the welding surface.

[0114] In the present invention, the vacuum reflow soldering equipment used can be an existing reflow oven equipment.

[0115] The present invention primarily reduces the void rate in the solder layer of power semiconductor chips by adjusting the number of vacuum gradients in the reflow zone, the target pressure required for each vacuum stage, and the temperature hold time after each vacuum stage. According to the present invention's stepped vacuuming method, by adjusting these parameters, the range of void rate generation in the solder layer of power semiconductor module chips can be controlled. This method can be implemented simply by adjusting the reflow process, without adding additional manufacturing steps. It is simple to operate and does not conflict with subsequent processes such as bonding. It is fully compatible with existing semiconductor packaging processes, has excellent versatility, and is conducive to the production of high-quality power semiconductor chips. Under optimal process parameters, the void rate in the solder layer of the produced module chip is within the range of 0.5%-1.5%, and the module yield reaches 99.9%, achieving high solder quality. This solution suppresses solder and flux splashing and prevents chip flipping while limiting the void rate to a small range. Compared to the requirement of 50% void rate in the solder layer of power semiconductor chips in high-demand applications, the 1.5% void rate achieved by this application solution is at least a 97% reduction.

[0116] Example 2

[0117] The difference between this embodiment 2 and embodiment 1 is that when a power semiconductor module with a better target void ratio is required, the following settings can be performed:

[0118] Set the following parameter ranges: N = 4, P(1) range: 65000Pa ± 500Pa, P(2) range: 40000Pa ± 500Pa, P(3) range: 15000Pa ± 500Pa, P(4) range: 50Pa ± 10Pa, and ΔT = 4s. This setting yields a power semiconductor module with a void ratio within the range [1.5%, 2.5%].

[0119] Alternatively, set the following parameter ranges: N = 4, P(1) range: 50,000 Pa ± 500 Pa, P(2) range: 25,000 Pa ± 500 Pa, P(3) range: 5,000 Pa ± 500 Pa, P(4) range: 50 Pa ± 10 Pa, and ΔT = 10 s. This setting yields a power semiconductor module with a void ratio within the range [0.5%, 1.5%].

[0120] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0121] The embodiments of the present invention have been described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the present invention. After reading the present invention, modifications of various equivalent forms of the present invention by those skilled in the art all fall within the scope defined by the claims appended to this application. In the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

Claims

1. A power semiconductor chip reflow method comprising the following steps: Step S1: placing the power semiconductor chip to be soldered in a reflow furnace, and allowing the power semiconductor chip to be soldered to adhere to the solder on the ceramic copper clad substrate; Step S2: performing a heating operation to make the temperature in the reflow furnace reach the soldering temperature; Step S3: performing an exhaust operation and maintaining the temperature in the reflow furnace at a soldering temperature, thereby soldering the power semiconductor chip to obtain a power semiconductor module; Step S4: performing a cooling operation; Step S5: taking out the power semiconductor module; It is characterized in that: the specific operation of performing the air extraction operation in step S3 is: Perform N pumping operations; after the i-th pumping operation, the pressure in the reflow furnace reaches the pressure value P(i); and the interval time △T between two pumping operations is in the range of [3s, 10s]; 1≤i≤N; the value range of N is [2, 4]; P(1)>P(2)>……>P(N); the value range of P(1) is [40000Pa, 65000Pa]; the value range of P(N) is [50Pa, 45000Pa]; from the execution of the first pumping operation to the execution of the N-1th pumping operation, the value range of the pressure drop amplitude in the reflow furnace caused by each pumping operation is [1000Pa, 60000Pa]; In step S3, the value of N, the pressure value reached in the reflow furnace after each vacuum operation, and the value of ΔT are determined based on the target void ratio of the chip solder layer formed between the power semiconductor chip and the ceramic copper-clad substrate.

2. The power semiconductor chip reflow method according to claim 1, wherein: If P(N)≥10000Pa, then from the first pumping operation to the N-1th pumping operation, the pressure drop amplitude in the reflow furnace during each pumping operation is in the range of [20000Pa, 60000Pa]; If 1000Pa≤P(N)<10000Pa, then the value range of P(N-1)-P(N) is [10000Pa, 60000Pa]. From the first pumping operation to the N-1 pumping operation, the pressure drop amplitude in the reflow furnace caused by each pumping operation is in the range of [20000Pa, 60000Pa]. If 50Pa≤P(N)<1000Pa, then the value range of P(N-1)-P(N) is [1000Pa, 60000Pa]; If 50Pa≤P(N)<1000Pa, and 1000Pa≤P(N-1)<10000Pa, then the value range of P(N-2)-P(N-1) is [10000Pa, 60000Pa]. From the first vacuum operation to the N-2 vacuum operation, the value range of the pressure drop in the reflow furnace caused by each vacuum operation is [20000Pa, 60000Pa].

3. The power semiconductor chip reflow method according to claim 1, wherein: When the target void ratio range is [20%, 25%], N=2, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, and △T=6s; or When the target void ratio range is [10%, 15%], N=3, the value range of P(1) is 60000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 20000Pa±500Pa, and △T=3s; or When the target void ratio range is [3%, 6%], N=3, the value range of P(1) is 40000Pa±500Pa, the value range of P(2) is 20000Pa±500Pa, the value range of P(3) is 6000Pa±500Pa, and △T=6s; or When the target void ratio range is [1.5%, 2.5%], N=4, the value range of P(1) is 65000Pa±500Pa, the value range of P(2) is 40000Pa±500Pa, the value range of P(3) is 15000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=4s; or When the target void ratio range is [0.5%, 1.5%], N=4, the value range of P(1) is 50000Pa±500Pa, the value range of P(2) is 25000Pa±500Pa, the value range of P(3) is 5000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, and △T=10s.

4. The power semiconductor chip reflow method according to claim 1, wherein: N=4, the value range of P(1) is 50000Pa±500Pa, the value range of P(2) is 25000Pa±500Pa, the value range of P(3) is 5000Pa±500Pa, the value range of P(4) is 50Pa±10Pa, △T=10s.

5. The power semiconductor chip reflow method according to any one of claims 1 to 4, characterized in that: The steps between step S1 and step S2 also include: Step SA1: Perform at least one purge operation to create an oxygen-free environment in the reflow furnace.

6. The power semiconductor chip reflow method according to claim 5, wherein: The scrubbing operation specifically includes: Perform vacuum operation to reduce the pressure in the reflow furnace to a value not greater than 50Pa; Fill with nitrogen until the pressure in the reflow oven reaches atmospheric pressure.

7. The power semiconductor chip reflow method according to any one of claims 1 to 4, characterized in that: Step S2 specifically includes: Step S21: After a first preset time T1, the temperature in the reflow furnace is heated to a first temperature TA1; Step S22: After a second preset time T2, the temperature in the reflow furnace is heated from the first temperature TA1 to the second temperature TA2; Step S23: After a third preset time T3, the temperature in the reflow furnace is heated from the second temperature TA2 to the soldering temperature; Wherein, T1>T2>T3, the second temperature TA2 is greater than the first temperature TA1 and lower than the welding temperature.

8. The power semiconductor chip reflow method according to claim 7, wherein: T1=180s; T2=120s; T3=60s; TA1=150°C; TA2=180°C; the welding temperature is 245°C.

9. A power semiconductor chip reflow system, characterized in that: The method comprises a processor configured to execute the steps of the power semiconductor chip reflow method according to any one of claims 1 to 8.

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