Method for simplifying PCB (Printed Circuit Board) mixed-pressing stack-up design

Abstract

The invention relates to the technical field of PCB (Printed Circuit Board) mixed-pressing stack-up structure, in particular to a method for simplifying PCB mixed-pressing stack-up structure design, which comprises the following steps of: accurately positioning and cutting a CCL supplied material, positioning and cutting the CCL to a uniform size, cleaning a board surface, covering photosensitive ink, curing, exposing, developing, etching to form a required pattern, manufacturing an inner-layer circuit pattern, browning an inner-layer board, fusing and riveting, and then, manufacturing a printed circuit board. And pressing according to parameters. According to the method, the exposure energy parameters are optimized, so that the precision of the PCB circuit pattern is accurately controlled, the definition and the accuracy of the circuit pattern are ensured, the qualified rate of a conduction test, an insulation test and AVI scanning of a PCB product is remarkably improved by the optimal exposure energy value determined by an experiment, the reliability and the stability of the product are improved, and the product quality is improved. 6 lattices and 7 lattices are used as optimal exposure energy values, so that the product quality is ensured, the stability and the cost effectiveness in the production process are also considered, and the production cost is reduced and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB hybrid pressing stack structures, and specifically provides a method for simplifying the design of PCB hybrid pressing stack structures. Background Technique

[0002] In modern electronic devices, as the support for electronic components and the provider of electrical connections, the rationality and efficiency of PCB design have a crucial impact on the performance, cost, and size of electronic devices. With the rapid development of electronic technology, the requirements for PCB by electronic devices are getting higher and higher. It not only needs to have higher signal transmission speed, better electromagnetic compatibility, but also needs to integrate more functions in a limited space.

[0003] However, generally, the traditional method for designing the PCB stack structure of the hybrid pressing structure is often relatively complex and requires considering various factors, such as signal integrity, power integrity, electromagnetic interference (EMI), etc. While the cost is high, the stability of the product is difficult to guarantee.

[0004] Based on this, the present invention provides a method for simplifying the design of PCB hybrid pressing stack structures to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for simplifying the design of PCB hybrid pressing stack structures to solve the problems raised in the above background technique.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A method for simplifying the design of PCB hybrid pressing stack structures includes the following steps:

[0008] S1. Precise positioning and cutting of the incoming CCL, and positioning and cutting the CCL to a unified size;

[0009] S2. Cleaning the board surface, covering with photosensitive ink and curing, exposing, developing, and etching to form the required pattern to produce the inner layer circuit pattern;

[0010] S3. After browning, fusing, and riveting the inner layer boards, pressing according to parameters;

[0011] S4. Drilling according to requirements with different parameters;

[0012] S5. Depositing copper on the whole board and in the holes, and then electroplating to increase the copper thickness;

[0013] S6. Repeating steps S1 to S5 to produce the sub-outer layer circuit;

[0014] S7. Browning, fusing, and riveting the inner layer board and the sub-outer layer board, and then pressing again;

[0015] S8. Manufacture the outer layer circuit, and perform solder mask treatment, text printing, surface treatment, shaping, testing and inspection.

[0016] Preferably, the implementation process of step S1 is as follows:

[0017] S1.1. Conduct strict quality inspection on the incoming copper clad laminate (CCL) to ensure that the material is defect-free.

[0018] S1.2. Use high-precision cutting equipment to position and cut the CCL into production sizes with consistent dimensions. The cutting accuracy is ±0.1 mm to ensure precise docking of subsequent processes.

[0019] S1.3. Conduct edge treatment on the cut copper clad laminate to remove burrs and impurities and ensure a flat board surface.

[0020] Preferably, the implementation process of step S2 is as follows:

[0021] S2.1. Use a micro-etching solution of the H2SO4 and H2O2 system to thoroughly clean the board surface and remove oil stains and oxides.

[0022] S2.2. Cover with photosensitive ink and dry and cure it to ensure that the ink adheres evenly to the board surface.

[0023] S2.3. Use a high-precision exposure machine for ultraviolet irradiation to cause a polymerization reaction. The exposure energy is selected as 5 - 7 grids to ensure uniform exposure.

[0024] S2.4. Perform shrinkage and expansion compensation according to different board thicknesses and copper thicknesses. The X compensation is 4 / 10000, and the Y compensation is 5 / 10000 to ensure graphic accuracy.

[0025] S2.5. After exposure, use the DES line for development, etching, and film removal operations to precisely present the required graphics and the routing slot positioning hole rings required for the next process.

[0026] Preferably, the implementation process of step S3 is as follows:

[0027] S3.1. Brown the inner layer boards of all layers to enhance the board surface adhesion.

[0028] S3.2. Perform fusion and riveting operations to ensure tight bonding between layers.

[0029] S3.3. Press and drill according to normal pressing parameters. The pressing temperature is 150 - 180 °C, the pressure is 5 - 10 MPa, and the time is 60 - 90 min to ensure pressing quality.

[0030] S3.4. Conduct quality inspection on the pressed board, including inspection of board warpage and interlayer bonding strength indicators.

[0031] Preferably, the implementation process of step S4 is as follows:

[0032] S4.1. According to the drilling requirements, select different drilling parameters for different types of product materials and copper thicknesses;

[0033] S4.2. Use a high-precision drilling machine for drilling operations. The drilling diameter is in the range of 0.2 - 3.0 mm, the depth is determined according to the board thickness, and the rotational speed is 10,000 - 30,000 rpm;

[0034] S4.3. Inspect the hole wall quality of the drilled board, including hole wall roughness and hole position accuracy indicators.

[0035] Preferably, the implementation process of step S5 is as follows:

[0036] S5.1. Use chemical CuCL2 solution to deposit copper on the entire board and inside the holes. The deposition thickness is in the range of 1 - 3 um, and the solution concentration is within a certain range to ensure the deposition quality;

[0037] S5.2. Pretreat the board surface before electroplating to remove oil and oxides;

[0038] S5.3. Convert copper - phosphorus balls into copper ions and transfer them from the anode to the cathode surface of the board. The electroplating current density is within a certain range, and the time is 30 - 60 min to increase the copper plating thickness to meet the requirements;

[0039] S5.4. Inspect the quality of the electroplated board, including the detection of coating thickness and uniformity indicators.

[0040] Preferably, the implementation process of step S6 is as follows:

[0041] S6.1. Repeat the cleaning, exposure, development, and etching operations in steps S1 to S5. In this step, the exposure energy is selected as 6 - 8 grids, and the shrinkage compensation is finely adjusted according to the physical board;

[0042] S6.2. Through the operations of development, etching, and film removal, accurately present the required sub - outer layer circuit pattern on the copper - clad laminate;

[0043] S6.3. Inspect the quality of the sub - outer layer circuit to ensure the circuit accuracy and integrity.

[0044] Preferably, the implementation process of step S7 is as follows:

[0045] S7.1. Brownify all layers of inner layer boards and sub - outer layer boards;

[0046] S7.2. Perform fusion and riveting operations to ensure tight bonding and no gaps between layers;

[0047] S7.3. Perform secondary lamination and drilling according to normal lamination parameters. Keep the lamination parameters consistent with the first lamination to ensure the quality of the overall stack structure. During the lamination process, strictly control the temperature, pressure, and time parameters;

[0048] S7.4. Conduct quality inspections on the overall stack structure after lamination, including inspections of the interlayer bonding force and board warpage index.

[0049] Preferably, the implementation process of step S8 is as follows:

[0050] S8.1. Clean the board surface with micro-etching solution, then laminate a photosensitive dry film and perform exposure, development, and etching operations to accurately present the required outer layer circuit pattern;

[0051] S8.2. Clean the board surface again using the volcanic ash and brush process, then print photosensitive ink and perform exposure and development operations to form a solder mask to protect the circuit from damage;

[0052] S8.3. Use a character printer to print characters to meet requirements, including product identification and production date information;

[0053] S8.4. Perform surface treatment operations such as immersion gold, immersion tin, OSP, or spray tin according to requirements to enhance the corrosion resistance and solderability of the board surface;

[0054] S8.5. Perform precise shaping operations on the product with a shaping accuracy of ±0.1 mm and a special control accuracy of ±0.05 mm to meet the requirements for dimensional accuracy;

[0055] S8.6. Conduct conduction and insulation tests on the product to ensure correct circuit connections. At the same time, use 100% AVI scanning to compare with the required standards for appearance inspection, and select products that do not meet the requirements for repair or scrapping.

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] By optimizing the exposure energy parameters, the present invention realizes precise control of the accuracy of PCB circuit patterns, ensures the clarity and accuracy of the circuit patterns. The optimal exposure energy value determined by experiments significantly improves the passing rates of the conduction test, insulation test, and AVI scanning of PCB products, enhances the reliability and stability of the products. Using 6 grids and 7 grids as the optimal exposure energy values not only guarantees product quality but also considers the stability and cost-effectiveness during the production process, helps reduce production costs and improve production efficiency. Specific Embodiments

[0058] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0059] Embodiment 1

[0060] The present invention provides a method for simplifying the design of PCB hybrid lamination structure, including the following steps:

[0061] S1. Precise positioning and cutting of the incoming CCL materials, and positioning and cutting the CCL to a unified size;

[0062] S2. Clean the board surface, cover with photosensitive ink and cure it, expose, develop, and etch to form the required pattern, and make the inner layer circuit pattern;

[0063] S3. After browning, fusing, and riveting the inner layer boards, press them according to the parameters;

[0064] S4. Drill holes according to different requirements using different parameters;

[0065] S5. Deposit copper on the whole board and in the holes, and then electroplate to increase the copper thickness;

[0066] S6. Repeat steps S1 to S5 to make the sub-outer layer circuit;

[0067] S7. After browning, fusing, and riveting the inner layer board and the sub-outer layer board, press them again;

[0068] S8. Make the outer layer circuit, and perform solder mask treatment, text printing, surface treatment, shaping, testing and inspection.

[0069] In this embodiment, it should also be noted that the implementation process of step S1 is as follows:

[0070] S1.1. Conduct strict quality inspection on the incoming copper clad laminate (CCL) materials to ensure that the materials are defect-free;

[0071] S1.2. Use high-precision cutting equipment to perform positioning cutting on the CCL, cut it into production sizes with the same size, and the cutting accuracy is ±0.1 mm to ensure the precise docking of subsequent processes;

[0072] S1.3. Perform edge treatment on the cut copper clad laminate to remove burrs and impurities and ensure the flatness of the board surface.

[0073] In this embodiment, it should also be noted that the implementation process of step S2 is as follows:

[0074] S2.1. Thoroughly clean the board surface using the micro-etching solution of the H2SO4 and H2O2 system to remove oil stains and oxides;

[0075] S2.2. Cover with photosensitive ink and dry and cure it to ensure that the ink adheres evenly to the board surface;

[0076] S2.3. Use a high-precision exposure machine for ultraviolet irradiation to cause a polymerization reaction. Select an exposure energy of 5 - 7 grids to ensure uniform exposure;

[0077] S2.4. Perform scaling compensation according to different board thicknesses and copper thicknesses. The X compensation is 4 / 10000, and the Y compensation is 5 / 10000 to ensure graphic accuracy;

[0078] S2.5. After exposure, perform development, etching, and film removal operations using the DES line to accurately present the required graphics and the routing slot positioning hole rings required for the next process.

[0079] In this embodiment, it should also be noted that the implementation process of step S3 is as follows:

[0080] S3.1. Brown the inner layer boards of all layers to enhance the adhesion of the board surface;

[0081] S3.2. Perform fusion and riveting operations to ensure tight bonding between layers;

[0082] S3.3. Perform press-fit and target punching according to normal press-fit parameters. The press-fit temperature is 150 - 180 °C, the pressure is 5 - 10 MPa, and the time is 60 - 90 min to ensure the press-fit quality;

[0083] S3.4. Inspect the quality of the press-fit board, including the inspection of board warp and interlayer bonding strength indicators.

[0084] In this embodiment, it should also be noted that the implementation process of step S4 is as follows:

[0085] S4.1. According to the drilling requirements, select different drilling parameters for different types of product materials and copper thicknesses;

[0086] S4.2. Use a high-precision drilling machine for drilling operations. The drilling diameter is in the range of 0.2 - 3.0 mm, the depth is determined according to the board thickness, and the rotational speed is 10000 - 30000 rpm;

[0087] S4.3. Inspect the quality of the hole wall of the drilled board, including hole wall roughness and hole position accuracy indicators.

[0088] In this embodiment, it should also be noted that the implementation process of step S5 is as follows:

[0089] S5.1. Perform copper deposition on the entire board and in the holes using chemical CuCl2 solution. The deposition thickness is in the range of 1 - 3 μm, and the solution concentration is within a certain range to ensure deposition quality;

[0090] S5.2. Pretreat the board surface before electroplating to remove oil and oxides;

[0091] S5.3. Convert copper - phosphorus balls into copper ions and transfer them from the anode to the cathode on the board surface. The electroplating current density is within a certain range, and the time is 30 - 60 min to increase the copper plating thickness to meet the requirements;

[0092] S5.4. Conduct quality inspection on the electroplated board, including inspection of coating thickness and uniformity indicators.

[0093] In this embodiment, it should also be noted that the implementation process of step S6 is as follows:

[0094] S6.1. Repeat the cleaning, exposure, development, and etching operations in steps S1 to S5. In this step, the exposure energy is selected as 6 - 8 grids, and the scaling compensation is finely adjusted according to the physical board;

[0095] S6.2. Through the operations of development, etching, and film removal, accurately present the required sub - outer layer circuit pattern on the copper - clad laminate;

[0096] S6.3. Conduct quality inspection on the sub - outer layer circuit to ensure circuit accuracy and integrity.

[0097] In this embodiment, it should also be noted that the implementation process of step S7 is as follows:

[0098] S7.1. Conduct browning treatment on the inner layer boards and sub - outer layer boards of all layers;

[0099] S7.2. Perform fusion and riveting operations to ensure tight bonding without gaps between layers;

[0100] S7.3. Conduct secondary press - fit targeting according to normal press - fit parameters. The press - fit parameters are the same as those of the first press - fit to ensure the overall stack - up quality. During the press - fit process, temperature, pressure, and time parameters need to be strictly controlled;

[0101] S7.4. Conduct quality inspection on the overall stack - up after press - fit, including inspection of inter - layer bonding strength and board warpage indicators.

[0102] In this embodiment, it should also be noted that the implementation process of step S8 is as follows:

[0103] S8.1. Clean the board surface using micro - etching solution, then press and laminate photosensitive dry film and perform exposure, development, and etching operations to accurately present the required outer layer circuit pattern;

[0104] S8.2. After using volcanic ash and abrasive brush process to clean the board surface again, print photosensitive ink and perform exposure and development operations to form a solder mask to protect the circuit from damage;

[0105] S8.3. Use a character printer to print characters to meet requirements, including product identification and production date information;

[0106] S8.4. Perform surface treatment operations such as immersion gold, immersion tin, OSP or spray tin according to requirements to enhance the corrosion resistance and solderability of the board surface;

[0107] S8.5. Perform precise forming operations on the product with a forming accuracy of ±0.1 mm and a special control accuracy of ±0.05 mm to meet the requirements for dimensional accuracy;

[0108] S8.6. Conduct conduction and insulation tests on the product to ensure correct circuit connection. At the same time, use 100% AVI scanning to compare with the required standard for appearance inspection, and select products that do not meet the requirements for repair or scrapping.

[0109] Example 2

[0110] Prepare a PCB according to the method steps of the simplified PCB hybrid stacking structure design in Example 1. By changing the exposure energy parameters in steps S2.3 and S6.1, explore the impact on the PCB, and conduct conduction and insulation tests on the PCB product. At the same time, use 100% AVI scanning to compare with the required standard. The experimental process is as follows:

[0111] a. Prepare the required materials and equipment for the PCB hybrid stacking structure design according to the method steps in Example 1, and ensure that all steps (except for the exposure energy) are carried out according to the parameters in Example 1;

[0112] b. Set the exposure energy in steps S2.3 and S6.1 as variables, and respectively select 4 grids, 5 grids, 6 grids, 7 grids, and 8 grids as experimental values. For each exposure energy value, prepare a batch of PCB samples;

[0113] c. Prepare PCB samples under different exposure energies according to steps S1 to S8 in Example 1, and ensure that all other parameters remain the same except for the exposure energy;

[0114] d. Testing and inspection

[0115] Conduct conduction and insulation tests on the prepared PCB samples to ensure correct circuit connection. Use 100% AVI scanning to compare with the required standard and inspect the appearance of the PCB samples;

[0116] e. Record the test and inspection results of the PCB samples at each exposure energy value, analyze the influence of the exposure energy on the quality of the PCB products, and determine the optimal exposure energy value, as shown in Table 1;

[0117] Table 1 Data Sheet of PCB Samples with Different Exposure Energy Parameters

[0118]

[0119] Conclusion:

[0120] a). Conduction test: As the exposure energy increases, the pass rate of the conduction test first increases and then slightly decreases, reaching the highest value of 95% at 6 grids and 7 grids;

[0121] b). Insulation test: The change trend of the pass rate of the insulation test with the exposure energy is similar to that of the conduction test, and also reaches relatively high values at 6 grids and 7 grids;

[0122] c). AVI scan: The pass rate of the AVI scan increases with the increase of the exposure energy, reaching the highest value of 92% at 7 grids, and then slightly decreasing;

[0123] In summary, considering the pass rates of the conduction test, insulation test and AVI scan comprehensively, 6 grids and 7 grids are determined as the optimal exposure energy values. Among them, 7 grids are superior in the pass rate of the AVI scan, and 6 grids are superior in terms of stability and cost in actual production, and it is also a very excellent choice.

[0124] Therefore, through the above steps, the present invention realizes precise control of the precision of the PCB circuit pattern by optimizing the exposure energy parameters, ensures the clarity and accuracy of the circuit pattern. The optimal exposure energy value determined by the experiment significantly improves the pass rates of the conduction test, insulation test and AVI scan of the PCB products, enhances the reliability and stability of the products. As the optimal exposure energy values, 6 grids and 7 grids not only ensure the product quality, but also consider the stability and cost - effectiveness in the production process, which helps to reduce the production cost and improve the production efficiency.

[0125] In the description of this specification, the descriptions referring to terms such as "one embodiment", "example", "specific example", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above - mentioned terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0126] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for simplifying PCB mixed pressure stacking design, characterized in that: The following steps are involved: S1. Precisely position and cut CCL materials to uniform size; S2. Clean the board surface, cover it with photosensitive ink and solidify it, expose, develop and etch it to form the required pattern, and make the inner layer circuit pattern; S3. After the inner layer is browned, fused and riveted, it is pressed according to the parameters; S4. Choose different drilling parameters according to the needs; S5. Copper is deposited on the entire board and in the holes, and then electroplated to increase the copper thickness; S6. Repeat steps S1 to S5 to make the secondary outer layer circuit; S7. After browning, fusing and riveting the inner plate and the second outer plate, they are pressed together again; S8. Make the outer layer circuit, perform solder mask treatment, text printing, surface treatment, molding, testing and inspection.

2. The method for simplifying PCB mixed pressure stacking design according to claim 1, characterized in that: The implementation process of step S1 is as follows: S1.

1. Carry out strict quality inspection on incoming copper clad laminate (CCL) materials to ensure that the materials are free of defects; S1.

2. Use high-precision cutting equipment to position and cut CCL into production sizes with consistent sizes. The cutting accuracy is ±0.1mm to ensure accurate docking of subsequent processes; S1.

3. Process the edges of the cut copper clad laminate to remove burrs and impurities and ensure a smooth surface.

3. The method for simplifying PCB mixed pressure stacking design according to claim 2, characterized in that: The implementation process of step S2 is as follows: S2.

1. Use H2SO4 and H2O2 system micro-etching solution to thoroughly clean the board surface to remove oil stains and oxides; S2.

2. Cover with photosensitive ink and dry and solidify to ensure that the ink is evenly attached to the board surface; S2.

3. Use a high-precision exposure machine to irradiate with ultraviolet light to make it polymerize. The exposure energy is 5-7 grids to ensure uniform exposure. S2.4 compensates for expansion and contraction according to different plate thickness and copper thickness, with X compensation of 4 / 10000 and Y compensation of 5 / 10000 to ensure graphic accuracy; After S2.5 exposure, the DES line is used for development, etching, and film stripping operations to accurately present the required graphics and the gong groove positioning hole rings required for the next process.

4. The method for simplifying PCB mixed pressure stacking design according to claim 3, characterized in that: The implementation process of step S3 is as follows: S3.

1. Brown all the inner layers to enhance the adhesion of the board surface; S3.

2. Perform fusing and riveting operations to ensure that each layer is tightly bonded; S3.

3. Perform pressing and targeting according to normal pressing parameters, with pressing temperature of 150-180°C, pressure of 5-10MPa, and time of 60-90min to ensure pressing quality; S3.4 Perform quality inspection on the laminated boards, including inspection of board warpage and interlayer bonding strength.

5. The method for simplifying PCB mixed pressure stacking design according to claim 4, characterized in that: The implementation process of step S4 is as follows: S4.

1. According to the drilling requirements, different drilling parameters are selected for different types of product materials and copper thickness; S4.

2. Use a high-precision drilling machine to perform drilling operations, with a drilling diameter in the range of 0.2-3.0 mm, a depth determined according to the plate thickness, and a rotation speed of 10000-30000 rpm; S4.

3. Check the hole wall quality of the plate after drilling, including the hole wall roughness and hole position accuracy indicators.

6. The method for simplifying PCB mixed pressure stacking design according to claim 5, characterized in that: The implementation process of step S5 is as follows: S5.

1. Use chemical CuCL2 solution to deposit copper on the whole board and in the hole. The deposition thickness is in the range of 1-3um. The concentration of the solution is within a certain range to ensure the deposition quality. S5.

2. Pre-treat the board surface before electroplating to remove oil and oxides; S5.

3. The copper phosphorus balls are converted into copper ions from the anode to the cathode on the plate surface, the electroplating current density is within a certain range, and the time is 30-60min to increase the copper plating thickness to meet the demand; S5.4 Perform quality inspection on the electroplated plates, including the inspection of coating thickness and uniformity index.

7. The method for simplifying PCB mixed pressure stacking design according to claim 6, characterized in that: The implementation process of step S6 is as follows: S6.

1. Repeat the cleaning, exposure, development and etching operations in step S1 to step S5. In this step, the exposure energy is selected to be 6-8 grids, and the expansion and contraction compensation is fine-tuned according to the physical board; S6.

2. Through the development, etching and film stripping operations, the required sub-outer layer circuit pattern is accurately presented on the copper clad laminate; S6.

3. Perform quality inspection on the sub-outer line to ensure line accuracy and integrity.

8. The method for simplifying PCB mixed pressure stacking design according to claim 7, characterized in that: The implementation process of step S7 is as follows: S7.

1. Brown all inner and outer layers of the board; S7.

2. Perform fusing and riveting operations to ensure that the layers are tightly bonded and have no gaps; S7.

3. Perform secondary pressing according to normal pressing parameters. The pressing parameters should be consistent with the first pressing to ensure the quality of the overall stacking structure. The temperature, pressure and time parameters should be strictly controlled during the pressing process; S7.4 Carry out quality inspection on the overall stacked structure after lamination, including inspection of interlayer bonding strength and board warpage index.

9. The method for simplifying PCB mixed pressure stacking design according to claim 8, characterized in that: The implementation process of step S8 is as follows: S8.

1. Use micro-etching solution to clean the board surface, then apply photosensitive dry film and perform exposure, development and etching operations to accurately present the required outer layer circuit pattern; S8.

2. Use volcanic ash and abrasive brushing to clean the board surface again, then print the photosensitive ink and perform exposure and development operations to form a solder mask to protect the circuit from damage; S8.

3. Use a text printer to print text to meet the needs, including product identification and production date information; S8.

4. Perform immersion gold, immersion tin, OSP or tin spraying surface treatment according to requirements to enhance the corrosion resistance and solderability of the board surface; S8.

5. The product is precisely molded with a molding accuracy of ±0.1mm and a special control accuracy of ±0.05mm to meet the dimensional accuracy requirements; S8.

6. Conduct continuity and insulation tests on the products to ensure that the circuit connections are correct. At the same time, use AVI 100% scanning to conduct appearance inspection against the required standards to select products that do not meet the requirements for repair or scrapping.

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