High-speed CMOS LVDS transmitter

Abstract

A high-speed CMOS LVDS transmitter disclosed by the present invention comprises a digital unit and an analog unit, the digital unit is used for generating a differential signal and a pre-emphasis signal, the analog unit is used for realizing analog differential output, and the digital unit comprises a level shift circuit module, a single-end-to-double-end circuit module and a pre-emphasis control signal module. The simulation unit comprises a current bias circuit module, an LVDS transmitter core circuit module and a common-mode feedback circuit module, the LVDS transmitter is simple in structure and ingenious in design, the speed and quality of signal transmission can be guaranteed, meanwhile, power consumption and production cost are reduced, the LVDS transmitter has great significance in development of the domestic high-speed transmission technology, the application prospect is wide, and the application range is wide. Popularization and application are facilitated.

Description

Technical Field

[0001] The invention relates to the technical field of signal transmission, and in particular to a high-speed CMOS LVDS transmitter. Background Art

[0002] At present, the standard interface technologies based on various signal transmissions such as TTL, CML, RS-422, RS-485, etc., which have been created, cannot continue to meet the needs of high-speed transmission required by current information transmission due to various limitations such as speed, power consumption, noise, electromagnetic interference, production cost and other factors. The emergence of LVDS interface technology solves this problem. It is a technology that uses low voltage and ensures the effective quality of the signal to achieve high-speed signal transmission. It stands out among various signal transmission technologies. Overall, the development of LVDS interface technology is meeting people's pursuit of signal transmission. However, the performance of many interface designs is not perfect and balanced, and it is impossible to ensure the quality of signal transmission while taking into account other important advantages. Therefore, it is urgent to develop a high-speed CMOS LVDS transmitter to solve the above technical problems.

[0003] In view of this, the present invention is proposed. Summary of the invention

[0004] The purpose of the present invention is to provide a high-speed CMOS LVDS transmitter with a simple structure and ingenious design. It can not only ensure the speed and quality of signal transmission, but also reduce power consumption and production costs. It is of great significance to the development of domestic high-speed transmission technology, has broad application prospects, and is conducive to popularization and application.

[0005] In order to achieve the above-mentioned object, the present invention provides a high-speed CMOS LVDS transmitter, comprising a digital unit and an analog unit, wherein the digital unit is used to generate a differential signal and a pre-emphasis signal, and the analog unit is used to realize an analog differential output, wherein the digital unit comprises a level shifting circuit module, a single-end to double-end circuit module and a pre-emphasis control signal module, and the analog unit comprises a current biasing circuit module, an LVDS transmitter core circuit module and a common-mode feedback circuit module; The level transfer circuit module adopts a level transfer circuit module of CMOS technology; The single-ended to double-ended circuit module has two functions: one is to enhance driving, and the other is to convert a single signal into a differential signal; The pre-emphasis control signal module has the function of turning off pre-emphasis, adopts testability design, and reserves key ports, which can not only test the working condition of the port, but also obtain output by inputting a signal to the port when LVDS cannot work normally; The current bias circuit module is used to provide the mirror current required by the transmitter for generating an appropriate bias voltage and reference current, and provide a reference voltage to the common-mode feedback circuit module; The circuit of the LVDS transmitter core circuit module is a dual-current main drive circuit. The current switch is composed of A1 and A2. OUTA and OUTB are the outputs of the drive circuit and are connected to the next stage. When A1 = 1 and A2 = 0, M1 and M3 are turned off, and M2 and M4 are turned on. At this time, OUTA is pulled to the high-level position and OUTB is pulled to the low-level position, forming a differential output signal; when A1 = 0 and A2 = 1, M1 and M3 are turned on, and M2 and M4 are turned off. At this time, OUTA is pulled to the low-level position and OUTB is pulled to the high-level position, forming a differential output signal; The common-mode feedback circuit module is used to increase the common-mode feedback network to detect the common-mode level output by the two output terminals. The process of common-mode feedback is to detect the common-mode level, compare it with the reference voltage, and then send the error back to the bias network of the amplifier.

[0006] Preferably, the circuit of the pre-emphasis control signal module is connected in parallel with the periphery of the circuit without the pre-emphasis control signal module to achieve the purpose of pre-emphasis. D1 and D2 are differential signals, and D1 controls the on and off of M1 and M2 transistors, and D2 controls the on and off of M3 and M4 transistors. D3, D4, D5, and D6 are pre-emphasis signals. D3 and D6, D4 and D5 are differential signals. D3 controls the on and off of M5, D4 controls the on and off of M6, D5 controls the on and off of M7, and D6 controls the on and off of M8. When D1 is high and D2 is low, or D1 is low and D2 is high, and M5, M6, M7, and M8 are all off, the current flows from R1 → R → R4, or from R3 → R → R2, and a signal is formed at both ends of AB. At this time, the circuit has no pre-emphasis function, which also realizes the controllable turn-off of pre-emphasis. When D1 is low and D3 is low, M1, M5, M4, and M8 are turned on, and the rest of the transistors are off. The current flows from R1 / / R5 → R → R4 / / R8; when D1 is high and D4 is high, that is, M2, M3, M6, and M7 are turned on, and the rest of the transistors are off. The current flows from R3 / / R7 → R → R2 / / R6. At this time, the circuit can achieve pre-emphasis.

[0007] Preferably, the digital unit is used to convert the input serial signal of the previous-stage ADC into a pair of differential signals and generate a pre-emphasis control signal, and the analog unit is used to complete the level conversion of the differential signals, converting a pair of digital input differential signals into a differential analog signal with an amplitude of 350 mV to reduce the transmission power consumption.

[0008] Preferably, the power supply voltage of the transmitter is 3.3V, the total current consumption is less than 4mA, the input signal frequency is 640MHz, the output load capacitance is 8.5pF, the typical value of the output amplitude is ±350mV, and the amplitude is required to be between 250mV and 450mV.

[0009] Preferably, the transmitter includes three types of ports, namely four power ground ports, eight analog ports, and nine digital ports. The power ground ports are: AVDD33, AVSS33, DVDD12, DGND. The analog ports are: IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, OUTN. The digital ports are: DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N.

[0010] Preferably, the input / output of the power ground ports AVDD33, AVSS33, DVDD12, DGND are all IN, and their functions and attributes are: analog power supply, analog ground, digital power supply, digital ground.

[0011] Preferably, the input / output of the analog ports IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, OUTN are respectively: IN, IN, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are: current mirror reference current, common mode feedback reference voltage, LEVEL SHIFT bias voltage, current mirror gate voltage output, current mirror gate voltage output, common mode level output, differential data output, differential data output.

[0012] Preferably, the input / output of the digital ports DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N are respectively IN, IN, OUT, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are: data input, system enable input, system enable output, pre-emphasis enable signal input, pre-emphasis enable signal output, analog BUFFER enable signal, analog BUFFER enable signal, current bias enable signal, current bias enable signal.

[0013] A high-speed CMOS LVDS transmitter provided by the present invention has the following beneficial effects.

[0014] 1. The present invention is a high-speed level. Compared with traditional levels, its voltage swing is low, enabling it to change its own current situation within a very short time range.

[0015] 2. Compared with levels such as TTL and LVPECL, the LVDS of the present invention has a simple design structure and adopts a differential signal transmission mode. It can still work properly within a relatively large range of interference during signal transmission compared to other interfaces. And a transmission driver is added at the sending end, and a receiving equalizer is added at the receiving end to enhance the driving ability of the signal, which can greatly increase the signal transmission distance and ensure signal transmission under the requirement of zero bit error rate.

[0016] 3. The power consumption of the present invention is relatively low. LVDS is driven by a constant current source, and different LVDS transmitters and receivers have different power consumption situations. Even when the operating frequency increases, the current remains constant. Such a driving mode greatly reduces the power consumption of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural block diagram of a high-speed CMOS LVDS transmitter provided by the present invention; Figure 2 is a working principle diagram of a high-speed CMOS LVDS transmitter provided by the present invention; Figure 3 is a port arrangement diagram of a high-speed CMOS LVDS transmitter provided by the present invention; Figure 4 is a circuit diagram of a pre-emphasis control signal module; Figure 5 is a dual-current main body drive circuit diagram of a LVDS transmitter core circuit module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following further describes the present invention in conjunction with specific embodiments and the accompanying drawings to facilitate understanding of the content of the present invention.

[0019] As Figure 1 shown, it is a structural block diagram of a high-speed CMOS LVDS transmitter provided by the present invention. The high-speed CMOS LVDS transmitter includes a digital unit and an analog unit. The digital unit is used to generate differential signals and pre-emphasis signals, and the analog unit is used to achieve analog differential output. The digital unit includes a level shift circuit module, a single-ended to differential-ended circuit module, and a pre-emphasis control signal module. The analog unit includes a current bias circuit module, a LVDS transmitter core circuit module, and a common-mode feedback circuit module; The level shift circuit module adopts a level shift circuit module using CMOS technology; since the power supply voltage and the core voltage are different in magnitude, level conversion is required when the data signal is transmitted to the LVDS transmitter. Therefore, a level shift circuit module using CMOS technology is adopted in the functional design.

[0020] The single-ended to differential circuit module has two functions: one is to enhance the drive, and the other is to convert a single signal into a differential signal; in order to ensure the driving ability of the circuit and enable the signal to pass through the circuit within a limited time, the size of the switching transistors of the LVDS driver is generally large, resulting in insufficient driving ability. In order to improve the speed and reduce the power consumption at the same time, the transistor size of the previous circuit part will be designed relatively small. Moreover, from the input of the main driving circuit, it can be seen that the input driving signal must be a differential signal. However, the signal output from the level shift circuit module is a single-level signal. Therefore, a single-ended to differential circuit module needs to be added between the level shift circuit module and the main circuit.

[0021] The pre-emphasis control signal module has the function of turning off the pre-emphasis. It adopts design for testability and reserves key ports, which can not only test the working conditions of the ports, but also obtain the output by inputting signals to this port when the LVDS cannot work properly; if an LVDS driver is to drive a very high load, such as a long cable, a highly capacitive cable, etc., in order to ensure that the LVDS driver can output a standard voltage range of 250mV - 450mV, the LVDS operating frequency needs to be appropriately reduced. This is because during the transmission of the signal in the medium, the high-frequency signal components will attenuate and delay during transmission, and then it will cause the received data signal swing at the receiver to be insufficient, ultimately resulting in incorrect information transmission, which is also called inter-symbol interference. In order to overcome the deficiencies of long-distance transmission, pre-emphasis technology needs to be used at the driver end to compensate for the high-frequency components of the signal. The working principle is: when the signal changes, the circuit deliberately overdrives the signal to make the signal overdriven. When the signal is continuous, the driving amount is reduced to reduce the signal swing (referred to as de-emphasis). Because many high-frequency signal components are concentrated at the rising edge of the transmission, overshoot will occur during the data transmission. Therefore, redundant high-frequency components will be added. However, when a series of identical data values appear continuously in the data, the low-frequency signal components will be dominant, and at this time the circuit will attenuate the data signal, that is, reduce the low-frequency components of the signal, and at this time the pre-emphasis of the signal is completed.

[0022] As Figure 4As shown in the figure, it is the circuit diagram of the pre-emphasis control signal module. A parallel path is added to the periphery of the circuit without the pre-emphasis control signal module to achieve the purpose of pre-emphasis. D1 and D2 are differential signals, and D1 controls the on and off of transistors M1 and M2, while D2 controls the on and off of transistors M3 and M4. D3, D4, D5, and D6 are the pre-emphasis signals. D3 and D6, D4 and D5 are differential signals. D3 controls the on and off of M5, D4 controls the on and off of M6, D5 controls the on and off of M7, and D6 controls the on and off of M8. When D1 is high and D2 is low, or D1 is low and D2 is high, and M5, M6, M7, and M8 are all off, the current flows from R1→R→R4, or from R3→R→R2, and a signal is formed at both ends of AB. At this time, the circuit does not have the function of pre-emphasis, which also realizes the controllable turn-off of pre-emphasis. When D1 is low and D3 is low, M1, M5, M4, and M8 are turned on, and the other transistors are turned off. The current flows from R1 / / R5→R→R4 / / R8; when D1 is high and D4 is high, that is, M2, M3, M6, and M7 are turned on, and the other transistors are turned off. The current flows from R3 / / R7→R→R2 / / R6. At this time, the circuit can achieve pre-emphasis. Compared with the circuit without the pre-emphasis control signal module, the resistance of the whole output is reduced by parallel resistors. Correspondingly, the current through the terminal resistor becomes larger, thus realizing the pre-emphasis effect, and the pre-emphasis effect can be improved by adjusting the value of the peripheral resistors.

[0023] The current bias circuit module is used to provide the mirror current required by the transmitter for generating an appropriate bias voltage and reference current, and provide a reference voltage to the common-mode feedback circuit module; the main performance includes the temperature coefficient of the output voltage and current and the power supply rejection ratio of the whole circuit, etc. A high-precision bias current has a great impact on the circuit and can even determine the accuracy of the circuit.

[0024] As Figure 5 As shown in the figure, it is the double-current main drive circuit diagram of the LVDS transmitter core circuit module. The circuit of the LVDS transmitter core circuit module is a double-current main drive circuit. The current switch is composed of A1 and A2. OUTA and OUTB are the outputs of the drive circuit and are connected to the next stage. When A1 = 1 and A2 = 0, M1 and M3 are turned off, and M2 and M4 are turned on. At this time, OUTA is pulled to the high-level position, and OUTB is pulled to the low-level position, forming a differential output signal; when A1 = 0 and A2 = 1, M1 and M3 are turned on, and M2 and M4 are turned off. At this time, OUTA is pulled to the low-level position, and OUTB is pulled to the high-level position, forming a differential output signal; There is noise both inside and outside the chip, which can cause the offset and fluctuation of the common-mode level during signal transmission. Therefore, it cannot meet the international standard of LVDS, that is, the common-mode level of the differential output at the driver output end is required to reach 1.125V - 1.275V. Moreover, the characteristics and adaptability of the device have high requirements for the output common-mode level, and it is impossible to achieve a stable effect by using differential-mode feedback. Therefore, a common-mode feedback network needs to be added to detect the common-mode level output by the two output ends. The common-mode feedback process of the common-mode feedback circuit module is to detect the common-mode level, compare it with the reference voltage, and then send the error back to the bias network of the amplifier.

[0025] The digital unit is used to convert the input serial signal of the previous-stage ADC into a pair of differential signals and generate a pre-emphasis control signal. The analog unit is used to complete the level conversion of the differential signals, converting a pair of digital input differential signals into differential analog signals with an amplitude of 350mV to reduce the transmission power consumption.

[0026] The power supply voltage of the transmitter is 3.3V, the total power consumption current is less than 4mA, the input signal frequency is 640MHz, the output load capacitance is 8.5pF, the typical value of the output amplitude is ±350mV, and the amplitude is required to be between 250mV - 450mV.

[0027] As Figure 3 shown, it is the port arrangement diagram of a high-speed CMOS LVDS transmitter provided by the present invention. The transmitter includes three types of ports, namely four power ground ports, eight analog ports and nine digital ports. The power ground ports are respectively: AVDD33, AVSS33, DVDD12, DGND. The analog ports are respectively: IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, OUTN. The digital ports are respectively: DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N. The specific port introduction is shown in Table 1: Table 1 Port Introduction The input / output of the power ground ports AVDD33, AVSS33, DVDD12, DGND are all IN, and their functions and attributes are respectively: analog power supply, analog ground, digital power supply, digital ground.

[0028] The inputs / outputs of the analog ports IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, and OUTN are respectively: IN, IN, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are respectively: current mirror reference current, common-mode feedback reference voltage, LEVEL SHIFT bias voltage, current mirror gate voltage output, current mirror gate voltage output, common-mode level output, differential data output, differential data output.

[0029] The inputs / outputs of the digital ports DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N are respectively IN, IN, OUT, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are respectively: data input, system enable input, system enable output, pre-emphasis enable signal input, pre-emphasis enable signal output, analog BUFFER enable signal, analog BUFFER enable signal, current bias enable signal, current bias enable signal.

[0030] The working principle of the present invention is as follows: As Figure 2 shown, it is the working principle diagram of a high-speed CMOS LVDS transmitter provided by the present invention. The CMOS LVDS transmitter is divided into two units: a digital unit and an analog unit. The digital unit includes a level shift circuit module, a single-ended to differential circuit module, and a pre-emphasis control signal module. The analog unit includes a current bias circuit module, an LVDS transmitter core circuit module, and a common-mode feedback circuit module. After the design is completed, PVT simulation is required to obtain the simulation results to verify whether the overall circuit situation meets the established goals, and finally, the layout drawing of each module is optimized through testing. The final parameters are as follows: the highest output frequency is 640 MHz; the typical value of the output amplitude is ±350 mV, and the range is between 250 mV - 450 mV; the working current < 5 mA.

[0031] The present invention is a high-speed level. Compared with traditional levels, its voltage swing is low, enabling it to change its current situation within a very short time range. Compared with levels such as TTL and LVPECL, the LVDS design has a simple structure and adopts a differential signal transmission mode, and can still work properly within a relatively large range of interference during signal transmission compared to other interfaces. Moreover, a transmission driver is added at the sending end, and a receiving equalizer is added at the receiving end to enhance the driving ability of the signal, which can greatly increase the signal transmission distance and ensure signal transmission with zero bit error rate. The present invention has low power consumption. LVDS is driven by a constant current source, and different LVDS transmitters and receivers have different power consumption situations. Even when the working frequency increases, the current remains constant, and such a driving mode greatly reduces the power consumption of signal transmission.

[0032] Specific examples are used in this article to elaborate on the inventive concept in detail. The description of the above embodiments is only used to help understand the core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, any obvious modifications, equivalent replacements, or other improvements made without departing from the inventive concept should be included within the protection scope of the present invention.

Claims

1. A high-speed CMOS LVDS transmitter, characterized in that, It includes a digital unit and an analog unit. The digital unit is used to generate differential signals and pre-emphasis signals, and the analog unit is used to achieve analog differential output. The digital unit includes a level-shifting circuit module, a single-ended to differential-ended circuit module, and a pre-emphasis control signal module. The analog unit includes a current bias circuit module, an LVDS transmitter core circuit module, and a common-mode feedback circuit module; The level-shifting circuit module is a level-shifting circuit module using CMOS process; The single-ended to differential-ended circuit module has two functions: one is to enhance the drive, and the other is to convert a single signal into a differential signal; The pre-emphasis control signal module has the function of turning off pre-emphasis. It adopts design for testability and reserves key ports, which can not only test the working conditions of the ports, but also obtain the output by inputting signals to this port when the LVDS cannot work properly; The current bias circuit module is used to provide the mirror current required by the transmitter for generating appropriate bias voltage and reference current, and provide a reference voltage to the common-mode feedback circuit module; The circuit of the LVDS transmitter core circuit module is a dual-current main body drive circuit. The current switch is composed of A1 and A2. OUTA and OUTB are the outputs of the drive circuit and are connected to the next stage. When A1 = 1 and A2 = 0, M1 and M3 are turned off, and M2 and M4 are turned on. At this time, OUTA is pulled to the high level position and OUTB is pulled to the low level position to form a differential output signal; when A1 = 0 and A2 = 1, M1 and M3 are turned on, and M2 and M4 are turned off. At this time, OUTA is pulled to the low level position and OUTB is pulled to the high level position to form a differential output signal; The common-mode feedback circuit module is used to increase the common-mode feedback network, which is used to detect the common-mode level output by the two output terminals. The process of common-mode feedback is to detect the common-mode level, compare it with the reference voltage, and then send the error back to the bias network of the amplifier.

2. The high-speed CMOS LVDS transmitter according to claim 1, wherein The circuit of the pre-emphasis control signal module is to connect a path in parallel to the periphery of the circuit without the pre-emphasis control signal module to achieve the purpose of pre-emphasis. D1 and D2 are differential signals, and D1 controls the on-off of M1 and M2 transistors, and D2 controls the on-off of M3 and M4 transistors. D3, D4, D5, and D6 are pre-emphasis signals. D3 and D6, D4 and D5 are differential signals. D3 controls the on-off of M5, D4 controls the on-off of M6, D5 controls the on-off of M7, and D6 controls the on-off of M8. When D1 is high and D2 is low or D1 is low and D2 is high, and M5, M6, M7, and M8 are all turned off, the current flows from R1→R→R4, or from R3→R→R2, and a signal is formed at both ends of AB. At this time, the circuit has no pre-emphasis function, which also realizes controllable turn-off of pre-emphasis. When D1 is low and D3 is low, M1, M5, M4, and M8 are turned on, and the rest of the transistors are turned off. The current flows from R1 / / R5→R→R4 / / R8; when D1 is high and D4 is high, that is, M2, M3, M6, and M7 are turned on, and the rest of the transistors are turned off. The current flows from R3 / / R7→R→R2 / / R6, and the circuit can achieve pre-emphasis at this time.

3. A high-speed CMOS LVDS transmitter according to claim 2, characterized in that, The digital unit is used to convert the input serial signal of the front-end ADC into a pair of differential signals and generate a pre-emphasis control signal. The analog unit is used to complete the level conversion of the differential signals, converting a pair of digital input differential signals into differential analog signals with an amplitude of 350 mV to reduce the transmission power consumption.

4. A high-speed CMOS LVDS transmitter according to claim 3, characterized in that, The power supply voltage of the transmitter is 3.3 V, the total power consumption current is less than 4 mA, the input signal frequency is 640 MHz, the output load capacitance is 8.5 pF, and the typical value of the output amplitude is ±350 mV. The amplitude is required to be between 250 mV and 450 mV.

5. The high-speed CMOS LVDS transmitter according to claim 4, characterized in that, The transmitter includes three types of ports, namely four power and ground ports, eight analog ports, and nine digital ports. The power and ground ports are respectively: AVDD33, AVSS33, DVDD12, DGND. The analog ports are respectively: IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, OUTN. The digital ports are respectively: DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N.

6. A high-speed CMOS LVDS transmitter according to claim 5, wherein, The input / output of the power and ground ports AVDD33, AVSS33, DVDD12, DGND are all IN, and their functions and attributes are respectively: analog power supply, analog ground, digital power supply, digital ground.

7. The high-speed CMOS LVDS transmitter according to claim 6, characterized in that, The input / output of the analog ports IREF_10u, VREF, VB, VBP, VBN, OUT_COM, OUTP, OUTN are respectively: IN, IN, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are respectively: current mirror reference current, common-mode feedback reference voltage, LEVEL SHIFT bias voltage, current mirror gate voltage output, current mirror gate voltage output, common-mode level output, differential data output, differential data output.

8. A high-speed CMOS LVDS transmitter according to claim 7, characterized in that, The input / output of the digital ports DATA, CORE_PDN_IN, CORE_PDN_OUT, PRE_EN, PRE_EN_OUT, AMPP_EN_P, AMPN_EN_P, CURRENT_COL_EN_P, CURRENT_COL_EN_N are respectively IN, IN, OUT, IN, OUT, OUT, OUT, OUT, OUT, and their functions and attributes are respectively: data input, system enable input, system enable output, pre-emphasis enable signal input, pre-emphasis enable signal output, analog BUFFER enable signal, analog BUFFER enable signal, current bias enable signal, current bias enable signal.

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