Level shift circuit with low time delay and low power consumption

Abstract

The invention discloses a low-delay low-power-consumption level shift circuit, relates to the technical field of integrated circuits, and is used for solving the problem that in the prior art, a high-voltage level shift circuit usually has large delay and power consumption. Comprising a low-power-consumption level shift circuit, a rapid falling edge capture circuit, a rapid rising edge capture circuit and an RS trigger. The low-power-consumption level shift circuit is connected with the input end of the fast falling edge capture circuit and the input end of the fast rising edge capture circuit, and the output end of the fast falling edge capture circuit and the output end of the fast rising edge capture circuit are both connected with the RS trigger. According to the invention, nanosecond-level delay and nanoampere-level static power consumption are realized while low-voltage domain signals in a specific range are converted into high-voltage domain signals in a preset range.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a low-delay and low-power level shifter circuit. Background Art

[0002] In most modern digital circuits and systems, level shifter circuits play a crucial role. They utilize multi-power voltage technology to enable each circuit sub-module to operate at the required power voltage. In particular, high-level shifter circuits can convert low-level signals into high-level signals, thereby achieving the control of high-voltage circuits by low-voltage signals. By adopting multiple power voltages, level shifters (LSs) establish connections between circuit sub-modules, ensuring the normal operation of the entire system.

[0003] With the continuous development of integrated circuit technology, reducing the power voltage has become an effective means to reduce circuit power consumption. However, lower power voltages also bring a series of challenges. Firstly, it limits the circuit speed, making the circuit potentially face performance bottlenecks when operating at high speeds. Secondly, lower power voltages affect the intrinsic gain and linearity of analog circuit modules, which may lead to a decline in signal quality. Therefore, how to maintain the high-speed performance and signal quality of the circuit while reducing power consumption has become an important issue in the design of level shifter circuits.

[0004] Therefore, there is an urgent need to provide a more reliable low-delay and low-power level shifter circuit. Summary of the Invention

[0005] The purpose of the present invention is to provide a low-delay and low-power level shifter circuit to solve the problem that high-voltage level shifter circuits in the prior art usually have large delays and high power consumption.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a low-delay and low-power level shifter circuit, including:

[0008] A low-power level shifter circuit, a fast falling-edge capture circuit, a fast rising-edge capture circuit, and an RS flip-flop;

[0009] The low-power level shifter circuit is respectively connected to the input ends of the fast falling-edge capture circuit and the fast rising-edge capture circuit, and the output ends of the fast falling-edge capture circuit and the fast rising-edge capture circuit are both connected to the RS flip-flop;

[0010] The fast falling-edge capture circuit and the fast rising-edge capture circuit capture the fast stage of the low-delay part before the step arrives and generate narrow pulse signals; the RS flip-flop restores the narrow pulse signals to normal square wave signals and outputs them.

[0011] Optionally, the low-power level-shifting circuit includes a first-stage current mirror structure, a cross-coupled structure, and a second-stage current mirror structure;

[0012] The cross-coupled structure includes a first-stage voltage withstand structure and a second-stage voltage withstand structure, and the first-stage voltage withstand structure and the second-stage voltage withstand structure are used to ensure that there are voltage steps during the rising edge and falling edge stages of the waveform.

[0013] Optionally, the first-stage voltage withstand structure is a 200V high-voltage PMOS transistor; the second-stage voltage withstand structure is a 200V high-voltage NMOS transistor;

[0014] The gate of the first-stage voltage withstand structure is connected to the high-voltage side voltage, and the gate of the second-stage voltage withstand structure is connected to the power supply voltage.

[0015] Optionally, the first-stage voltage withstand structure includes a first high-voltage PMOS transistor and a second high-voltage PMOS transistor; the second-stage voltage withstand structure includes a first high-voltage NMOS transistor and a second high-voltage NMOS transistor;

[0016] When the input signal is 0, the second node is pulled up to the VDDH potential, and the sixth NMOS transistor in the first-stage current mirror structure and the seventh NMOS transistor in the second-stage current mirror structure are turned on;

[0017] When the input signal transitions from a low level to a high level, the first NMOS transistor, the first high-voltage NMOS transistor, and the first high-voltage PMOS transistor in the cross-coupled structure are all turned on, the second PMOS transistor in the cross-coupled structure is turned on, pulling up the first node to the VDDH potential, the fifth NMOS transistor in the first-stage current mirror structure and the eighth NMOS transistor in the second-stage current mirror structure are turned on, and the first-stage current mirror structure and the second-stage current mirror structure are turned on, respectively generating a first current and a third current; the first current is copied to a second current through the current mirror structure composed of the third PMOS transistor and the fourth PMOS transistor in the first-stage current mirror structure, and the second current charges the gate of the first PMOS transistor in the cross-coupled structure.

[0018] Optionally, when the input signal is at a high level, the sixth NMOS transistor in the first-stage current mirror structure and the seventh NMOS transistor in the second-stage current mirror structure are turned off, respectively cutting off the current paths of the first-stage current mirror structure and the second-stage current mirror structure.

[0019] Optionally, when the input signal is 1, the first node is pulled up to the VDDH potential, and the fifth NMOS transistor in the first-stage current mirror structure and the eighth NMOS transistor in the second-stage current mirror structure are turned on;

[0020] When the input signal transitions from a high level to a low level, the second NMOS transistor, the second high-voltage NMOS transistor, and the second high-voltage PMOS transistor in the cross-coupled structure are all turned on; the first PMOS transistor in the cross-coupled structure is turned on, pulling up the second node to VDDH, and the sixth NMOS transistor in the first-stage current mirror structure and the seventh NMOS transistor in the second-stage current mirror structure are turned on.

[0021] Optionally, the first-stage current mirror structure and the second-stage current mirror structure are turned on to respectively generate the first current and the third current;

[0022] The third current is copied to the fourth current through the current mirror structure composed of the fifth PMOS transistor and the sixth PMOS transistor in the second-stage current mirror structure; the fourth current charges the gate of the second PMOS transistor.

[0023] Optionally, when the input signal is at a low level, the fifth NMOS transistor in the first-stage current mirror structure and the eighth NMOS transistor in the second-stage current mirror structure are turned off, respectively cutting off the current paths of the first-stage current mirror structure and the second-stage current mirror structure.

[0024] Optionally, in the fast falling-edge capture circuit and the fast rising-edge capture circuit, the threshold voltage is greater than the threshold voltage of the 20V NMOS transistor at the later stage of the low-power level shifter circuit. The fast falling-edge capture circuit and the fast rising-edge capture circuit capture the fast falling-edge portions of the first node and the second node and generate narrow pulses.

[0025] Optionally, when the signals of the first node and the second node are input into the fast falling-edge capture circuit and the fast rising-edge capture circuit, the delay circuit delays the first node and the second node. The delayed signals are shaped by the SMT flip-flop, inverted by the inverter, and then NANDed with the signals of the first node and the second node to output a narrow pulse signal.

[0026] Compared with the prior art, the present invention provides a low-delay and low-power level-shifting circuit. It includes a low-power level-shifting circuit, a fast falling-edge capture circuit, a fast rising-edge capture circuit, and an RS flip-flop; the low-power level-shifting circuit is respectively connected to the input ends of the fast falling-edge capture circuit and the fast rising-edge capture circuit, and the output ends of the fast falling-edge capture circuit and the fast rising-edge capture circuit are both connected to the RS flip-flop. The low-power level-shifting circuit causes voltage steps to exist in the rising-edge and falling-edge stages of the waveform, thereby increasing the overall delay of the circuit. The fast falling-edge capture circuit and the fast rising-edge capture circuit capture the fast stages of the low-delay part before the steps arrive and generate narrow pulse signals, thereby achieving nanosecond-level delay. While realizing the conversion of low-voltage domain signals within a specific range to high-voltage domain signals within a preset range, nanosecond-level delay and nanoampere-level static power consumption are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0028] Figure 1 Schematic diagram of a high-voltage current mirror level-shifting circuit of the prior art one;

[0029] Figure 2 Schematic diagram of a high-voltage cross-coupled level-shifting circuit of the prior art two;

[0030] Figure 3 Schematic diagram of a low-delay and low-power level-shifting circuit provided by the present application;

[0031] Figure 4 Schematic diagram of the structure of the low-power level-shifting circuit in a low-delay and low-power level-shifting circuit provided by the present application;

[0032] Figure 5 Timing diagram of a low-delay and low-power level-shifting circuit provided by the present invention;

[0033] Figure 6 Schematic diagram of the fast falling-edge capture circuit and the fast rising-edge capture circuit provided by the present invention;

[0034] Figure 7 Schematic diagram of the simulation results of the turn-on delay and static power consumption;

[0035] Figure 8 Schematic diagram of the simulation results of the turn-off delay and static power consumption.

[0036] Reference numerals:

[0037] 1 - Low - power level - shifting circuit, 2 - Fast - falling - edge capture circuit, 3 - Fast - rising - edge capture circuit, 4 - RS flip - flop, 11 - First - stage current - mirror structure, 12 - Cross - coupling structure, 13 - Second - stage current - mirror structure, HPM1 - First high - voltage PMOS transistor, HPM2 - Second high - voltage PMOS transistor, HNM1 - First high - voltage NMOS transistor, HNM2 - Second high - voltage NMOS transistor, N1 - First node, N2 - Second node, NM1 - First NMOS transistor, NM2 - Second NMOS transistor, NM3 - Third NMOS transistor, NM4 - Fourth NMOS transistor, NM5 - Fifth NMOS transistor, NM6 - Sixth NMOS transistor, NM7 - Seventh NMOS transistor, NM8 - Eighth NMOS transistor, PM1 - First PMOS transistor, PM2 - Second PMOS transistor, PM3 - Third PMOS transistor, PM4 - Fourth PMOS transistor, PM5 - Fifth PMOS transistor, PM6 - Sixth PMOS transistor, I1 - First current, I2 - Second current, I3 - Third current, I4 - Fourth current. Detailed implementation manners

[0038] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and roles. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different.

[0039] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0040] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or a similar expression refers to any combination of these items, including any combination of single item(s) or plural item(s). For example, at least one (item) of a, b, or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple.

[0041] Traditional level-shifting circuits are as shown in Prior Art 1 and Prior Art 2:

[0042] In Prior Art 1, a traditional high-voltage current mirror level-shifting circuit (Current Mirror LevelShifter, CMLS) is as Figure 1 shown. This circuit improves the breakdown voltage by adding a stage of high-voltage PMOS transistors (PL1, PL2) between the low-voltage domain (GND - V DDL ) and the high-voltage domain (VS - V DDH ). Its basic structure is an extended design based on the level-shifting circuit of the low-voltage domain CMLS. When the input signal IN changes from low level to high level, INb changes from high level to low level, N1 conducts, N2 turns off, and the voltage at point X is clamped to VS + V th (PL1). In this state, P2 conducts, and the output node OUT is pulled up to V DDH . Conversely, when the input signal IN changes from high level to low level, INb changes from low level to high level, N2 conducts, N1 turns off, the voltage at point OUT is clamped to VS + V th (PL2), and point X is pulled up to V DDH . Thus, the level conversion from the low-voltage domain to the high-voltage domain is achieved.

[0043] As can be seen from the timing diagram on the right in Prior Art 1 Figure 1 , when the input signal IN changes from low level to high level, N1, PL1, and P1 conduct, and there is a current path (Iloss), resulting in relatively large power consumption. When the input signal IN changes from high level to low level, N2, PL2, and P2 conduct, and there is also a current path, resulting in relatively large static power consumption.

[0044] In the second prior art, a traditional high-voltage cross-coupled level shifter (CCLS) is as follows Figure 2 shown. This circuit realizes the improvement of the withstand voltage ability by adding a stage of high-voltage PMOS transistors (PL1, PL2) between the low-voltage domain (GND - V DDL ) and the high-voltage domain (VS - V DDH ). Its basic structure is an extended design based on the level shifter circuit of the low-voltage domain CCLS. When the input signal IN changes from low level to high level, INb changes from high level to low level, N1 conducts, N2 turns off, and the voltage at point X is clamped to VS + V th (PL1). In this state, P2 conducts, and the output node OUT is pulled up to V DDH . Conversely, when the input signal IN changes from high level to low level, INb changes from low level to high level, N2 conducts, N1 turns off, the voltage at point OUT is clamped to VS + V th (PL2), and point X is pulled up to V DDH . Thus, the level conversion from the low-voltage domain (GND - V DDL ) to the high-voltage domain (VS - V DDH ) is achieved.

[0045] As can be seen from the timing diagram on the right in the second prior art Figure 2 , before the input signal IN transiently changes from low to high, IN is at low level and INB is at high level. At this time, the voltage at point OUT is VS + V th (PL2), and the voltage at point X is V DDH . When the input signal IN changes from low to high, during the conversion, at point X, it is pulled down from the potential of V DDH to the potential of VS + V th (PL1) by PL1 and N1, and the voltage at point OUT is pulled up from the potential of VS + V th (PL2) to the potential of V DDH by PL2 and N2. Because PL1 and PL2 have relatively large parasitic capacitances (Ciss, Coss), this will result in a weaker pull-down ability of OUT than the pull-up ability, and further lead to the output wave of OUT having a current competition problem at point OUT, thus increasing the delay of the circuit.

[0046] To solve the problems that the high-voltage level shifter circuit in the prior art usually has relatively large delay and power consumption, the present invention provides a low-delay and low-power level shifter circuit. Next, the solution provided in the embodiments of this specification will be described in conjunction with the accompanying drawings:

[0047] As Figure 3 shown, a low-delay and low-power level shifter circuit provided by the present invention may include:

[0048] A low-power level-shifting circuit 1, a fast falling-edge capture circuit 2, a fast rising-edge capture circuit 3, and an RS flip-flop 4;

[0049] The low-power level-shifting circuit 1 is respectively connected to the input end of the fast falling-edge capture circuit 2 and the input end of the fast rising-edge capture circuit 3, and the output ends of the fast falling-edge capture circuit 2 and the fast rising-edge capture circuit 3 are both connected to the RS flip-flop 4;

[0050] The fast falling-edge capture circuit 2 and the fast rising-edge capture circuit 3 capture the fast stage of the low-delay part before the step arrives and generate a narrow pulse signal; the RS flip-flop 4 restores the narrow pulse signal to a normal square-wave signal and outputs it.

[0051] Among them, Figure 3 For the low-delay and low-power level-shifting circuit, the input is a low-voltage domain signal of 0V - 15V, and the output is a high-voltage domain signal of 185V - 200V. Therefore, a low-delay and low-power level-shifting circuit provided by the present invention realizes the conversion of a low-voltage domain signal of 0V - 15V to a high-voltage domain signal of 185V - 200V.

[0052] Figure 3 The structure in includes a low-power level-shifting circuit 1, a fast falling-edge capture circuit 2, a fast rising-edge capture circuit 3, and an RS flip-flop 4; the low-power level-shifting circuit 1 is respectively connected to the input end of the fast falling-edge capture circuit 2 and the input end of the fast rising-edge capture circuit 3, and the output ends of the fast falling-edge capture circuit 2 and the fast rising-edge capture circuit 3 are both connected to the RS flip-flop 4. The low-power level-shifting circuit 1 makes the waveform have a voltage step in the rising-edge and falling-edge stages, thereby increasing the overall delay of the circuit. The fast falling-edge capture circuit 2 and the fast rising-edge capture circuit 3 capture the fast stage of the low-delay part before the step arrives and generate a narrow pulse signal, thereby realizing a nanosecond-level delay. While realizing the conversion of a low-voltage domain signal in a specific range to a high-voltage domain signal in a preset range, a nanosecond-level delay and a nanoampere-level static power consumption are achieved.

[0053] Based on Figure 3 the structure of, some specific implementation manners of this structure are also provided in the embodiments of this specification, which will be described below.

[0054] Figure 3 The low-power level-shifting circuit 1 in may include a first-stage current mirror structure 11, a cross-coupling structure 12, and a second-stage current mirror structure 13; more specifically, Figure 4 In, the first-stage current mirror structure 11 includes at least a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6.

[0055] The cross-coupling structure 12 includes at least a first PMOS transistor PM1, a second PMOS transistor PM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first high-voltage PMOS transistor HPM1, a second high-voltage PMOS transistor HPM2, a first high-voltage NMOS transistor HNM1, a second high-voltage NMOS transistor HNM2, a first NMOS transistor NM1, and a second NMOS transistor NM2.

[0056] The second-stage current mirror structure 13 includes at least a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8.

[0057] Further, the cross-coupling structure 12 includes a first-stage voltage withstand structure and a second-stage voltage withstand structure, and the first-stage voltage withstand structure and the second-stage voltage withstand structure are used to ensure that there are voltage steps during the rising edge and falling edge stages of the waveform. Among them, the first-stage voltage withstand structure includes a first high-voltage PMOS transistor HPM1 and a second high-voltage PMOS transistor HPM2;

[0058] The low-power level-shifting circuit 1 is composed of a cross-coupling structure 12 and two current mirror structures. Among them, HPM1 and HPM2 are 200V high-voltage PMOS transistors, HNM1 and HNM2 are 200V high-voltage NMOS transistors, and the remaining MOS transistors all use 20V MOS transistors. VS is connected to the gates of HPM1 and HPM2, and V DDL is connected to the gates of HNM1 and HNM2 to isolate the signals in the high-voltage domain and the low-voltage domain, thereby ensuring the reliability of the circuit.

[0059] For the low-power level-shifting circuit 1, combining Figure 4 and Figure 5 it can be known that when the input signal is 0, the second node N2 is pulled up to the V DDH potential, and the sixth NMOS transistor NM6 in the first-stage current mirror structure 11 and the seventh NMOS transistor NM7 in the second-stage current mirror structure 13 are turned on;

[0060] When the input signal transitions from a low level to a high level, the first NMOS transistor NM1, the first high-voltage NMOS transistor HNM1, and the first high-voltage PMOS transistor HPM1 in the cross-coupling structure 12 are all turned on, and the second PMOS transistor PM2 in the cross-coupling structure 12 is turned on to pull up the first node N1 to V DDHPotential, the fifth NMOS transistor NM5 in the first - stage current - mirror structure 11 and the eighth NMOS transistor NM8 in the second - stage current - mirror structure 13 are turned on, the first - stage current - mirror structure 11 and the second - stage current - mirror structure 13 are turned on, generating a first current I1 and a third current I3 respectively; the first current I1 is copied to a second current I2 through the current - mirror structure composed of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 in the first - stage current - mirror structure 11, and the second current I2 charges the gate of the first PMOS transistor PM1 in the cross - coupled structure 12. That is, when IN = "0": The N2 point is pulled high to V DDH Potential, NM6 and NM7 are turned on. When IN transitions from a low level to a high level, NM1, HNM1, and HPM1 are turned on, and HPM1 clamps its source (N2) to VS + V th(HPM1) Potential. PM2 is turned on, pulling up the N1 point to V DDH , NM8 and NM5 are turned on. The first - stage current - mirror structure 11 and the second - stage current - mirror structure 13 are turned on, generating a first current I1 and a third current I3 respectively. The first current I1 is copied to a second current I2 through the current - mirror structure composed of PM3 and PM4. The second current I2 charges the gate of PM1, thereby weakening the pulling - up ability of PM1 on the N2 node. The current competition problem of PM1 with NM1, HNM1, and HPM1 regarding the N2 point is solved. From Figure 5 It can be seen that the rapid pull - down of N2 is achieved. However, due to the large parasitic capacitance of HPM1 and the N2 node being clamped by HPM1, a step effect occurs when the N2 point rapidly pulls down to VS + V th(HPM1) Potential.

[0061] When the input signal is at a high level, the sixth NMOS transistor NM6 in the first - stage current - mirror structure 11 and the seventh NMOS transistor NM7 in the second - stage current - mirror structure 13 are turned off, respectively cutting off the current paths of the first - stage current - mirror structure 11 and the second - stage current - mirror structure 13. That is, IN = "1" (when IN is at a high level): NM6 and NM7 are turned off, respectively cutting off the current paths of the first - stage current - mirror structure 11 and the second - stage current - mirror structure 13. Therefore, there is no static - current power consumption.

[0062] When the input signal is 1, the first node N1 is pulled high to V DDHPotential, the fifth NMOS transistor NM5 in the first - stage current - mirror structure 11 and the eighth NMOS transistor NM8 in the second - stage current - mirror structure 13 are turned on; when the input signal transitions from a high level to a low level, the second NMOS transistor NM2, the second high - voltage NMOS transistor HNM2, and the second high - voltage PMOS transistor HPM2 in the cross - coupled structure 12 are all turned on; the first PMOS transistor PM1 in the cross - coupled structure 12 is turned on, pulling up the second node N2 to V DDH , the sixth NMOS transistor NM6 in the first - stage current - mirror structure 11 and the seventh NMOS transistor NM7 in the second - stage current - mirror structure 13 are turned on. The first - stage current - mirror structure 11 and the second - stage current - mirror structure 13 are turned on, generating the first current I1 and the third current I3 respectively; the third current I3 is copied to the fourth current I4 through the current - mirror structure composed of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 in the second - stage current - mirror structure 13; the fourth current I4 charges the gate of the second PMOS transistor PM2. That is, the transition of IN from high to low: from Figure 4 and Figure 5 it can be seen that when IN = "1", the point N1 is pulled up to V DDH potential, and NM5 and NM8 are turned on. When IN transitions from a high level to a low level, NM2, HNM2, and HPM2 are turned on, and HPM2 clamps its source (N1) to VS + V th(HPM2) potential. PM1 is turned on, pulling up the point N2 to V DDH , and NM6 and NM7 are turned on. The first - stage current - mirror structure 11 and the second - stage current - mirror structure 13 are turned on, generating the first current I1 and the third current I3 respectively. The third current I3 is copied to the fourth current I4 through the current - mirror structure composed of PM5 and PM6. I4 charges the gate of PM2, thereby weakening the pulling - up ability of PM2 on the N1 node. The current competition problem of PM2 with NM2, HNM2, and HPM2 regarding the N1 point is solved. From Figure 5 it can be seen that the rapid pull - down of N1 is achieved, but due to the large parasitic capacitance of HPM1 and the N1 node being clamped by HPM2, a step effect occurs when the N1 point rapidly pulls down to VS + V th(HPM2) potential.

[0063] When the input signal is at a high level, the sixth NMOS transistor NM6 in the first - stage current - mirror structure 11 and the seventh NMOS transistor NM7 in the second - stage current - mirror structure 13 are turned off, respectively cutting off the current paths of the first - stage current - mirror structure 11 and the second - stage current - mirror structure 13. When the input signal is at a low level, NM5 and NM8 are turned off, respectively cutting off the current paths of the first - stage current - mirror structure 11 and the second - stage current - mirror structure 13. Therefore, there is no static - current power consumption.

[0064] In the above structure, to achieve a breakdown voltage withstand capacity of 200V, a two-stage breakdown voltage structure is introduced in the design. The first-stage breakdown voltage structure consists of 200V high-voltage HPM1 and HPM2, and the second-stage breakdown voltage structure consists of 200V high-voltage HNM1 and HNM2. HNM1 and HNM2 clamp their source electrodes to V DDL +V th(HNM1，HNM2) potential. HPM1 and HPM2 clamp their source electrodes (N1, N2) to VS + V th(HPM1，HPM2) potential. However, due to the relatively large parasitic capacitances (CI SS , C OSS , C RSS ) of the 200V high-voltage transistors HPM1, HPM2, HNM1, and HNM2, the pull-down ability to the N1 and N2 nodes is greatly weakened. As shown in the timing diagram of Figure 5 , the weaker pull-down ability and the relatively large V th(HPM1，HPM2) result in voltage steps at the rising and falling edges of the waveform, thereby increasing the overall delay of the circuit. To solve this technical problem, the present invention further adds a fast falling edge capture circuit 2 and a fast rising edge capture circuit 3. That is, because there is a stepped voltage of VS + V th(HPM1，2) , and HPM1 and HPM2 are 200V high-voltage PMOS transistors. Their threshold voltages are often greater than the threshold voltage of the 20V NMOS at the later stage of the low-power level shifter circuit 1, which easily causes misflipping operations at the later stage, thereby increasing unnecessary delays. Therefore, a fast rising and falling edge capture circuit is designed, and its circuit structure is as shown in Figure 6 . It can capture the fast falling edge part of N1 and N2 as shown in the timing diagram of Figure 5 and generate narrow pulses of N1_out and N2_out.

[0065] When the N1 and N2 signals are input to the fast rising and falling edge capture circuit, a delay circuit composed of PM7, NM8, resistor (R6), and capacitor (C) delays N1 and N2, and then the delayed signals are shaped by an SMT flip-flop, and then inverted by an inverter and NANDed with the N1 and N2 signals, and finally output as narrow pulse signals. The RS flip-flop 4 restores the two narrow pulse signals into normal square wave signals and outputs them.

[0066] The corresponding technical effects of the above fast falling edge capture circuit 2 and fast rising edge capture circuit 3 are as follows:

[0067] The fast falling edge capture circuit 2 and the fast rising edge capture circuit 3 capture the fast stage of the low-delay part before the step arrives and generate narrow pulse signals, thereby achieving nanosecond-level delay. The RS flip-flop 4 restores the narrow pulse signals into normal square wave signals and outputs them.

[0068] By Figure 7 andFigure 8 For the simulation structure, the technical effects corresponding to the technical solution provided by the present invention can be deduced as follows:

[0069] From Figure 7 and Figure 8 the simulation results, it can be seen that the novel low-delay and low-power level shift circuit can achieve a 200V level shift at a frequency of 1MHz. Its turn-on delay is 3.14ns, and the static power consumption is 276.5nA. The turn-off delay is 4.19ns, and the static power consumption is 73.35nA. Therefore, the present invention provides a novel low-delay and low-power level shift circuit applicable to a 200V eGaN half-bridge drive chip, which realizes the conversion of signals in the low-voltage domain of 0V - 15V to signals in the high-voltage domain of 185V - 200V, and at the same time, achieves nanosecond-level delay and nanoampere-level static power consumption.

[0070] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0071] Although the present invention has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present invention. Accordingly, the present specification and the drawings are merely exemplary illustrations of the invention defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A low-latency and low-power level shift circuit, characterized in that: include: Low power level shift circuit, fast falling edge capture circuit, fast rising edge capture circuit and RS flip-flop; The low power consumption level shift circuit is connected to the input end of the fast falling edge capture circuit and the input end of the fast rising edge capture circuit respectively, and the output end of the fast falling edge capture circuit and the output end of the fast rising edge capture circuit are both connected to the RS trigger; The fast falling edge capture circuit and the fast rising edge capture circuit capture the fast phase of the low delay part before the step arrives and generate a narrow pulse signal; the RS trigger restores the narrow pulse signal to a normal square wave signal and outputs it.

2. The low-latency and low-power level shifting circuit according to claim 1, characterized in that: The low power consumption level shift circuit comprises a first-stage current mirror structure, a cross-coupling structure and a second-stage current mirror structure; The cross-coupling structure includes a first-level voltage-resistant structure and a second-level voltage-resistant structure, and the first-level voltage-resistant structure and the second-level voltage-resistant structure are used to ensure that there are voltage steps in the waveform at the rising edge and the falling edge stages.

3. The low-latency and low-power level shifting circuit according to claim 2, characterized in that: The first-level voltage-resistant structure is a 200V high-voltage PMOS tube; the second-level voltage-resistant structure is a 200V high-voltage NMOS tube; The gate of the first-level voltage-withstand structure is connected to the high-voltage side voltage, and the gate of the second-level voltage-withstand structure is connected to the power supply voltage.

4. The low-latency and low-power level shifting circuit according to claim 2, characterized in that: The first-level voltage-resistant structure includes a first high-voltage PMOS tube and a second high-voltage PMOS tube; the second-level voltage-resistant structure includes a first high-voltage NMOS tube and a second high-voltage NMOS tube; When the input signal is 0, the second node is pulled high to V DDH potential, the sixth NMOS transistor in the first-stage current mirror structure and the seventh NMOS transistor in the second-stage current mirror structure are turned on; When the input signal is converted from a low level to a high level, the first NMOS transistor, the first high-voltage NMOS transistor and the first high-voltage PMOS transistor in the cross-coupling structure are all turned on, and the second PMOS transistor in the cross-coupling structure is turned on, pulling the first node up to V DDH The fifth NMOS tube in the first-stage current mirror structure and the eighth NMOS tube in the second-stage current mirror structure are turned on, and the first-stage current mirror structure and the second-stage current mirror structure are turned on to generate a first current and a third current respectively; the first current is copied to the second current through the current mirror structure composed of the third PMOS tube and the fourth PMOS tube in the first-stage current mirror structure, and the second current charges the gate of the first PMOS tube in the cross-coupling structure.

5. The low-latency and low-power level shifting circuit according to claim 4, characterized in that: When the input signal is at a high level, the sixth NMOS tube in the first-stage current mirror structure and the seventh NMOS tube in the second-stage current mirror structure are turned off, respectively cutting off the current paths of the first-stage current mirror structure and the second-stage current mirror structure.

6. The low-latency and low-power level shifting circuit according to claim 4, characterized in that: When the input signal is 1, the first node is pulled high to V DDH potential, the fifth NMOS transistor in the first-stage current mirror structure and the eighth NMOS transistor in the second-stage current mirror structure are turned on; When the input signal is converted from a high level to a low level, the second NMOS transistor, the second high-voltage NMOS transistor and the second high-voltage PMOS transistor in the cross-coupling structure are all turned on; the first PMOS transistor in the cross-coupling structure is turned on, pulling the second node up to V DDH , the sixth NMOS tube in the first-stage current mirror structure and the seventh NMOS tube in the second-stage current mirror structure are turned on.

7. The low-latency and low-power level shifting circuit according to claim 6, characterized in that: The first-stage current mirror structure and the second-stage current mirror structure are turned on to generate the first current and the third current respectively; The third current is copied to a fourth current through a current mirror structure composed of a fifth PMOS tube and a sixth PMOS tube in the second-stage current mirror structure; and the fourth current charges the gate of the second PMOS tube.

8. The low-latency and low-power level shifting circuit according to claim 4, characterized in that: When the input signal is at a low level, the fifth NMOS tube in the first-stage current mirror structure and the eighth NMOS tube in the second-stage current mirror structure are turned off, thereby cutting off the current paths of the first-stage current mirror structure and the second-stage current mirror structure respectively.

9. The low-latency and low-power level shifting circuit according to claim 4, characterized in that: In the fast falling edge capture circuit and the fast rising edge capture circuit, the threshold voltage is greater than the threshold voltage of the 20V NMOS in the rear stage of the low-power level shift circuit. The fast falling edge capture circuit and the fast rising edge capture circuit capture the fast falling edge parts of the first node and the second node and generate a narrow pulse.

10. The low-latency and low-power level shifting circuit according to claim 8, characterized in that: When the signals of the first node and the second node are input into the fast falling edge capture circuit and the fast rising edge capture circuit, the first node and the second node are delayed by the delay circuit, the delayed signals are shaped by the SMT trigger, and after being inverted by the inverter, they are OR-ed with the signals of the first node and the second node to be output as narrow pulse signals.

Images