Digital clock data recovery circuit

Abstract

The invention belongs to the technical field of digital integrated circuits, and particularly relates to a digital clock data recovery circuit which comprises a phase-locked loop of a single-loop structure composed of a dual-mode bang-bang phase frequency detector, a digital state machine, a numerical control oscillator and a frequency divider, and efficient data recovery is achieved. According to the invention, additional reference clock input is not needed, so that the circuit complexity and cost are reduced; meanwhile, a binary fast search algorithm is adopted, and frequency locking can be completed in a short time; and through the design of the jitter suppression digital state machine, the output jitter is effectively controlled, and the accuracy of data recovery is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital integrated circuits, and particularly relates to a digital clock data recovery circuit. Background Art

[0002] Clock Data Recovery (CDR) technology is one of the key technologies in high-speed data transmission systems. Its purpose is to extract clock information from a clockless signal and use this clock information to re-time the input data, thereby achieving accurate data recovery. Currently, digital CDR circuits based on oversampling have been widely studied and applied due to their high precision and low sensitivity.

[0003] In the prior art, CDR circuits usually include modules such as a sampling synchronization unit and a shaping filter unit. However, these circuits have some problems, such as low tolerance to data jitter and insufficient ability to adapt to the difference between the input data rate and the system clock. In addition, some designs require an additional reference clock input, increasing complexity and cost. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a digital clock data recovery circuit, including: The circuit consists of a dual-mode bang-bang frequency discriminator and phase detector, a digital state machine, a numerically controlled oscillator, and a frequency divider to form a single-loop phase-locked loop to achieve efficient data recovery;

[0005] The dual-mode bang-bang frequency discriminator and phase detector operates in the synchronous signal systemclockpattern mode and switches to the random data processing mode after frequency locking;

[0006] The digital state machine adopts a binary fast search algorithm and a jitter suppression algorithm to achieve fast frequency locking and jitter suppression;

[0007] The numerically controlled oscillator generates a high-precision oscillation signal synchronized with the input data clock by dynamically adjusting the output frequency according to the control word output by the digital state machine to track the clock offset or jitter of the input data;

[0008] The frequency divider divides the high-frequency output of the numerically controlled oscillator to a frequency matching the input data rate for the dual-mode bang-bang frequency discriminator and phase detector to perform phase and frequency comparison.

[0009] Advantages of the Present Invention:

[0010] Low cost: The circuit is based on a single-loop phase-locked loop design, does not require an additional reference clock input, has an overall power consumption of only 1.279 mW@40 MHz (typical operating conditions) during operation, has a fast locking speed, good portability, and is insensitive to noises such as substrate coupling, reducing the circuit complexity cost.

[0011] Fast locking: The digital state machine of this circuit adopts a binary fast search algorithm, which can complete frequency locking in a short time;

[0012] Low jitter output: The digital state machine of this circuit controls the output jitter effectively through the design of a jitter suppression digital state machine, improving the accuracy of data recovery. Description of the Drawings

[0013] Figure 1 It is a schematic diagram of the overall structure of a digital clock data recovery circuit of the present invention;

[0014] Figure 2 It is a schematic diagram of the structure of the bang-bang frequency discriminator and phase detector of a digital clock data recovery circuit of the present invention;

[0015] Figure 3 It is a schematic diagram of the operation of the frequency discriminator and phase detector of a digital clock data recovery circuit of the present invention in a random data mode;

[0016] Figure 4 It is a schematic diagram of the binary search process of the digital state machine of a digital clock data recovery circuit of the present invention;

[0017] Figure 5 It is a schematic diagram of the jitter suppression filtering process of the digital state machine of a digital clock data recovery circuit of the present invention;

[0018] Figure 6 It is a diagram of the structure of the coarse adjustment stage and the simulation result of the structure of the coarse adjustment stage of a digital clock data recovery circuit of the present invention;

[0019] Figure 7 It is a schematic diagram of the fine adjustment structure of a digital clock data recovery circuit of the present invention. Detailed Embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0021] A digital clock data recovery circuit, as Figure 1 shown, includes: The circuit consists of a dual-mode bang-bang frequency discriminator and phase detector, a digital state machine, a numerically controlled oscillator, and a frequency divider to form a single-loop phase-locked loop to achieve efficient data recovery;

[0022] The dual-mode bang-bang frequency discriminator and phase detector operates in the system clock pattern of the synchronization signal. After frequency locking is completed, it switches to the random data processing mode;

[0023] The digital state machine adopts a binary fast search algorithm and a jitter suppression algorithm to achieve fast frequency locking and jitter suppression;

[0024] The numerically controlled oscillator generates a high-precision oscillation signal synchronized with the input data clock by dynamically adjusting the output frequency according to the control word output by the digital state machine to track the clock offset or jitter of the input data;

[0025] The frequency divider divides the high-frequency output of the numerically controlled oscillator to a frequency matching the input data rate for the dual-mode bang-bang frequency discriminator and phase detector to perform phase and frequency comparison.

[0026] Preferably, the dual-mode bang-bang frequency discriminator and phase detector, as Figure 2 shown, includes: a basic frequency discriminator and phase detector, two-stage time amplifiers, and one-stage edge detection flip-flops;

[0027] The two-stage time amplifiers can provide higher gain and linearity by amplifying the small time difference between the data and the clock edge, enabling digital logic to detect finer phase offsets, thereby optimizing the loop accuracy in high-frequency or low-jitter scenarios;

[0028] The one-stage edge detection flip-flops sample based on the amplified time difference signal through the clock edge, convert the analog time difference into a digital logic signal, achieve phase difference quantization through precise timing control, and cooperate with the time amplifiers to improve the resolution and noise immunity of the system.

[0029] In this embodiment, as Figure 2As shown in the figure, the working principle of the time amplifier is as follows: Taking the time amplifier TA1 as an example, assume that the phase of signal IN1 leads that of signal IN2, and both are temporarily at a low level. Then the outputs of inverters N1 and N2 are at a high level, N3 and N4 are at a low level, and N5 and N6 are at a high level. When IN1 is pulled high while IN2 remains unchanged, the output of N2 is pulled low, and then the NMOS transistor M3 conducts. Current I1 is turned off and I2 conducts, thus slowing down the falling speed of IN2. When the output of N3 is pulled high, both M4 and I2 are turned off, and the PMOS transistor M7 conducts. At this time, I4 conducts, thus slowing down the rising speed of N4. When the outputs of IN1 and IN2 both become low levels, both I3 and I4 are cut off. In this way, the time difference between signals IN1 and IN2 is widened, and the subsequent flip-flop can use a traditional DFF to complete signal sampling, realizing the quantization of pulses. Since the output signal is inverted every time it passes through a TA, in order to ensure the normal function of the phase detector PDC, there are slight differences in the selection of pull-up and pull-down transistors between the two stages of TA. In TA1, the PMOS of the second-stage inverter is matched, and the third-stage inverter is matched with NOMS, while TA2 is just the opposite.

[0030] As Figure 3 shown, the Bang-bang frequency discriminator and phase detector can select the corresponding working mode according to different inputs. When the synchronous pattern clock signal comes, the frequency discriminator and phase detector is similar to an ordinary Bang-bang frequency discriminator and phase detector, comparing the signal with the rising edge of the oscillator output at each clock edge and outputting a one-bit binary phase signal; when the circuit completes frequency and phase locking, the dual-mode Bang-bang frequency discriminator and phase detector will switch to the masked mode. At this time, under the condition of continuous 0 or 1 data input, the frequency discriminator and phase detector will not output a phase signal either. Only when there is edge information input for both the data and the oscillator simultaneously, will it output the corresponding phase signal.

[0031] Preferably, the digital state machine is the control unit of the clock data recovery circuit, consisting of two parts of digital circuits: a jitter suppression filtering algorithm and a binary search algorithm; its main function is to monitor the phase input of the frequency discriminator and phase detector, adjust the control code of the numerically controlled oscillator, and adjust the working mode of the frequency discriminator and phase detector according to the locking state. In the digital state machine of this design, a binary fast search algorithm is added to speed up the locking process. During the locking process, the digital state machine adjusts the control word according to the phase information in each clock cycle. If the polarity of the input phase signal changes, the frequency control word takes the average value of the current value and the frequency control word averaged with the adjacent previous change in phase polarity. As Figure 4 shown, the frequency control word approaches the target value quickly in this way. After completing frequency and phase locking, in order to suppress the output jitter of the clock data recovery circuit, as Figure 5As shown, its basic principle is that the filter does not adjust the frequency control word when each phase signal is input, but operates only under certain conditions. The specific process includes: counting the polarity and number of the input phase signals, and operating on the frequency control word only when the following two conditions are met: (1) continuously receiving phase signals of one polarity exceeds the set threshold threshold; (2) the polarity of adjacent two phase signals changes. When condition (1) is met, the state machine sets the threshold to twice the original value and clears the polarity statistical counter. When condition (2) is met, the counter is also cleared, but the threshold threshold is set to an initial value threshold_0.

[0032] The jitter suppression filtering algorithm digital circuit is used to monitor the phase input of the frequency discriminator and phase discriminator to adjust the control code of the numerically controlled oscillator, and adjust the working mode of the frequency discriminator and phase discriminator according to the locked state;

[0033] The binary fast search algorithm digital circuit is used to accelerate the locking process. During the locking process, the digital state machine adjusts the control word according to the phase information in each clock cycle. When the polarity of the input phase signal changes, the frequency control word takes the average value of the current value and the frequency control word averaged with the adjacent change in phase polarity.

[0034] Preferably, the numerically controlled oscillator adopts a three-stage cascaded ring structure, including: a first-stage coarse adjustment stage and two-stage fine adjustment;

[0035] The two-stage fine adjustment includes: a first-stage fine adjustment stage and a second-stage fine adjustment stage;

[0036] Both of the two-stage fine adjustment stages adopt a phase interpolation structure; the adjustment steps of both two-stage fine adjustment stages are 16 steps. The adjustment range of the first-stage fine adjustment stage is one coarse adjustment unit delay time (CDC), and the adjustment range of the second-stage fine adjustment stage is one step length of the first-stage fine adjustment stage.

[0037] The coarse adjustment stage adopts a path selection ladder structure, as Figure 6 (a) shows. Here, there are two groups of control codes sel and en. Sel controls the selection of the output path, and en controls the delay chain path. Among them, en[0] to en

[31] adopt thermometer codes, and the sel control code corresponding to the highest bit enabled by the en control code is enabled, and the rest of the sel control codes are grounded. The coarse adjustment stage selects the corresponding delay path length through the cooperation of the two groups of control codes, and outputs at ca_out and cb_out. The difference between these two outputs is one coarse adjustment delay unit delay (CDC). Simulation Figure 6 (b) shows that the output of this structure has good linearity. In order to achieve higher adjustment accuracy, the oscillator of the present application adds two more fine adjustment stages on the basis of the coarse adjustment stage. Both of these two fine adjustment stages adopt the same structure as Figure 7The multi-stage interpolation circuit structure shown, such as Figure 7 shown, uses a 4-bit binary control word, and the number of tri-state buffers controlled by the control word increases exponentially in binary by bit. The adjustment steps of both two-stage fine-tuning levels are 16 steps. The adjustment range of the first-stage fine-tuning level is one coarse-tuning unit delay time (CDC), and the adjustment range of the second-stage fine-tuning level is one step of the first-stage fine-tuning level. The verification results show that the numerically controlled oscillator outputs monotonically, and its linearity and resolution can meet the design requirements, and the power consumption is only 0.744 mw@40 MHz.

[0038] Although embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digital clock data recovery circuit, characterized in that: include: The circuit is composed of a dual-mode bang-bang frequency and phase detector, a digital state machine, a digitally controlled oscillator and a frequency divider to form a single-loop phase-locked loop to achieve efficient data recovery; The dual-mode bang-bang frequency and phase detector operates in the synchronization signal systemclockpattern mode, and switches to the random data processing mode after completing frequency locking; The digital state machine adopts a binary fast search algorithm and a jitter suppression algorithm to achieve fast frequency locking and jitter suppression; The digitally controlled oscillator generates a high-precision oscillation signal synchronized with the input data clock by dynamically adjusting the output frequency according to the control word output by the digital state machine and tracking the clock offset or jitter of the input data; The frequency divider divides the high frequency output of the digital controlled oscillator to a frequency matching the input data rate for phase and frequency comparison by the dual-mode bang-bang frequency and phase detector.

2. A digital clock data recovery circuit according to claim 1, characterized in that: The dual-mode bang-bang frequency detector and phase detector comprises: a basic frequency detector and a two-stage time amplifier and a first-stage edge detection trigger; The two-stage time amplifier can provide higher gain and linearity by amplifying the tiny time difference between the data and clock edges, enabling digital logic to detect more subtle phase offsets, thereby optimizing loop accuracy in high-frequency or low-jitter scenarios; The first-level edge detection trigger converts the analog time difference into a digital logic signal through clock edge sampling based on the amplified time difference signal, realizes phase difference quantization through precise timing control, and cooperates with the time amplifier to improve the resolution and noise resistance of the system.

3. A digital clock data recovery circuit according to claim 1, characterized in that: The Bang-bang frequency detector can select the corresponding working mode according to different inputs. When the synchronization pattern clock signal comes over, the frequency detector is similar to the ordinary bang-bang frequency detector. It compares the signal and the rising edge of the oscillator output at each clock edge and outputs a one-bit binary phase signal. When the circuit completes the frequency phase lock, the dual-mode bang-bang frequency detector will switch to the mask shielding mode. At this time, under the condition of continuous 0 or 1 data input, the frequency detector will not output a phase signal. Only when the data and the oscillator have edge information input at the same time, will it output the corresponding phase signal.

4. A digital clock data recovery circuit according to claim 1, characterized in that: The digital state machine includes two digital circuits: a jitter suppression filter algorithm and a binary search algorithm; The jitter suppression filter algorithm digital circuit is used to monitor the phase input of the frequency detector to adjust the control code of the digital controlled oscillator, and adjust the working mode of the frequency detector according to the locking state; The binary fast search algorithm digital circuit is used to speed up the locking process. During the locking process, the digital state machine adjusts the control word according to the phase information in each clock cycle. If the polarity of the input phase signal changes, the frequency control word takes the average value of the current value and the frequency control word after the adjacent phase polarity change.

5. The digital clock data recovery circuit according to claim 1, characterized in that: The digital controlled oscillator adopts a three-stage cascade adjustment ring structure, including: a first stage of coarse adjustment and two stages of fine adjustment; The two-stage fine adjustment includes: a primary fine adjustment stage and a secondary fine adjustment stage; The coarse adjustment stage adopts a two-path path selection ladder structure, and the two fine adjustment stages both adopt a phase interpolation structure; the adjustment steps of the two fine adjustment stages are both 16 steps, the adjustment range of the first fine adjustment stage is a coarse adjustment unit delay time (CDC), and the adjustment range of the second fine adjustment stage is a step length of the first fine adjustment stage.

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