Multistage all-digital adaptive equalization device suitable for echo high-speed data transmission signals

Abstract

The invention discloses a multi-stage all-digital adaptive equalization device suitable for echo high-speed data transmission signals, and belongs to the field of communication and data transmission. The device comprises an ADC (Analog to Digital Converter), a digital down-conversion module, a digital resampling module, a matched filtering module, a self-adaptive multipath offset equalization module, a carrier synchronization module, a timing synchronization module and a self-adaptive inter-symbol crosstalk offset equalization module. Compared with a traditional self-adaptive equalization device, pilot frequency transmission is not needed, an all-digital implementation scheme is adopted, the equalization process is reasonably decomposed into a two-stage equalization processing process, and the flexibility and stability of the equalization device are improved. Hardware logic resources required for realizing the device are relatively small, the realization complexity is low, and the device is convenient to realize and popularize.

Description

Technical Field

[0001] The present invention relates to the field of communication and data transmission, and in particular to a multi-stage all-digital adaptive equalization device applicable to echo high-speed data transmission signals, which can be used for demodulation synchronization and adaptive equalization in the data receiving subsystem of a ground receiving station for echo high-speed data transmission signals. Background Art

[0002] Traditional adaptive equalization devices are generally divided into pilot-based adaptive equalization devices and pilotless equalization devices. Pilot-based equalization devices will occupy the effective signal transmission bandwidth and reduce the signal transmission efficiency. Pilotless equalization devices mainly have two categories. The first type of equalization device needs to complete the compensation of signal waveform distortion through adaptive filtering under the condition of completing timing synchronization or carrier synchronization. The advantage of this type of adaptive equalization is excellent performance, but the disadvantage is that it depends on timing synchronization or carrier synchronization. When timing synchronization or carrier synchronization fails due to large signal distortion, adaptive equalization cannot be completed. The second type of equalization device is a pre-equalizer, which is a fixed coefficient equalizer. It needs to rely on testing and calibration of the transmission channel before the task and perform pre-equalization processing on the data before timing and carrier synchronization to compensate for the distortion of the signal generated by the channel. The advantage of this type of equalization is that it can reduce the impact of the channel on timing synchronization or carrier synchronization, thereby improving the system adaptability. However, the disadvantage is that the calibration process is relatively independent, and with the change of the channel, its real-time performance is poor, and the channel calibration process requires the cooperation of the signal sending end and the signal receiving end, which increases the complexity of system use and also brings additional signal transmission overhead. Summary of the Invention

[0003] The purpose of the present invention is to provide a multi-stage all-digital adaptive equalization device applicable to echo high-speed data transmission signals, avoiding the deficiencies in the above background art. The present invention has the characteristics of high implementation reliability, high stability, and low implementation complexity.

[0004] The purpose of the present invention is achieved as follows:

[0005] A multi-stage all-digital adaptive equalization device applicable to echo high-speed data transmission signals includes an analog-to-digital converter 1, a digital down-conversion module 2, a digital resampling module 3, a matched filtering module 4, an adaptive multipath cancellation equalization module 5, a carrier synchronization module 6, a timing synchronization module 7, and an adaptive inter-symbol interference cancellation equalization module 8;

[0006] Among them, the analog-to-digital converter 1 samples and digitizes the input analog intermediate frequency signal and transmits the digital intermediate frequency signal to the digital down-conversion module 2;

[0007] The digital down-conversion module 2 performs quadrature down-conversion processing on the digital intermediate frequency signal to generate I / Q two-way digital baseband signals and transmits them to the digital resampling module 3;

[0008] The digital resampling module 3 resamples the I / Q two-channel digital baseband signals at an integer multiple of the symbol rate, and the resampled I / Q two-channel digital baseband signals are transmitted to the matched filtering module 4;

[0009] The matched filtering module 4 performs matched filtering on the resampled I / Q two-channel digital baseband signals to generate I / Q two-channel digital baseband signals after matched filtering, and transmits them to the adaptive multipath cancellation and equalization module 5;

[0010] The adaptive multipath cancellation and equalization module 5 performs adaptive equalization on the I / Q two-channel digital baseband signals after matched filtering to cancel the multipath signals, generates I / Q two-channel digital baseband signals after equalization, and transmits them to the carrier synchronization module 6;

[0011] The carrier synchronization module 6 generates a local carrier signal, completes carrier synchronization and carrier demodulation, generates I / Q two-channel digital baseband signals, and transmits them to the timing synchronization module 7;

[0012] The timing synchronization module 7 completes symbol timing synchronization, generates I / Q two-channel digital baseband signals after timing synchronization, and transmits them to the adaptive inter-symbol interference cancellation and equalization module 8;

[0013] The adaptive inter-symbol interference cancellation and equalization module 8 performs adaptive equalization on the I / Q two-channel digital baseband signals after timing synchronization to cancel the inter-symbol interference, generates I / Q two-channel baseband signals after equalization as the output of this device; in addition, the adaptive inter-symbol interference cancellation and equalization module 8 transmits the I / Q two-channel equalization error signals and data power signals to the adaptive multipath cancellation and equalization module 5 to assist the adaptive multipath cancellation and equalization module 5 to complete the equalization process.

[0014] Further, the adaptive multipath cancellation and equalization module 5 includes a first squaring operation module 9-1, a second squaring operation module 9-2, an addition module 10, a division module 11, an accumulation module 12, a fixed step coefficient and delay adjustment state machine 13, a first fixed step coefficient adjustment unit 14-1 to an eighth fixed step coefficient adjustment unit 14-8, a first complex multiplier 15-1 to a fourth complex multiplier 15-4, a first variable delay unit 16-1 to an eighth variable delay unit 16-8, a fixed delay unit 17, a first multi-way adder 18-1, and a second multi-way adder 18-2;

[0015] Among them, the first squaring operation module 9-1 and the second squaring operation module 9-2 respectively receive the I / Q two-channel equalization error signals output by the adaptive inter-symbol interference cancellation and equalization module 8, perform squaring operations on the input signals respectively, and transmit them to the addition module 10;

[0016] The addition module 10 performs an addition operation on the two received signals and outputs;

[0017] The division module 11 receives the signal output by the addition module 10, and at the same time receives the data power signal output by the adaptive inter-symbol interference cancellation equalization module 8, completes the division operation, and outputs the operation result;

[0018] The accumulation module 12 receives the signal output by the division module 11, performs accumulation processing on the received signal, and transmits the processed signal to the fixed step coefficient and delay adjustment state machine 13;

[0019] The fixed step coefficient and delay adjustment state machine 13 respectively controls the first variable delay unit 16-1 to the eighth variable delay unit 16-8 and the first fixed step coefficient adjustment unit 14-1 to the eighth fixed step coefficient adjustment unit 14-8 through the state adjustment signals S1 to S16, and periodically traverses all delay and coefficient adjustable values; during the periodic traversal process, the accumulated signals output by the accumulation module 12 are recorded in sequence; when the periodic traversal is completed, the fixed step coefficient and delay adjustment state machine 13 selects the optimal control amount according to the accumulated signal values recorded in sequence, and finally completes the control and adjustment of the first variable delay unit 16-1 to the eighth variable delay unit 16-8 and the first fixed step coefficient adjustment unit 14-1 to the eighth fixed step coefficient adjustment unit 14-8 through the state adjustment signals;

[0020] The first fixed step coefficient adjustment unit 14-1 to the eighth fixed step coefficient adjustment unit 14-8 receive the state adjustment signals output by the fixed step coefficient and delay adjustment state machine 13, and adjust the output signal values with a fixed step;

[0021] The first variable delay unit 16-1 to the eighth variable delay unit 16-8 receive the state adjustment signals output by the fixed step coefficient and delay adjustment state machine 13, adjust the delay of the input signal with a fixed step, and output the delayed signal; among them, the first variable delay unit 16-1 and the fifth variable delay unit 16-5 respectively receive the I / Q two-channel digital baseband signals output by the matched filtering module 4, perform delay processing on the received signals respectively and output; the second variable delay unit 16-2 and the sixth variable delay unit 16-6 respectively receive the signals output by the first variable delay unit 16-1 and the fifth variable delay unit 16-5, perform delay processing on the received signals respectively and output; the third variable delay unit 16-3 and the seventh variable delay unit 16-7 respectively receive the signals output by the second variable delay unit 16-2 and the sixth variable delay unit 16-6, perform delay processing on the received signals respectively and output; the fourth variable delay unit 16-4 and the eighth variable delay unit 16-8 respectively receive the signals output by the third variable delay unit 16-3 and the seventh variable delay unit 16-7, perform delay processing on the received signals respectively and output;

[0022] The first complex multiplier 15-1 receives a complex signal composed of the output signals of the first fixed step coefficient adjustment unit 14-1 and the fifth fixed step coefficient adjustment unit 14-5, and at the same time receives a complex signal composed of the output signals of the first variable delay unit 16-1 and the fifth variable delay unit 16-5, completes complex multiplication and outputs;

[0023] The second complex multiplier 15-2 receives a complex signal composed of the output signals of the second fixed step coefficient adjustment unit 14-2 and the sixth fixed step coefficient adjustment unit 14-6, and at the same time receives a complex signal composed of the output signals of the second variable delay unit 16-2 and the sixth variable delay unit 16-6, completes complex multiplication and outputs;

[0024] The third complex multiplier 15-3 receives a complex signal composed of the output signals of the third fixed step coefficient adjustment unit 14-3 and the seventh fixed step coefficient adjustment unit 14-7, and at the same time receives a complex signal composed of the output signals of the third variable delay unit 16-3 and the seventh variable delay unit 16-7, completes complex multiplication and outputs;

[0025] The fourth complex multiplier 15-4 receives a complex signal composed of the output signals of the fourth fixed step coefficient adjustment unit 14-4 and the eighth fixed step coefficient adjustment unit 14-8, and at the same time receives a complex signal composed of the output signals of the fourth variable delay unit 16-4 and the eighth variable delay unit 16-8, completes complex multiplication and outputs;

[0026] The first multi-channel adder 18-1 respectively receives the Q-channel signals output by the first complex multiplier 15-1 to the fourth complex multiplier 15-4, and at the same time receives the Q-channel signals output by the fixed delay unit 17, completes multi-channel addition operation and outputs to the carrier synchronization module 6;

[0027] The second multi-channel adder 18-2 respectively receives the I-channel signals output by the first complex multiplier 15-1 to the fourth complex multiplier 15-4, and at the same time receives the I-channel signals output by the fixed delay unit 17, completes multi-channel addition operation and outputs to the carrier synchronization module 6;

[0028] The fixed delay unit 17 receives the I / Q two-channel baseband signals output by the matched filter 4, and after fixed delay processing, transmits them to the first multi-channel adder 18-1 and the second multi-channel adder 18-2 respectively.

[0029] Furthermore, the adaptive inter-symbol interference cancellation and equalization module 8 includes a digital AGC 19, a branch delay module 20, a parallel convolution operation module 21, a convolution coefficient generation module 22, a data extraction module 23, and an error extraction module 24;

[0030] Among them, the digital AGC 19 performs signal power detection and power adjustment on the input I / Q two-way digital baseband signals, transmits the power-adjusted I / Q two-way digital baseband signals to the branch delay module 20, and transmits the data power signal to the adaptive multipath cancellation equalization module 5;

[0031] The branch delay module 20 performs branch and independent delay processing on the received I / Q two-way digital baseband signals to generate two groups of I / Q two-way digital baseband signals. Among them, the first group of I / Q two-way digital baseband signals is transmitted to the parallel convolution operation module 21, and the second group of I / Q two-way digital baseband signals is transmitted to the convolution coefficient generation module 22;

[0032] The parallel convolution operation module 21 receives the I / Q two-way convolution coefficients transmitted by the convolution coefficient generation module 22, performs convolution operations on the input I / Q two-way digital baseband signals, generates the processed I / Q two-way digital baseband signals, and transmits them to the data extraction module 23;

[0033] The data extraction module 23 respectively extracts the peak points of the input I / Q two-way digital baseband signals and outputs them. The I / Q two-way digital baseband signals output by the data extraction module 23 are branched to generate two groups of I / Q two-way digital baseband signals. Among them, the first group of I / Q two-way digital baseband signals is used as the output signal of the device, and this output signal is the equalized I / Q two-way digital baseband signal, and the second group of I / Q two-way digital baseband signals is transmitted to the error extraction module 24;

[0034] The error extraction module 24 processes the input I / Q two-way digital baseband signals, generates and outputs two groups of I / Q two-way equalization error signals. Among them, the first group of I / Q two-way equalization error signals is transmitted to the convolution coefficient generation module 22, and the second group of I / Q two-way equalization error signals is transmitted to the adaptive multipath cancellation equalization module 5;

[0035] The convolution coefficient generation module 22 receives the second group of I / Q two-way digital baseband signals output by the branch delay module 20 and the first group of I / Q two-way equalization error signals output by the error extraction module 24, calculates and generates I / Q two-way convolution coefficient signals, and outputs them to the parallel convolution operation module 21.

[0036] The present invention has the following advantages compared with the background technology:

[0037] 1. Compared with the traditional adaptive equalization device, the present invention does not need to transmit pilots and adopts a fully digital implementation scheme, reasonably decomposes the equalization process into a two-stage equalization process, and improves the flexibility and stability of the equalization device.

[0038] 2. Before carrier synchronization and timing synchronization, the present invention uses the second-stage equalization feedback signal to complete the first-stage adaptive equalization, decoupling the equalization process from carrier synchronization and timing synchronization. The first-stage adaptive equalization can effectively cancel out multipath signals, significantly improving the working threshold of carrier synchronization and timing synchronization in a multipath channel, thereby enhancing the adaptability and receiving sensitivity of the device.

[0039] 3. After carrier synchronization and timing synchronization, the present invention completes the second-stage adaptive equalization, which can effectively cancel out the influence of inter-symbol interference on the demodulation performance, thereby improving the demodulation performance of the device.

[0040] 4. The present invention can be implemented based on FPGA, adopting a fully digital processing flow, with a simple structure and strong portability. Since units such as subtractors, numerical comparators, multipliers, and adders are integrated in FPGA, it is more convenient to implement and promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is the principle block diagram of the present invention.

[0042] Figure 2 is Figure 1 the circuit schematic diagram of the adaptive multipath cancellation equalization module in

[0043] Figure 3 is Figure 1 the circuit schematic diagram of the adaptive inter-symbol interference cancellation equalization module in DETAILED DESCRIPTION OF THE INVENTION

[0044] A multi-stage fully digital adaptive equalization device applicable to echo high-speed data transmission signals, referring to Figure 1 , includes an analog-to-digital converter (ADC) 1, a digital down-conversion module 2, a digital resampling module 3, a matched filtering module 4, an adaptive multipath cancellation equalization module 5, a carrier synchronization module 6, a timing synchronization module 7, and an adaptive inter-symbol interference cancellation equalization module 8.

[0045] Among them, the ADC 1 samples and digitizes the input analog intermediate-frequency signal, and transmits the digital intermediate-frequency signal to the digital down-conversion module 2;

[0046] The digital down-conversion module 2 performs quadrature down-conversion processing on the digital intermediate-frequency signal, generating I / Q two-way digital baseband signals and transmitting them to the digital resampling module 3;

[0047] The digital resampling module 3 performs resampling of the I / Q two-way digital baseband signals at an integer multiple of the symbol rate, and the resampled I / Q two-way digital baseband signals are transmitted to the matched filtering module 4;

[0048] The matched filtering module 4 performs matched filtering on the resampled I / Q digital baseband signals of both paths, generating the I / Q digital baseband signals after matched filtering of both paths and transmitting them to the adaptive multipath cancellation and equalization module 5;

[0049] The adaptive multipath cancellation and equalization module 5 performs adaptive equalization on the I / Q digital baseband signals after matched filtering of both paths, cancels the multipath signals, generates the I / Q digital baseband signals after equalization of both paths and transmits them to the carrier synchronization module 6;

[0050] The carrier synchronization module 6 generates a local carrier signal, completes carrier synchronization and carrier demodulation, generates the I / Q digital baseband signals of both paths and transmits them to the timing synchronization module 7;

[0051] The timing synchronization module 7 completes symbol timing synchronization, generates the I / Q digital baseband signals after timing synchronization of both paths and transmits them to the adaptive inter-symbol interference cancellation and equalization module 8;

[0052] The adaptive inter-symbol interference cancellation and equalization module 8 performs adaptive equalization on the I / Q digital baseband signals after timing synchronization of both paths, cancels the inter-symbol interference, generates the equalized I / Q baseband signals of both paths as the output of this device; meanwhile, the adaptive inter-symbol interference cancellation and equalization module 8 transmits the I / Q equalization error signals and data power signals of both paths to the adaptive multipath cancellation and equalization module 5 to assist the adaptive multipath cancellation and equalization module 5 in completing the equalization process.

[0053] In the embodiment, the digital down-conversion module 2, the digital resampling module 3, the matched filtering module 4, the adaptive multipath cancellation and equalization module 5, the carrier synchronization module 6, the timing synchronization module 7, and the adaptive inter-symbol interference cancellation and equalization module 8 are all implemented using the Virtex7 type FPGA.

[0054] Figure 2 is the principle block diagram of the adaptive multipath cancellation and equalization module. The embodiment is according to Figure 2 the connection lines. The adaptive multipath cancellation and equalization module 5 includes a square operation module 9-1 and a square operation module 9-2, an addition module 10, a division module 11, an accumulation module 12, a fixed step coefficient and delay adjustment state machine 13, fixed step coefficient adjustment units 14-1 to 14-8, complex multipliers 15-1 to 15-4, variable delay units 16-1 to 16-8, a fixed delay unit 17, and multiplexed addition modules 18-1 to 18-2.

[0055] Among them, the square operation module 9-1 and the square operation module 9-2 respectively receive the I / Q equalization error signals output by the adaptive inter-symbol interference cancellation and equalization module 8, perform square operations on the input signals respectively and transmit them to the addition module 10;

[0056] The addition module 10 performs an addition operation on the two received signals and outputs the result;

[0057] The division module 11 receives the signal transmitted by the addition module 10 and simultaneously receives the data power signal output by the adaptive inter-symbol interference cancellation equalization module 8, performs a division operation, and outputs the operation result;

[0058] The accumulation module 12 receives the signal output by the division module 11, performs an accumulation process on the received signal, and transmits the processed signal to the fixed step coefficient and delay adjustment state machine 13;

[0059] The fixed step coefficient and delay adjustment state machine 13 controls the variable delay units 16-1 to 16-8 and the fixed step coefficient adjustment units 14-1 to 14-8 respectively through the state adjustment signals S1 to S16, and periodically traverses all adjustable delay and coefficient values; during the periodic traversal process, the accumulated signals output by the accumulation module 12 are recorded in sequence. When the periodic traversal is completed, the fixed step coefficient and delay adjustment state machine 13 selects the optimal control quantity according to the sequentially recorded accumulated signal values, and finally completes the control and adjustment of the variable delay units 16-1 to 16-8 and the fixed step coefficient adjustment units 14-1 to 14-8 through the state adjustment signals;

[0060] The fixed step coefficient adjustment units 14-1 to 14-8 receive the state adjustment signals output by the fixed step coefficient and delay adjustment state machine 13, and adjust their output signal values with a fixed step;

[0061] The variable delay units 16-1 to 16-8 receive the state adjustment signals output by the fixed step coefficient and delay adjustment state machine 13, adjust the delay of the input signal with a fixed step, and output the delayed signal; among them, the variable delay unit 16-1 and the variable delay unit 16-5 respectively receive the I / Q two-channel digital baseband signals output by the matched filter module 4, perform delay processing on the received signals and output them. The variable delay unit 16-2 and the variable delay unit 16-6 respectively receive the signals output by the variable delay unit 16-1 and the variable delay unit 16-5, perform delay processing on the received signals and output them. The variable delay unit 16-3 and the variable delay unit 16-7 respectively receive the signals output by the variable delay unit 16-2 and the variable delay unit 16-6, perform delay processing on the received signals and output them. The variable delay unit 16-4 and the variable delay unit 16-8 respectively receive the signals output by the variable delay unit 16-3 and the variable delay unit 16-7, perform delay processing on the received signals and output them;

[0062] The complex multiplier 15-1 receives the complex signal composed of the output signals of the fixed step coefficient adjustment unit 14-1 and the fixed step coefficient adjustment unit 14-5, and at the same time receives the complex signal composed of the output signals of the variable delay unit 16-1 and the variable delay unit 16-5, completes complex multiplication and outputs;

[0063] The complex multiplier 15-2 receives the complex signal composed of the output signals of the fixed step coefficient adjustment unit 14-2 and the fixed step coefficient adjustment unit 14-6, and at the same time receives the complex signal composed of the output signals of the variable delay unit 16-2 and the variable delay unit 16-6, completes complex multiplication and outputs;

[0064] The complex multiplier 15-3 receives the complex signal composed of the output signals of the fixed step coefficient adjustment unit 14-3 and the fixed step coefficient adjustment unit 14-7, and at the same time receives the complex signal composed of the output signals of the variable delay unit 16-3 and the variable delay unit 16-7, completes complex multiplication and outputs;

[0065] The complex multiplier 15-4 receives the complex signal composed of the output signals of the fixed step coefficient adjustment unit 14-4 and the fixed step coefficient adjustment unit 14-8, and at the same time receives the complex signal composed of the output signals of the variable delay unit 16-4 and the variable delay unit 16-8, completes complex multiplication and outputs;

[0066] The multi-channel adder 18-1 respectively receives the Q-channel signals output by the complex multipliers 15-1 to 15-4, and at the same time receives the Q-channel signals output by the fixed delay unit 17, completes multi-channel addition operation and outputs to the carrier synchronization module 6;

[0067] The multi-channel adder 18-2 respectively receives the I-channel signals output by the complex multipliers 15-1 to 15-4, and at the same time receives the I-channel signals output by the fixed delay unit 17, completes multi-channel addition operation and outputs to the carrier synchronization module 6;

[0068] The fixed delay unit 17 receives the I / Q two-channel baseband signals output by the matched filter 4, and after fixed delay processing, transmits them to the multi-channel adder 18-2 and the multi-channel adder 18-1 respectively.

[0069] Figure 3 It is the principle block diagram of the adaptive inter-symbol interference cancellation equalization module. The embodiment is according to Figure 3 the connection circuit. The adaptive inter-symbol interference cancellation equalization module 8 includes a digital AGC 19, a branch delay module 20, a parallel convolution operation module 21, a convolution coefficient generation module 22, a data extraction module 23, and an error extraction module 24.

[0070] Among them, the digital AGC 19 performs signal power detection and power adjustment on the input I / Q two-way digital baseband signals, transmits the power-adjusted I / Q two-way digital baseband signals to the branch delay module 20, and simultaneously transmits the data power signal to the adaptive multipath cancellation equalization module 5;

[0071] The branch delay module 20 performs branch and independent delay processing on the received I / Q two-way digital baseband signals to generate two groups of I / Q two-way digital baseband signals, and the first group of I / Q two-way digital baseband signals is transmitted to the parallel convolution operation module 21;

[0072] The parallel convolution operation module 21 receives the I / Q two-way convolution coefficients transmitted by the convolution coefficient generation module 22, performs convolution operations on the input I / Q two-way digital baseband signals, generates the processed I / Q two-way digital baseband signals and transmits them to the data extraction module 23;

[0073] The data extraction module 23 respectively extracts the peak points of the input I / Q two-way digital baseband signals and outputs them; the I / Q two-way digital baseband signals output by the data extraction module 23 are branched to generate two groups of I / Q two-way digital baseband signals, and the first group of I / Q two-way digital baseband signals is used as the output of this device, and this output signal is the equalized I / Q two-way digital baseband signal, and the second group of I / Q two-way digital baseband signals is transmitted to the error extraction module 24;

[0074] The error extraction module 24 processes the input I / Q two-way digital baseband signals, generates two groups of I / Q two-way equalization error signals and outputs them, and the first group of I / Q two-way equalization error signals is transmitted to the convolution coefficient generation module 22;

[0075] The convolution coefficient generation module 22 receives the second group of I / Q two-way digital baseband signals output by the branch delay module 20 and the first group of I / Q two-way equalization error signals output by the error extraction module 24, operates to generate I / Q two-way convolution coefficient signals and outputs them; the I / Q two-way convolution coefficient signals output by the convolution coefficient generation module 22 are transmitted to the parallel convolution operation module 21;

[0076] The second group of I / Q two-way equalization error signals generated by the error extraction module 24 is transmitted to the adaptive multipath cancellation equalization module 5.

[0077] The brief working principle of this device is as follows:

[0078] When a multi - stage all - digital adaptive equalization device applicable to echo high - speed data transmission signals is working, first, ADC1 samples and digitizes the input analog intermediate - frequency signal, and transmits the digital intermediate - frequency signal to the digital down - conversion module 2. The digital down - conversion module 2 performs quadrature down - conversion processing on the digital intermediate - frequency signal to generate I / Q two - path digital baseband signals and transmits them to the digital resampling module 3. The digital resampling module 3 resamples the I / Q two - path digital baseband signals at an integer - multiple symbol rate. The resampled I / Q two - path digital baseband signals are transmitted to the matched - filtering module 4. The matched - filtering module 4 performs matched - filtering processing on the resampled I / Q two - path digital baseband signals to generate I / Q two - path matched - filtered digital baseband signals and transmits them to the adaptive multi - path cancellation equalization module 5. The adaptive multi - path cancellation equalization module 5 performs adaptive equalization processing on the I / Q two - path matched - filtered digital baseband signals to cancel multi - path signals, generates I / Q two - path equalized digital baseband signals and transmits them to the carrier synchronization module 6. The carrier synchronization module 6 generates a local carrier signal, completes carrier synchronization and carrier demodulation, generates I / Q two - path digital baseband signals and transmits them to the timing synchronization module 7. The timing synchronization module completes symbol timing synchronization, generates I / Q two - path digitally - baseband signals after timing synchronization and transmits them to the adaptive inter - symbol interference cancellation equalization module 8. The adaptive inter - symbol interference cancellation equalization module 8 performs adaptive equalization processing on the I / Q two - path digitally - baseband signals after timing synchronization to cancel inter - symbol interference, generates equalized I / Q two - path baseband signals, which are used as the output of this device. At the same time, the adaptive inter - symbol interference cancellation equalization module 8 transmits the I / Q two - path equalization error signals and data power signals to the adaptive multi - path cancellation equalization module 5 to assist the adaptive multi - path cancellation equalization module 5 to complete the equalization processing. Through the above processing, the adaptive equalization processing of the input signal is completed.

[0079] Compared with the traditional adaptive equalization device, the present invention does not need to transmit pilots and adopts an all - digital implementation scheme. The equalization process is reasonably decomposed into a two - stage equalization process, which improves the flexibility and stability of the equalization device. In the present invention, the second - stage equalization feedback signal is used to complete the first - stage adaptive equalization before carrier synchronization and timing synchronization, decoupling the equalization process from carrier synchronization and timing synchronization. The first - stage adaptive equalization can effectively cancel multi - path signals, greatly improving the working thresholds of carrier synchronization and timing synchronization in a multi - path channel, thereby improving the adaptability and receiving sensitivity of the device. The present invention completes the second - stage adaptive equalization after carrier synchronization and timing synchronization, which can effectively cancel the influence of inter - symbol interference on the demodulation performance, thereby improving the demodulation performance of the device. In addition, since the hardware logic resources required for the implementation of this device are small, the implementation complexity is low, and it is easy to implement and promote.

Claims

1. A multi-level fully digital adaptive equalization device suitable for echo high-speed digital transmission signals, characterized in that: It comprises an analog-to-digital converter (1), a digital down-conversion module (2), a digital resampling module (3), a matched filtering module (4), an adaptive multipath offset equalization module (5), a carrier synchronization module (6), a timing synchronization module (7) and an adaptive inter-symbol crosstalk offset equalization module (8); The analog-to-digital converter (1) samples and digitizes the input analog intermediate frequency signal, and transmits the digital intermediate frequency signal to the digital down-conversion module (2); The digital down-conversion module (2) performs orthogonal down-conversion processing on the digital intermediate frequency signal to generate I / Q two-channel digital baseband signals, which are transmitted to the digital resampling module (3); The digital resampling module (3) resamples the I / Q two-way digital baseband signals at an integer multiple symbol rate, and transmits the resampled I / Q two-way digital baseband signals to the matched filtering module (4); The matched filtering module (4) performs matched filtering on the resampled I / Q two-way digital baseband signals to generate I / Q two-way matched filtered digital baseband signals, which are transmitted to the adaptive multipath offset equalization module (5); The adaptive multipath cancellation equalization module (5) performs adaptive equalization processing on the digital baseband signals after the I / Q two-way matched filtering, cancels the multipath signals, generates the digital baseband signals after the I / Q two-way equalization, and transmits them to the carrier synchronization module (6); The carrier synchronization module (6) generates a local carrier signal, completes carrier synchronization and carrier demodulation, generates I / Q two-way digital baseband signals, and transmits them to the timing synchronization module (7); The timing synchronization module (7) completes symbol timing synchronization, generates I / Q two-way timing synchronized digital baseband signals, and transmits them to the adaptive inter-symbol crosstalk cancellation equalization module (8); The adaptive inter-symbol crosstalk cancellation equalization module (8) performs adaptive equalization processing on the I / Q two-way digital baseband signals that have been synchronized with each other, cancels the inter-symbol crosstalk, and generates the I / Q two-way baseband signals after equalization as the output of the device; in addition, the adaptive inter-symbol crosstalk cancellation equalization module (8) transmits the I / Q two-way equalization error signals and the data power signal to the adaptive multipath cancellation equalization module (5), and assists the adaptive multipath cancellation equalization module (5) to complete the equalization processing.

2. A multi-level fully digital adaptive equalization device suitable for echo high-speed digital transmission signals according to claim 1, characterized in that: The adaptive multipath cancellation equalization module (5) comprises a first square operation module (9-1) and a second square operation module (9-2), an addition module (10), a division module (11), an accumulation module (12), a fixed step coefficient and delay adjustment state machine (13), a first fixed step coefficient adjustment unit (14-1) to an eighth fixed step coefficient adjustment unit (14-8), a first complex multiplier (15-1) to a fourth complex multiplier (15-4), a first variable delay unit (16-1) to an eighth variable delay unit (16-8), a fixed delayer (17), a first multi-way adder (18-1), and a second multi-way adder (18-2); The first square operation module (9-1) and the second square operation module (9-2) respectively receive the I / Q two-way equalization error signals output by the adaptive inter-symbol crosstalk cancellation equalization module (8), respectively perform square operations on the input signals, and transmit them to the addition module (10); The adding module (10) performs addition operation on the two received signals and outputs the result; The division module (11) receives the signal output by the addition module (10), and simultaneously receives the data power signal output by the adaptive inter-symbol interference cancellation equalization module (8), completes the division operation, and outputs the operation result; The accumulation module (12) receives the signal output by the division module (11), performs accumulation processing on the received signal, and transmits the processed signal to the fixed step coefficient and delay adjustment state machine (13); The fixed step coefficient and delay adjustment state machine (13) controls the first variable delay unit (16-1) to the eighth variable delay unit (16-8) and the first fixed step coefficient adjustment unit (14-1) to the eighth fixed step coefficient adjustment unit (14-8) respectively through the state adjustment signals S1 to S16, and periodically traverses all delay and coefficient adjustable values; during the periodic traversal process, the accumulated signals output by the accumulation module (12) are recorded in sequence; after the periodic traversal is completed, the fixed step coefficient and delay adjustment state machine (13) selects the optimal control amount according to the accumulated signal values ​​recorded in sequence, and finally completes the control and adjustment of the first variable delay unit (16-1) to the eighth variable delay unit (16-8) and the first fixed step coefficient adjustment unit (14-1) to the eighth fixed step coefficient adjustment unit (14-8) through the state adjustment signal; The first fixed step coefficient adjustment unit (14-1) to the eighth fixed step coefficient adjustment unit (14-8) receive the state adjustment signal output by the fixed step coefficient and delay adjustment state machine (13) to adjust the output signal value thereof with a fixed step; The first variable delay unit (16-1) to the eighth variable delay unit (16-8) receive the fixed step coefficient and the state adjustment signal output by the delay adjustment state machine (13), adjust the delay of the input signal with a fixed step, and output the delayed signal; wherein the first variable delay unit (16-1) and the fifth variable delay unit (16-5) respectively receive the I / Q two-way digital baseband signal output by the matched filter module (4), respectively delay the received signal and output it; the second variable delay unit (16-2) and the sixth variable delay unit (16-6) respectively receive the first variable delay unit (16-1) ) and the fifth variable delay unit (16-5), respectively delay processing the received signals and output them; the third variable delay unit (16-3) and the seventh variable delay unit (16-7) respectively receive the signals output by the second variable delay unit (16-2) and the sixth variable delay unit (16-6), respectively delay processing the received signals and output them; the fourth variable delay unit (16-4) and the eighth variable delay unit (16-8) respectively receive the signals output by the third variable delay unit (16-3) and the seventh variable delay unit (16-7), respectively delay processing the received signals and output them; The first complex multiplier (15-1) receives a complex signal composed of output signals of the first fixed step coefficient adjustment unit (14-1) and the fifth fixed step coefficient adjustment unit (14-5), and simultaneously receives a complex signal composed of output signals of the first variable delay unit (16-1) and the fifth variable delay unit (16-5), completes complex multiplication and outputs the complex signal; The second complex multiplier (15-2) receives a complex signal composed of output signals of the second fixed step coefficient adjustment unit (14-2) and the sixth fixed step coefficient adjustment unit (14-6), and simultaneously receives a complex signal composed of output signals of the second variable delay unit (16-2) and the sixth variable delay unit (16-6), completes complex multiplication and outputs the complex signal; The third complex multiplier (15-3) receives a complex signal composed of output signals of the third fixed step coefficient adjustment unit (14-3) and the seventh fixed step coefficient adjustment unit (14-7), and simultaneously receives a complex signal composed of output signals of the third variable delay unit (16-3) and the seventh variable delay unit (16-7), completes complex multiplication and outputs the complex signal; The fourth complex multiplier (15-4) receives a complex signal composed of output signals of the fourth fixed step coefficient adjustment unit (14-4) and the eighth fixed step coefficient adjustment unit (14-8), and simultaneously receives a complex signal composed of output signals of the fourth variable delay unit (16-4) and the eighth variable delay unit (16-8), completes complex multiplication and outputs the complex signal; The first multi-channel adder (18-1) receives the Q-channel signals output by the first complex multiplier (15-1) to the fourth complex multiplier (15-4) respectively, and simultaneously receives the Q-channel signal output by the fixed delay device (17), completes the multi-channel addition operation and outputs it to the carrier synchronization module (6); The second multi-channel adder (18-2) receives the I-channel signals outputted by the first complex multiplier (15-1) to the fourth complex multiplier (15-4) respectively, and receives the I-channel signal outputted by the fixed delayer (17) at the same time, completes the multi-channel addition operation and outputs it to the carrier synchronization module (6); The fixed delay device (17) receives the I / Q two-way baseband signals output by the matching filter (4), and transmits them to the first multi-way adder (18-1) and the second multi-way adder (18-2) respectively after fixed delay processing.

3. A multi-level fully digital adaptive equalization device suitable for echo high-speed digital transmission signals according to claim 1, characterized in that: The adaptive inter-symbol crosstalk cancellation equalization module (8) comprises a digital AGC (19), a branch delay module (20), a parallel convolution operation module (21), a convolution coefficient generation module (22), a data extraction module (23), and an error extraction module (24); The digital AGC (19) performs signal power detection and power adjustment on the input I / Q two-channel digital baseband signals, transmits the power-adjusted I / Q two-channel digital baseband signals to the branch delay module (20), and transmits the data power signal to the adaptive multipath cancellation equalization module (5); The branching delay module (20) generates two groups of I / Q two-way digital baseband signals after branching and independently delaying the received I / Q two-way digital baseband signals, wherein the first group of I / Q two-way digital baseband signals is transmitted to the parallel convolution operation module (21), and the second group of I / Q two-way digital baseband signals is transmitted to the convolution coefficient generation module (22); The parallel convolution operation module (21) receives the I / Q two-way convolution coefficients transmitted by the convolution coefficient generation module (22), and performs convolution operation on the input I / Q two-way digital baseband signals to generate the I / Q two-way digital baseband signals after operation processing, and transmits them to the data extraction module (23); The data extraction module (23) extracts peak points of the input I / Q two-way digital baseband signals and outputs them respectively. The I / Q two-way digital baseband signals output by the data extraction module (23) are further divided to generate two groups of I / Q two-way digital baseband signals, wherein the first group of I / Q two-way digital baseband signals is used as the output signal of the device, and the output signal is the I / Q two-way digital baseband signal after equalization. The second group of I / Q two-way digital baseband signals is transmitted to the error extraction module (24); The error extraction module (24) processes the input I / Q two-way digital baseband signal to generate and output two groups of I / Q two-way equalization error signals, wherein the first group of I / Q two-way equalization error signals is transmitted to the convolution coefficient generation module (22), and the second group of I / Q two-way equalization error signals is transmitted to the adaptive multipath cancellation equalization module (5); The convolution coefficient generation module (22) receives the second group of I / Q two-path digital baseband signals output by the branch delay module (20) and the first group of I / Q two-path equalization error signals output by the error extraction module (24), generates I / Q two-path convolution coefficient signals by calculation, and outputs them to the parallel convolution operation module (21).

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