Chip parameter optimization method, device, medium and product

Abstract

The present application discloses a chip parameter optimization method, device, medium, and product, which relate to the field of logic circuit design verification technology, including: inputting register parameters into a prototype verification environment of a target chip module and executing a preset verification task; calculating a parameter fitness value based on the task execution time, and using a chip parameter group corresponding to a target parameter fitness value that meets a preset fitness threshold condition as a target chip parameter group; adjusting a parameter crossover probability and a parameter mutation probability based on the parameter fitness value of the target chip parameter group; performing register parameter crossover and register parameter mutation on register parameters in the target chip parameter group based on the adjusted parameter crossover probability and parameter mutation probability, outputting new register parameters, and jumping to the step of inputting the register parameters into the prototype verification environment of the target chip module until the register parameters meet the parameter adjustment condition, and outputting a target chip parameter group composed of the current register parameters. Chip parameter optimization is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of logic circuit design verification, and in particular to a chip parameter optimization method, device, medium and product. Background Art

[0002] In recent years, with the rapid advancement of large-scale integrated circuit (IC) development and manufacturing technology, the various indicators of chip analog modules have become increasingly critical factors in measuring the performance of certain specialized chips. High integration and complex functionality are also design hallmarks of these chips, designed to meet the needs of diverse industries. Therefore, while confirming the logical functionality of the functional modules, performance screening and verification of chip modules is a critical step after the chip is tape-out. Factors such as processing and packaging can cause individual deviations, necessitating the reservation of chip configuration parameters that can be adjusted to ensure optimal performance in different environments. Time is cost, and effectively finding appropriate parameters and a stable operating environment for the chip in a short period of time places high demands on the design of test vectors.

[0003] In the current chip analog module verification process, conventional test vectors are tested using standard design values. This makes it difficult to achieve good coverage and accurate diagnostic capabilities across the full threshold range for high-precision and complex circuits. Testing using non-self-learning algorithm libraries is time-consuming, and most test items suffer from misjudgment of erroneous symptoms and confusion of symptoms. Furthermore, test scripts and instrument program-controlled stimulus are generally not integrated into the entire verification system, requiring manual configuration for most verification tasks. This wastes significant labor costs and debugging time, increases the risk of errors during manual debugging operations, and thus affects test quality and results. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip parameter optimization method, device, medium and product that can automatically accelerate the chip parameter optimization process. The specific solution is as follows:

[0005] In a first aspect, the present application discloses a chip parameter optimization method, comprising:

[0006] Input register parameters into the prototype verification environment of the target chip module, execute the preset verification task, and record the task execution time; wherein the register parameters are register values corresponding to several chip parameter groups;

[0007] Calculating the corresponding parameter fitness value according to the task execution time, and screening the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group;

[0008] Adjust the parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group;

[0009] According to the adjusted parameter cross probability and the adjusted parameter mutation probability, register parameter crossover and register parameter mutation are performed on the register parameters in the target chip parameter group respectively to output new register parameters, and the step of inputting the register parameters into the prototype verification environment of the target chip module is jumped to be executed until the new register parameters meet the parameter adjustment conditions, and the target chip parameter group composed of the current register parameters is output to the chip configuration interface.

[0010] Optionally, the chip parameter optimization method further includes:

[0011] Based on the physical configuration constraints of the target chip module, several groups of register parameter combinations are randomly generated within the feasible domain of register values;

[0012] A plurality of chip parameter groups are respectively formed based on the register parameters in each register parameter combination.

[0013] Optionally, before randomly generating a plurality of register parameter combinations within a feasible domain of register values based on the physical configuration constraints of the target chip module, the method further includes:

[0014] Obtain the physical configuration constraints of each register in the target chip module;

[0015] The physical configuration constraints include the value range constraints of each register and the value association constraints between registers.

[0016] Optionally, based on the physical configuration constraints of the target chip module, several groups of register parameter combinations are randomly generated within the feasible domain of register values, including:

[0017] Generate several groups of initial register parameter combinations within the feasible domain of register values based on the Monte Carlo random sampling method;

[0018] Physical configuration constraint verification is performed on each initial register parameter combination to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

[0019] Optionally, performing register parameter mutation on register parameters in the target chip parameter group according to the adjusted parameter mutation probability to output new register parameters includes:

[0020] Determine the register parameters to be mutated in the target chip parameter group according to the adjusted parameter mutation probability;

[0021] The parameters of the registers to be mutated are mutated to obtain new register parameters that meet the physical configuration constraints and are in the feasible domain.

[0022] Optionally, adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group includes:

[0023] If the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is dynamically reduced according to the crossover probability calculation equation to obtain the adjusted parameter crossover probability; the parameter mutation probability of the current target chip parameter group is dynamically reduced according to the mutation probability calculation equation to obtain the adjusted parameter mutation probability;

[0024] If the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is adjusted to a preset maximum parameter crossover probability, and the parameter mutation probability of the current target chip parameter group is adjusted to a preset maximum parameter mutation probability;

[0025] The average parameter fitness value is the average of the parameter fitness values of all target chip parameter groups.

[0026] Optionally, the crossover probability calculation equation is:

[0027] ;

[0028] in, Indicates the maximum value of the preset parameter crossover probability, Indicates the maximum parameter adaptation value among all target chip parameter groups, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group with the larger fitness value in the parameter crossover, and the value range is , Indicates the minimum value of the preset parameter crossover probability.

[0029] Optionally, the mutation probability calculation equation is:

[0030] ;

[0031] in, Indicates the maximum probability of mutation of preset parameters, Indicates the maximum parameter adaptation value among all target chip parameter groups, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group participating in parameter variation.

[0032] Optionally, performing register parameter crossover on register parameters in the target chip parameter group according to the adjusted parameter crossover probability to output new register parameters includes:

[0033] The target chip parameter groups are divided into groups according to parameter fitness values to obtain a first target chip parameter group and a second target chip parameter group; wherein the first target chip parameter group is a target chip parameter group whose fitness value ranking satisfies a preset fitness ranking condition, and the second target chip parameter group is a target chip parameter group other than the first target chip parameter group;

[0034] Using a multi-point crossover method and based on the adjusted parameter crossover probability, a portion of the register parameters in the first target chip parameter group is exchanged to output new register parameters;

[0035] The target register parameter position in the register parameters of the second target chip parameter group is determined based on the adjusted parameter crossover probability, and all register parameters located after the target register parameter position are exchanged using a single-point crossover method to output new register parameters.

[0036] Optionally, after outputting the new register parameters, also include:

[0037] Perform constraint verification of physical configuration constraints on the new register parameters after the exchange process;

[0038] If the constraint verification is passed, the execution jumps to the step of inputting the register parameters into the prototype verification environment of the target chip module;

[0039] If the constraint verification fails, the process jumps to the step of performing register parameter crossover on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability.

[0040] Optionally, outputting a target chip parameter group consisting of current register parameters to the chip configuration interface includes:

[0041] Convert the target chip parameter group composed of the current register parameters into a binary configuration code stream;

[0042] Write the configuration code stream into the physical register of the target chip through the preset communication interface;

[0043] Verify whether the actual performance indicators of the target chip are consistent with the simulation results;

[0044] If they are inconsistent, the chip parameter optimization process is re-triggered.

[0045] Optionally, the prototype verification environment is an FPGA-based hardware simulation platform; wherein the hardware simulation platform includes a parameter loading unit for configuring register parameters to FPGA logic units through a hardware description language to simulate the physical behavior of a target chip module, a real-time monitoring unit for collecting signal indicators of the target chip module when performing a preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task based on real-time monitoring data when performing the preset verification task to approximate the actual prototype verification environment;

[0046] Among them, signal indicators include clock jitter indicators, signal delay indicators and dynamic power consumption indicators.

[0047] In a second aspect, the present application discloses an electronic device, comprising:

[0048] Memory, used to store computer programs;

[0049] The processor is used to execute the computer program to implement the steps of the chip parameter optimization method disclosed above.

[0050] In a third aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the chip parameter optimization method disclosed above are implemented.

[0051] In a fourth aspect, the present application discloses a computer program product, including a computer program / instruction, which implements the steps of the aforementioned chip parameter optimization method when executed by a processor.

[0052] It can be seen that the present application discloses a chip parameter optimization method, including: inputting register parameters into the prototype verification environment of the target chip module, executing a preset verification task, and recording the task execution time; wherein the register parameters are register values corresponding to several chip parameter groups; calculating the corresponding parameter fitness value according to the task execution time, and screening the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness value of each target chip parameter group; performing register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability to output new register parameters, and jumping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and outputting the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0053] This demonstrates that dynamically adjusting crossover and mutation probabilities based on fitness distribution allows for rapid early exit from local optima and precise convergence in later stages, significantly accelerating convergence compared to traditional genetic algorithms. This automated closed-loop process of parameter generation, verification testing, fitness evaluation, and crossover mutation replaces traditional manual debugging, avoiding repeated testing and parameter omissions caused by inexperience. This overall process reduces manual debugging during chip parameter configuration, lowering labor costs and debugging time while increasing chip module parameter optimization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0055] Figure 1 This is a flow chart of a chip parameter optimization method disclosed in this application;

[0056] Figure 2 A schematic diagram of a constraint condition of a physical configuration constraint disclosed in this application;

[0057] Figure 3 A schematic diagram of parameter crossover disclosed in this application;

[0058] Figure 4 This is a flow chart of a specific chip parameter optimization method disclosed in this application;

[0059] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0061] In recent years, with the rapid advancement of large-scale integrated circuit (IC) development and manufacturing technology, the various indicators of chip analog modules have become increasingly critical factors in measuring the performance of certain specialized chips. High integration and complex functionality are also design hallmarks of these chips, designed to meet the needs of diverse industries. Therefore, while confirming the logical functionality of the functional modules, performance screening and verification of chip modules is a critical step after the chip is tape-out. Factors such as processing and packaging can cause individual deviations, necessitating the reservation of chip configuration parameters that can be adjusted to ensure optimal performance in different environments. Time is cost, and effectively finding appropriate parameters and a stable operating environment for the chip in a short period of time places high demands on the design of test vectors.

[0062] In the current chip analog module verification process, conventional test vectors are tested using standard design values. This makes it difficult to achieve good coverage and accurate diagnostic capabilities across the full threshold range for high-precision and complex circuits. Testing using non-self-learning algorithm libraries is time-consuming, and most test items suffer from misjudgment of erroneous symptoms and confusion of symptoms. Furthermore, test scripts and instrument program-controlled stimulus are generally not integrated into the entire verification system, requiring manual configuration for most verification tasks. This wastes significant labor costs and debugging time, increases the risk of errors during manual debugging operations, and thus affects test quality and results.

[0063] To this end, the present invention provides a chip parameter optimization solution that can automatically accelerate the chip parameter optimization process.

[0064] Reference Figure 1 As shown, an embodiment of the present invention discloses a chip parameter optimization method, comprising:

[0065] Step S11: inputting register parameters into the prototype verification environment of the target chip module, executing a preset verification task, and recording the task execution time; wherein the register parameters are register values corresponding to several chip parameter groups.

[0066] In this embodiment, the physical configuration constraints of each register in the target chip module are obtained; wherein, the physical configuration constraints include the value range constraints of each register and the value association constraints between registers. It is understandable that since the valid values of registers are within a certain range, if they exceed this range, there is no point in verification. Therefore, the value range of each register needs to be used as one of the constraints, such as Figure 2 As shown in the figure, the value range of register A is 2 to 6. Therefore, the value of register A in the algorithm cannot be less than 2 or greater than 6. There are also certain constraints between registers. For example, the value of register A must be less than the value of register B. Based on the above physical configuration constraints, several chip parameter groups are further generated within the feasible domain of register values, as follows:

[0067] Based on the physical configuration constraints of the target chip module, several groups of register parameter combinations are randomly generated within the feasible domain of register values. Several chip parameter groups are formed based on the register parameters in each register parameter combination. Specifically, several groups of initial register parameter combinations are generated within the feasible domain of register values based on the Monte Carlo random sampling method. Physical configuration constraint verification is performed on each initial register parameter combination to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

[0068] It can be understood that within the feasible region, several solutions are randomly generated based on the physical configuration constraints, which are called the initial population. Within the initial population, several groups of initial register parameter combinations are generated using the Monte Carlo random sampling method. The physical configuration constraints are then verified for each initial register parameter combination to obtain several groups of register parameter combinations that all meet the physical configuration constraints.

[0069] For example, a function in an IP module requires configuration of three registers: registers A, B, and C, with values ranging from A1 to A5, B1 to B4, and C1 to C7, respectively. Monte Carlo random sampling is used to randomly select registers A1 to A5 as the value of register A2, register B1 to B4 as the value of register B3, and register C1 to C7 as the value of register C4, satisfying the constraint that the value of register A is less than the value of register B. Each register is called a gene, and the combination of registers (chip parameter set) is called a chromosome. A chromosome is a solution. In this embodiment, a chromosome is an individual, such as [A2, B3, C4], which is a solution. The number of chromosomes used for population initialization should be selected based on actual conditions. The population size should be neither too large nor too small. If it is too small, genetic optimization performance will generally be poor. If it is too large, it will easily fall into a local optimum.

[0070] In this embodiment, the register parameters within the aforementioned chip parameter groups are input into the prototype verification environment of the target chip module, a preset verification task is executed, and the task execution time is recorded. This means that each solution in the population is evaluated for fitness by running the solution as chip input parameters on the prototype verification environment to obtain performance output parameters. This evaluates the adaptability of each individual to the environment. For example, if a function in an IP module requires the configuration of three registers, namely register A, register B, and register C, individuals 1 [A2, B3, C4], 2 [A3, B4, C5], and 3 [A3, B3, C4] are randomly selected. The times required to run the same task on the prototype verification environment using individuals 1, 2, and 3 as chip inputs are t1, t2, and t3, respectively, representing the task execution time.

[0071] In addition, the prototype verification environment is an FPGA-based hardware simulation platform; wherein, the hardware simulation platform includes a parameter loading unit for configuring register parameters to the FPGA logic unit through a hardware description language to simulate the physical behavior of the target chip module, a real-time monitoring unit for collecting signal indicators of the target chip module when performing a preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task according to the real-time monitoring data when performing the preset verification task to approach the actual prototype verification environment; wherein, the signal indicators include clock jitter indicators, signal delay indicators and dynamic power consumption indicators. It can be understood that the prototype verification environment is a hardware simulation platform based on FPGA (Field-Programmable Gate Array). The preset verification tasks include workload testing, extreme frequency testing, and power consumption testing. Among them, the workload test is to run the daily business scenarios of the chip module (such as video encoding, AI (Artificial Intelligence) reasoning); the extreme frequency test is to perform stress tasks at the highest operating frequency of the chip; the power consumption test is to record the average power consumption during the task execution; the task execution time is the weighted average of the three test times (weights are 0.5, 0.3, and 0.2 respectively) to comprehensively evaluate the performance, robustness and energy efficiency of the parameter group.

[0072] Step S12: Calculate the corresponding parameter fitness value according to the task execution time, and select the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group.

[0073] In this embodiment, the fitness function is f(t)=1 / t, where t is the time it takes for an individual to perform the same task as a chip input parameter in a prototype verification environment, that is, the task execution time. The better the individual fitness, the larger the parameter fitness value f(t), and the worse the individual fitness, the smaller the parameter fitness value f(t). According to the sorting of parameter fitness values, unsuitable individuals are eliminated and suitable ones are retained. The selection operation selects a part of excellent individuals by evaluating and sorting the fitness of individuals, giving them a greater chance to participate in the reproduction process. In this way, the genetic information of excellent individuals can be inherited and developed in future generations, thereby improving the fitness of the entire population. However, too large a selection probability may lead to the occurrence of premature maturity. The preset fitness threshold condition is a selection probability range of 0.2 <p s <0.5, in this embodiment, the selected probability p s is 0.4. The number of retained individuals Res = selection probability p sInitialize the chromosomes, i.e., the target chip parameter set. Furthermore, calculate the fitness of the individual chromosomes, sort them by fitness value, and retain a few chromosomes with the lowest fitness, thus obtaining the target chip parameter set. The remaining chromosomes are eliminated.

[0074] Step S13: adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group.

[0075] In this embodiment, the parameter crossover probability and parameter mutation probability are adjusted based on the fitness distribution of the parameter fitness values of each target chip parameter group, including: if the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is dynamically reduced according to the crossover probability calculation equation to obtain an adjusted parameter crossover probability; the parameter mutation probability of the current target chip parameter group is dynamically reduced according to the mutation probability calculation equation to obtain an adjusted parameter mutation probability; if the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is adjusted to a preset maximum parameter crossover probability, and the parameter mutation probability of the current target chip parameter group is adjusted to a preset maximum parameter mutation probability; wherein the average parameter fitness value is the average of the parameter fitness values of all target chip parameter groups. It can be understood that in the adaptive crossover and mutation operators in the prior art, when the fitness approaches the maximum fitness, the crossover and mutation probabilities become very small, and when the fitness is equal to the maximum fitness, the crossover and mutation probabilities become zero. When using the existing adaptive genetic algorithm, the chip module parameters are not ideal in the early stage. The better individuals in the early stage of the algorithm hardly change. At this time, the better individuals are not necessarily the global optimal solution, which increases the possibility of the algorithm obtaining a local optimal solution. To this end, the present invention uses an improved adaptive genetic operator, wherein, when If it is greater than or equal to the average parameter fitness value, the crossover probability calculation equation is:

[0076] ;

[0077] when If it is less than the average parameter fitness value, the crossover probability of the adjusted parameters is:

[0078] ;

[0079] in, represents the crossover probability of the adjusted parameters, , They represent the maximum value of the crossover probability of the preset parameters and the minimum value of the crossover probability of the preset parameters, respectively. Indicates the maximum parameter adaptation value in the target chip parameter group, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group with the larger fitness value in the parameter crossover, and the value range is The crossover probability parameter is generally set at 0.4 to 0.99. The crossover probability selected in the present invention is is 0.7, is 0.4. That is, each gene in two individuals has a crossover probability of Crossover is performed, randomly selecting all gene sequences following a gene and exchanging them. By improving the adaptive genetic operator, the crossover and mutation probability is increased in the early stages of the algorithm, accelerating convergence. Later, as the algorithm gradually approaches the optimal solution, the crossover and mutation probability is reduced to protect the already obtained excellent genotypes. The optimal solution is obtained through a narrow search. The improved adaptive genetic operator more precisely controls the crossover and mutation probabilities during the crossover and mutation processes than the adaptive genetic operator, resulting in faster convergence.

[0080] like Figure 3 As shown, through the improved parameter crossover algorithm adjustment scheme of the present invention, gene 3, gene 4, and gene 5 can be cross-processed with gene 3', gene 4', and gene 5' respectively, instead of only crossing gene 3 with gene 3'.

[0081] In this embodiment, during the evolution process, the genes in the chromosomes are randomly changed to generate new individuals. The mutation process plays an important role in the evolutionary algorithm, which can increase the search space and avoid falling into the local optimal solution. Generally speaking, a lower mutation probability can maintain the stability of the population, while a higher mutation probability can increase the exploration space. The present invention adopts the improved adaptive genetic operator. Greater than or equal to the average parameter fitness value, the mutation probability calculation equation is:

[0082] ;

[0083] when If the value is less than the average parameter fitness value, the probability of parameter mutation after adjustment is:

[0084] ;

[0085] in, represents the probability of parameter variation after adjustment, 、 They represent the maximum and minimum probability of mutation of the preset parameters, respectively. Indicates the maximum parameter adaptation value among all target chip parameter groups, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group involved in parameter variation, wherein and The values of are the same, and different symbols are used to distinguish parameter crossover from parameter variation.

[0086] when When , the function is a monotonically decreasing function, and its value range is The original mutation probability should not be too large or too small. Generally, the value is 0.0001 to 0.2. The original mutation probability selected by the present invention is is 0.1, is 0.0001, that is, the probability of a certain value of a gene in an individual is mutated The gene mutation range must also be within the register value range, and must satisfy the constraint that the value of register A is less than the value of register B.

[0087] Step S14: Perform register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability to output new register parameters, and jump to the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and output the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0088] In this embodiment, the register parameters to be mutated of the register parameters in the target chip parameter group are determined according to the adjusted parameter mutation probability; the register parameters to be mutated are subjected to parameter mutation to obtain new register parameters that meet the physical configuration constraints and are in the feasible domain. It can be understood that, according to the above-mentioned adjusted parameter mutation probability, the register parameters to be mutated of the register parameters in the target chip parameter group are determined, such as Figure 4 As shown in the figure, the IP module has three registers, namely register D, register E, and register F, with value ranges of 2 to 6, 5 to 8, and 11 to 17, respectively. The specific steps of improving the genetic algorithm to verify the coverage prototype are as follows: first, the population is initialized, the population size m is 3, the number of genes in each chromosome G is 3, and the selection probability p is 0. s is 0.4, the crossover probability is 0.7, is 0.4, the mutation probability is 0.1, is 0.0001, the maximum value of the adaptation value 1, the maximum number of iterations The fitness value is 1000 and the fitness value is 0.1 seconds. Initialize the three chromosomes as x1=[2,5,11], x2=[6,8,17], and x3=[4,6,14]. Calculate the fitness value according to the fitness function and sort them according to the fitness value to select the probability p. s Select and retain the best individuals (i.e. chromosomes). Chromosomes x1, x2, x3 are used as input parameters and the time required to perform the same task in the prototype verification environment is t1, t2, t3, and the fitness is sorted according to the time taken. . Each gene in an individual chromosome is Mutation occurs because the population has a larger fitness ,because Less than 1, but the mutated gene must be an integer, so a gene in an individual, that is, a chromosome, is randomly selected for mutation, and the value of register D after mutation must be between 2 and 6, the value of register E must be between 5 and 8, and the value of register F must be between 11 and 17.

[0089] In this embodiment, register parameter crossover is performed on register parameters in a target chip parameter group according to an adjusted parameter crossover probability to output new register parameters, including: dividing the target chip parameter group into groups according to parameter fitness values to obtain a first target chip parameter group and a second target chip parameter group; wherein the first target chip parameter group is a target chip parameter group whose fitness value ranking satisfies a preset fitness ranking condition, and the second target chip parameter group is a target chip parameter group other than the first target chip parameter group; using a multi-point crossover method and based on the adjusted parameter crossover probability, some register parameters in the register parameters in the first target chip parameter group are exchanged to output new register parameters; determining a target register parameter site in the register parameters in the second target chip parameter group based on the adjusted parameter crossover probability, and using a single-point crossover method, exchanging all register parameters located after the target register parameter site to output new register parameters. It can be understood that for the individuals with the top 20% of fitness values, a multi-point crossover method is used to exchange only some gene sites in the chromosome (such as the values of registers D and E) to retain high-performance parameter combinations; for the individuals with the bottom 80% of fitness values, a single-point crossover method is used to exchange all gene sequences after a gene site in the chromosome (such as registers F and subsequent registers) to introduce diversity; for example: for the individuals with the bottom 80% of fitness values, two chromosomes are randomly selected for crossover, and each gene in the individual chromosome is exchanged with probability Crossover is performed, because the fitness of the population is larger ,all Greater than 2, but crossover must be an integer, so two genes are selected for crossover. One gene is randomly selected from each chromosome, and then all genes are exchanged. This ensures that the top 20% of individuals by fitness already possess optimal parameter combinations. Multi-point crossover (exchanging multiple loci) allows for fine-tuning of secondary parameters while retaining core high-quality genes, accelerating the refined search for local optimal solutions. This prevents the loss of high-quality genes and ensures that the algorithm converges quickly to a high-performance parameter combination in the later stages. Single-point crossover is used for the bottom 80% of individuals with low fitness. Individuals with lower fitness also undergo single-point crossover (exchanging only the entire sequence after a specific locus), introducing a wider range of parameter variations, expanding the search space, and exploring potential new solutions. This prevents premature loss of population diversity and prevents the algorithm from becoming trapped in local optimality.

[0090] In this embodiment, after outputting the new register parameters, the following steps are further included: performing constraint verification of the physical configuration constraints on the new register parameters after the swap process; if the constraint verification passes, then the execution jumps to the step of inputting the register parameters into the prototype verification environment of the target chip module; if the constraint verification fails, then the execution jumps to the step of performing register parameter crossover on the register parameters in the target chip parameter group based on the adjusted parameter crossover probability. It is understood that the child parameters generated after the crossover must pass the constraint verification of the physical configuration constraints, and if the constraints are violated, the crossover operation is re-executed.

[0091] After obtaining the new register parameters, determine whether the new register parameters reach the ideal performance output parameters, that is, whether the maximum number of generations is reached. Or if the fitness value reaches 10 seconds, the iteration is stopped and the actual coverage rate is output. Otherwise, the process jumps to the step of calculating the fitness value according to the fitness function and sorting according to the fitness value.

[0092] In this embodiment, outputting the target chip parameter group composed of the current register parameters to the chip configuration interface includes: converting the target chip parameter group composed of the current register parameters into a binary configuration code stream; writing the configuration code stream into the physical registers of the target chip via a preset communication interface; verifying whether the actual performance indicators of the target chip are consistent with the simulation results; and re-triggering the chip parameter optimization process if they are inconsistent. It can be understood that since the parameter optimization process of the present invention is intended to be completed before the target chip parameter group is input into the physical registers of the target chip for multiple actual optimization tests, the current target chip parameter group is obtained during the performance screening and verification process of the chip module. Therefore, before complete packaging, the optimal register parameter combination can be converted into a binary configuration code stream; writing the configuration code stream into the physical registers of the target chip via a JTAG (Joint Test Action Group, an international standard test protocol) or I2C (Inter-Integrated Circuit) interface; verifying whether the actual performance indicators of the chip after writing are consistent with the simulation results; and re-triggering the optimization process if they are inconsistent.

[0093] It can be seen that the present application discloses a chip parameter optimization method, including: inputting register parameters into the prototype verification environment of the target chip module, executing a preset verification task, and recording the task execution time; wherein the register parameters are register values corresponding to several chip parameter groups; calculating the corresponding parameter fitness value according to the task execution time, and screening the target parameter fitness value that meets the preset fitness threshold condition, so as to use the chip parameter group corresponding to the target parameter fitness value as the target chip parameter group; adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness value of each target chip parameter group; performing register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability to output new register parameters, and jumping to execute the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and outputting the target chip parameter group composed of the current register parameters to the chip configuration interface.

[0094] This demonstrates that dynamically adjusting crossover and mutation probabilities based on fitness distribution allows for rapid early exit from local optima and precise convergence in later stages, significantly accelerating convergence compared to traditional genetic algorithms. This automated closed-loop process of parameter generation, verification testing, fitness evaluation, and crossover mutation replaces traditional manual debugging, avoiding repeated testing and parameter omissions caused by inexperience. This overall process reduces manual debugging during chip parameter configuration, lowering labor costs and debugging time while increasing chip module parameter optimization efficiency.

[0095] Figure 5This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, the device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the chip parameter optimization method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0096] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0097] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0098] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0099] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to enable the processor 21 to calculate and process the massive amount of data 223 in the memory 22. It can be Windows, Unix, Linux, etc. In addition to including computer programs that can be used to implement the chip parameter optimization method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include computer programs that can be used to perform other specific tasks. In addition to data transmitted by external devices received by the electronic device, the data 223 can also include data collected by its own input and output interface 25.

[0100] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the chip parameter optimization method steps disclosed in any of the aforementioned embodiments are implemented.

[0101] An embodiment of the present invention further discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the chip parameter optimization method disclosed in any of the aforementioned embodiments.

[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0103] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0104] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0105] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0106] The above is a detailed introduction to the solution provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A chip parameter optimization method, characterized in that: include: Inputting register parameters into a prototype verification environment of a target chip module, executing a preset verification task, and recording the task execution time; wherein the register parameters are register values corresponding to a plurality of chip parameter groups; Calculating a corresponding parameter fitness value according to the task execution time, and screening a target parameter fitness value that meets a preset fitness threshold condition, so as to use a chip parameter group corresponding to the target parameter fitness value as a target chip parameter group; Adjusting the parameter crossover probability and the parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group; Performing register parameter crossover and register parameter mutation on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability and the adjusted parameter mutation probability to output new register parameters, and jumping to the step of inputting the register parameters into the prototype verification environment of the target chip module until the new register parameters meet the parameter adjustment conditions, and outputting the target chip parameter group composed of the current register parameters to the chip configuration interface; Performing register parameter crossover on register parameters in the target chip parameter group according to the adjusted parameter crossover probability to output new register parameters, including: The target chip parameter group is divided into groups according to parameter fitness values to obtain a first target chip parameter group and a second target chip parameter group; wherein the first target chip parameter group is a target chip parameter group whose fitness value ranking meets a preset fitness ranking condition, and the second target chip parameter group is a target chip parameter group other than the first target chip parameter group; exchanging some register parameters in the first target chip parameter group using a multi-point crossover method and based on the adjusted parameter crossover probability, so as to output new register parameters; A target register parameter position in the register parameters of the second target chip parameter group is determined based on the adjusted parameter crossover probability, and all register parameters located after the target register parameter position are exchanged using a single-point crossover method to output new register parameters.

2. The chip parameter optimization method according to claim 1, characterized in that: Also includes: Based on the physical configuration constraints of the target chip module, several groups of register parameter combinations are randomly generated within the feasible domain of register values; A plurality of chip parameter groups are respectively formed based on the register parameters in each register parameter combination.

3. The chip parameter optimization method according to claim 2, characterized in that: Before randomly generating a plurality of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module, the method further includes: Obtain the physical configuration constraints of each register in the target chip module; The physical configuration constraints include value range constraints of the registers and value association constraints between the registers.

4. The chip parameter optimization method according to claim 2, characterized in that: The method randomly generates several groups of register parameter combinations within the feasible domain of register values based on the physical configuration constraints of the target chip module, including: Generate several groups of initial register parameter combinations within the feasible domain of register values based on the Monte Carlo random sampling method; Physical configuration constraint verification is performed on each of the initial register parameter combinations to obtain several groups of register parameter combinations that meet the physical configuration constraint verification.

5. The chip parameter optimization method according to claim 2, characterized in that: Performing register parameter mutation on register parameters in the target chip parameter group according to the adjusted parameter mutation probability to output new register parameters includes: Determining register parameters to be mutated of register parameters in the target chip parameter group according to the adjusted parameter mutation probability; The register parameters to be mutated are mutated to obtain new register parameters that meet physical configuration constraints and are within the feasible domain.

6. The chip parameter optimization method according to any one of claims 1 to 5, characterized in that: The adjusting parameter crossover probability and parameter mutation probability based on the fitness distribution of the parameter fitness values of each target chip parameter group includes: If the parameter fitness value of the current target chip parameter group is greater than or equal to the average parameter fitness value, the parameter crossover probability of the current target chip parameter group is dynamically reduced according to the crossover probability calculation equation to obtain an adjusted parameter crossover probability; the parameter mutation probability of the current target chip parameter group is dynamically reduced according to the mutation probability calculation equation to obtain an adjusted parameter mutation probability; If the parameter fitness value of the current target chip parameter group is less than the average parameter fitness value, adjusting the parameter crossover probability of the current target chip parameter group to a preset maximum parameter crossover probability, and adjusting the parameter mutation probability of the current target chip parameter group to a preset maximum parameter mutation probability; The average parameter fitness value is the average of the parameter fitness values of all the target chip parameter groups.

7. The chip parameter optimization method according to claim 6, characterized in that: The crossover probability calculation equation is: ； in, Indicates the maximum value of the preset parameter crossover probability, Indicates the maximum parameter adaptation value among all target chip parameter groups, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group with the larger fitness value in the parameter crossover, and the value range is , Indicates the minimum value of the preset parameter crossover probability.

8. The chip parameter optimization method according to claim 6, characterized in that: The mutation probability calculation equation is: ； in, Indicates the maximum probability of mutation of preset parameters, Indicates the maximum parameter adaptation value among all target chip parameter groups, represents the average parameter fitness value, Indicates the fitness value of the target chip parameter group participating in parameter variation.

9. The chip parameter optimization method according to claim 1, characterized in that: After outputting the new register parameters, the method further includes: Perform constraint verification of physical configuration constraints on the new register parameters after the exchange process; If the constraint verification is passed, the step of inputting the register parameters into the prototype verification environment of the target chip module is jumped to execution; If the constraint verification fails, the process jumps to executing the step of performing register parameter crossover on the register parameters in the target chip parameter group according to the adjusted parameter crossover probability.

10. The chip parameter optimization method according to claim 1, characterized in that: Outputting the target chip parameter group composed of the current register parameters to the chip configuration interface includes: Convert the target chip parameter group composed of the current register parameters into a binary configuration code stream; Writing the configuration code stream into the physical register of the target chip through a preset communication interface; Verify whether the actual performance indicators of the target chip are consistent with the simulation results; If they are inconsistent, the chip parameter optimization process is re-triggered.

11. The chip parameter optimization method according to claim 1, characterized in that: The prototype verification environment is an FPGA-based hardware simulation platform; wherein the hardware simulation platform includes a parameter loading unit for configuring register parameters to FPGA logic units through a hardware description language to simulate the physical behavior of a target chip module, a real-time monitoring unit for collecting signal indicators of the target chip module when performing a preset verification task, and a dynamic feedback module for adjusting the voltage and temperature conditions of the preset verification task based on real-time monitoring data when performing the preset verification task to approximate the actual prototype verification environment; The signal indicators include clock jitter indicator, signal delay indicator and dynamic power consumption indicator.

12. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the chip parameter optimization method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that Used to store a computer program; wherein, when the computer program is executed by a processor, the steps of the chip parameter optimization method according to any one of claims 1 to 11 are implemented.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the chip parameter optimization method according to any one of claims 1 to 11 are implemented.

Images