Method for improving accuracy of manually selected GPP crystal grain appearance

Abstract

The invention relates to the technical field of semiconductor devices, and particularly provides a method for improving the appearance accuracy of artificially selected GPP crystal grains, which comprises the following steps: carrying out photoetching, corrosion, electrophoresis, glass sintering, metallization, probe testing, laser cutting and appearance selection on a diffused silicon wafer, and specifically comprises the following steps: carrying out photoetching, corrosion, electrophoresis, glass sintering, metallization, probe testing, laser cutting and appearance selection on the surface of the silicon wafer subjected to phosphorus diffusion and boron diffusion; and photoetching an identification mark along an edge exclusion area on the outer side of the outermost circle of crystal grains, wherein the edge exclusion area is a blank between the outermost circle of crystal grains and the edge of the silicon wafer. By adopting the method, an employee can accurately and quickly pick out incomplete crystal grains and incomplete crystal grains along the glass, additional detection and ink dispensing operation do not need to be carried out on an edge exclusion area, and the method has a good application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a method for improving the accuracy of visually inspecting GPP die appearance. Background Art

[0002] With the booming development of the semiconductor market, customers' demands for semiconductor chips have become more diverse and require higher reliability. The stability of the chip determines the quality assurance of the product in the market. To ensure the stable quality of the chip, generally, the die located in the outermost circle of the GPP wafer is not used. Therefore, it is necessary to detect and select the die in the outermost circle. There are two traditional methods for visually inspecting the die in the outermost circle of the GPP wafer. The first method is manual selection through a microscope, which is inefficient. The second method is to mark the die without a complete glass edge or an incomplete die with ink dots during the test stage. This method not only affects the test time but also wastes ink, and it is easy to cause misunderstanding on the MAP graph of the probe station. At the same time, such a processing method does not conform to the yield calculation logic of the probe station software, resulting in distorted yield. During subsequent customer audits, additional explanations and separate verifications are required.

[0003] Therefore, how to efficiently screen for good products has become one of the technical problems to be solved urgently at present. Summary of the Invention

[0004] In view of this, the present invention proposes a method for improving the accuracy of visually inspecting GPP die appearance.

[0005] The technical solution of the present invention is implemented as follows: The present invention provides a method for improving the accuracy of visually inspecting GPP die appearance, including: performing photolithography, etching, electrophoresis, glass sintering, metal plating, probe testing, laser cutting, and visual inspection on the diffused wafer. Among them, photolithography is to form an identification mark by photolithography along the edge exclusion area outside the outermost die on the surface of the wafer after phosphorus diffusion and boron diffusion are completed. The edge exclusion area is the blank area between the outermost die and the wafer edge.

[0006] In some embodiments, there are multiple identification marks, and the positions of the identification marks are in the blank area between the outermost die and the wafer edge, that is, in the edge exclusion area. The surface of the die located in the edge exclusion area and having a complete edge after cutting has at least one identification mark.

[0007] The identification mark does not overlap with the alignment mark in space and has a different shape. When an alignment mark is provided, no identification mark is set at the corresponding position.

[0008] The identification mark is spatially isolated from the existing alignment mark, avoiding the need to re-design the photomask, being compatible with the standard semiconductor manufacturing process, and reducing the equipment modification cost.

[0009] In some embodiments, the photolithography method includes: exposing through a reticle provided with identification marks.

[0010] On the reticle, the area where the identification marks are set is in the area corresponding to the edge exclusion zone.

[0011] In some embodiments, the etching method includes etching the photolithographed silicon wafer with a mixed acid. The etching temperature is -5 to -3 °C, the etching time is not less than 600 s, and the etching depth is 125 - 155 μm.

[0012] In some embodiments, the mixed acid is obtained by mixing hydrofluoric acid: nitric acid: glacial acetic acid: sulfuric acid in a volume ratio of (8 - 10):(8 - 10):(10 - 18):(3 - 5).

[0013] In some embodiments, the electrophoresis method includes preparing an electrophoresis solution. After cleaning the etched silicon wafer, it is immersed in the electrophoresis solution, and electrophoresis is carried out at a voltage of 180 - 260 V and an ultrasonic amplitude of 10 - 30 mV to adsorb glass powder into the grain grooves. During electrophoresis, halogen lamp illumination of 100 - 200 V is applied simultaneously, and the current intensity is 1 - 3 A.

[0014] In some embodiments, the glass sintering temperature is 800 - 900 °C, and the glass sintering atmosphere is a mixed gas of nitrogen: oxygen with a volume ratio of (6 - 10):(5 - 10).

[0015] In some embodiments, the shape of the identification mark is circular or cross-shaped, and the size of the widest part of the identification mark is 0.5 - 1.5 mm.

[0016] The identification mark (cross-shaped / circular) forms a visual positioning reference through a high-contrast geometric pattern (such as a line width of 1 mm and a chamfer design). During manual inspection, the edge grains and non-intact grains can be quickly distinguished, avoiding misjudgment caused by blurred grain edges in traditional microscope inspections (such as improving the identification efficiency of critical defects with a chipping depth < 0.3 mm).

[0017] In some embodiments, when the identification mark is cross-shaped, the corners of its pattern are chamfered, and the chamfer radius is 0.1 - 0.2 mm.

[0018] In some embodiments, probe testing: Using a probe station, separate the good products and bad products according to the required conditions. Mark the bad products with ink. It is only necessary to test each grain on the silicon wafer, and there is no need to detect and dot the edge exclusion zone.

[0019] After omitting the ink dot marking step, the pollution risk of ink solvents (such as diluents) is eliminated, and the cost of chemical waste treatment is reduced.

[0020] The present invention has the following beneficial effects compared with the prior art:

[0021] (1) First, the present invention utilizes the principle of photolithography to draw easily recognizable marks (in the gaps between the outermost grains and the silicon wafer edge) on the gaps outside the outermost grains on a standardized film plate. These marks need to be distinguishable from the alignment marks. This method does not affect the efficiency of operations such as spin coating and exposure, and is convenient and fast. It also does not affect the testing time or cause misjudgment in the MAP. When inspecting the appearance of this silicon wafer, employees can accurately and quickly select the grains with incomplete glass edges and incomplete shapes.

[0022] (2) Traditional GPP marks ink dots on the grains with incomplete glass edges or incomplete grains for quick selection during appearance inspection. However, this method requires marking ink dots on the grains with incomplete glass edges or incomplete grains during testing, which not only affects the testing time but also wastes ink, causes misunderstanding in the MAP of the probe station, and distorts the yield of the probe station software (because the yield is calculated as (total number of grains - number of dotted grains) / total number of grains. At this time, the grains with incomplete glass edges or incomplete grains themselves are not counted as good products during photolithography, but are counted as the total number). When being audited by customers, explanations and verifications need to be provided to the customers. The present invention can improve the accuracy and efficiency of manual appearance inspection and avoid the risk of misjudging defective products outside the outermost circle of the silicon wafer as good products. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 The figure of the film plate used in Embodiment 1 of the present invention;

[0025] Figure 2 The appearance diagram of the nickel-plated silicon wafer in Embodiment 1 of the present invention;

[0026] Figure 3 The partial appearance diagram of the nickel-plated silicon wafer in Embodiment 1 of the present invention;

[0027] Figure 4 The diagram of defective product grains that are easily misjudged in Embodiment 1 of the present invention

[0028] Figure 5 Another diagram of defective product grains that are easily misjudged in Embodiment 1 of the present invention. Detailed implementation manners

[0029] The following will describe the technical solutions in the embodiments of the present invention clearly and completely in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0030] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments of the present invention belong. If the definitions stated in this part are contrary to or inconsistent with the definitions stated in the patents, patent applications, published patent applications and other publications incorporated herein by reference, the definitions listed in this part shall prevail over the definitions incorporated herein by reference.

[0031] Unless otherwise specified, the methods used in the following embodiments are all conventional methods. The materials, reagents and instruments used, unless otherwise specified, are all conventional materials, reagents and instruments in this field, and those skilled in the art can obtain them through commercial channels.

[0032] When an equivalent, concentration or other value or parameter is expressed as a range, a preferred range or a range defined by a series of upper limit preferred values and lower limit preferred values, it should be understood that all ranges formed by any pairing of any range upper limit or preferred value and any range lower limit or preferred value are specifically disclosed, regardless of whether the range is separately disclosed. For example, when the range "1 to 5" is disclosed, the described range should be interpreted as including the ranges "1 to 4", "1 to 3", "1 to 2", "1 to 2 and 4 to 5", "1 to 3 and 5", etc. When a numerical range is described herein, unless otherwise stated, the range is intended to include its end values and all integers and fractions within the range. In the specification and claims of this application, range limitations can be combined and / or interchanged, and if not otherwise stated, these ranges include all sub-ranges contained therein.

[0033] Example 1

[0034] This embodiment provides a wafer processing method using identification marks.

[0035] Steps and parameters:

[0036] Photolithography mark preparation (edge exclusion area)

[0037] Mark design: Cross-shaped mark (line width 1 mm, chamfer radius 0.15 mm), located in the 2.5 mm blank area outside the outermost grains, and does not overlap with the alignment mark.

[0038] Lithography parameters: Chromium plate film (line width error ±0.1μm), exposure energy 120mJ / cm 2 (wavelength 248nm), developer 2.38% TMAH, development time 45 seconds, post-baking 110℃ / 90 seconds.

[0039] Low-temperature etching process

[0040] Mixing ratio of mixed acid: HF:HNO3:CH3COOH:H2SO4 = 9:9:12:4 (volume ratio), temperature -4℃ (temperature control accuracy ±0.5℃), etching time 720 seconds, depth 140 ± 5μm (verified by white light interferometer, Ra ≤ 0.2μm).

[0041] Cleaning: After rinsing with ultrapure water, ultrasonic cleaning with isopropyl alcohol 3 times (2 minutes each time).

[0042] Electrophoretic passivation optimization

[0043] Electrophoretic solution formula: Glass powder (particle size 1 - 3μm) 90g + acetone 8000ml + nitric acid 500ml + additive (ethyl cellulose acetate 2g), voltage 200V, ultrasonic amplitude 12mV, halogen lamp illumination wavelength 400 ± 10nm (current intensity 2A), electrophoresis time 40 minutes.

[0044] Passivation layer characteristics: Thickness 20 ± 2μm (SEM cross-section analysis), porosity ≤ 3% (helium mass spectrometry).

[0045] Glass sintering process

[0046] Sintering conditions: 5-stage diffusion furnace (temperature gradient 800 - 850 - 900 - 850 - 800℃), introducing N2:O2 = 6:5 mixed gas, time 20 minutes.

[0047] Detection: High-temperature leakage current IR ≤ 10μA@150℃ (HTRB test).

[0048] Metal plating and sintering

[0049] Electroless nickel plating: Plating solution formula (nickel chloride 30g / L + sodium hypophosphite 10g / L), double-sided nickel plating thickness 1.5μm, sintering temperature 680℃ (N2:H2 = 9:1, 30 minutes).

[0050] Probe test optimization

[0051] Dynamic data layer: Lithography mark coordinates are stored independently (Halcon algorithm matching accuracy ±5μm), and defective grains in the edge exclusion area are automatically skipped (no need for ink marking and detection).

[0052] Laser cutting calibration

[0053] Cutting parameters: Fiber laser (wavelength 1,064 nm), power 20 W, cutting speed 150 mm / s, chipping rate <1% (SEM cross-section analysis).

[0054] Verification of manual selection efficiency

[0055] Detection standard: Integrity of glass edge (chipping depth ≥ 0.3 mm or length ≥ 0.5 mm).

[0056] Efficiency data: Manual inspection time 8 minutes / wafers (45 minutes by traditional microscope method), miss rate <1% (15% for traditional method).

[0057] Comparative example 1

[0058] Traditional manual inspection with microscope

[0059] Steps and defects:

[0060] Lithography step: Only alignment marks, no edge exclusion zone lithography marks.

[0061] Etching and electrophoresis: Mixing acid ratio 9:9:12:4, process same as in Example 1.

[0062] Manual inspection: Check the outer ring grains one by one under the microscope, chipping standard same as in Example 1.

[0063] Single wafer inspection takes 45 minutes, miss rate 15%.

[0064] Yield distortion: Probe station defaults to full grain testing (including edge defects), yield statistical error ±5%.

[0065] Comparative example 2

[0066] Probe station ink dot marking method

[0067] Steps and defects:

[0068] Lithography step: Same as in Comparative example 1 (no edge marks).

[0069] Probe test: Mark the edge defect grains with ink dots (ink consumption 0.5 ml / wafer).

[0070] Defect analysis:

[0071] Yield conflict: The MAP map mislabels physical defects as electrical failures, yield error ±3%.

[0072] Pollution risk: Ink dot overflow pollutes adjacent grains (extra cleaning steps are required).

[0073] Comparative example 3

[0074] Wafer processing method without chamfer identification marks

[0075] Parameter difference: The cross mark has no chamfer (right-angle connection, line width 0.8 mm).

[0076] Defects: The laser cutting edge chipping rate is 8% (SEM cross-section analysis), and the MAP map positioning deviation > 50 μm.

[0077] The results of the above examples and comparative examples are statistically as follows:

[0078] Index Example Comparative Example 1 Comparative Example 2 Comparative Example 3 Single-wafer inspection time 8 min 45 min 25 min 10 min Omission rate <1％ 15％ 5％ 12％ Yield error ±0.5％ ±5％ ±3％ ±2％ Ink consumption per wafer 0ml - 0.5ml - Die separation chipping rate <1％ - - 8％

[0079] From the comparison between Example 1 and Comparative Example 3 above, it can be seen that the marked part after chamfering can reduce the edge chipping rate by 80%. From the comparison between Example 1 and Comparative Example 1, it can be seen that after adopting the lithography identification mark in this solution, compared with the method of identifying and selecting by optical microscope, the manual detection speed has increased by 5.6 times, the probe test time has also been reduced by 18%, and the automatic alignment effect of the laser cutting path is better, reducing the rework rate. There is no need to dot the grains in the edge exclusion area, saving consumables and reducing the cleaning steps. At the same time, this method makes the MAP map valuable as a reference, omitting the time for the customer's audit report.

[0080] The above is only the preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for improving the accuracy of visually inspecting the appearance of GPP grains, characterized in that, Including: Performing photolithography, etching, electrophoresis, glass sintering, metal plating, probe testing, laser cutting, and appearance selection on the diffused silicon wafers. Among them, for photolithography, on the surface of the silicon wafers after phosphorus diffusion and boron diffusion, identification marks are photolithographed along the outer edge of the outermost ring of grains in the edge exclusion area, and the edge exclusion area is the blank between the outermost ring of grains and the edge of the silicon wafer.

2. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, There are multiple identification marks, and the positions of the identification marks are in the blank between the outermost ring of grains and the edge of the silicon wafer. On the surface of the grains located in the edge exclusion area and having a complete edge after cutting, there is at least one identification mark.

3. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, The method of photolithography includes: exposing through a photomask with identification marks.

4. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, wherein The method of etching includes: etching the photolithographed silicon wafers with a mixed acid. The etching temperature is -5 to -3 °C, the etching time is not less than 600 s, and the etching depth is 125 - 155 μm.

5. The method for improving the appearance accuracy of manually selected GPP grains according to claim 4, characterized in that, The mixed acid is obtained by mixing hydrofluoric acid: nitric acid: glacial acetic acid: sulfuric acid in a volume ratio of (8 - 10):(8 - 10):(10 - 18):(3 - 5).

6. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, The method of electrophoresis includes: preparing an electrophoresis solution, cleaning the etched silicon wafers and then immersing them in the electrophoresis solution, performing electrophoresis at a voltage of 180 - 260 V and an ultrasonic amplitude of 10 - 30 mV to adsorb glass powder into the grain grooves. During electrophoresis, halogen lamp illumination of 100 - 200 V is applied, and the current intensity is 1 - 3 A.

7. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, The temperature of glass sintering is 800 - 900 °C, and the glass sintering atmosphere is a mixed gas of nitrogen: oxygen with a volume ratio of (6 - 10):(5 - 10).

8. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, The shape of the identification mark is circular or cross-shaped, and the size of the widest part of the identification mark is 0.5 - 1.5 mm.

9. The method for improving the appearance accuracy of manually selected GPP grains according to claim 1, characterized in that, When the identification mark is cross-shaped, the corners of its pattern are chamfered, and the chamfer radius is 0.1 - 0.2 mm.

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