Structure and manufacturing method of circuit board with interconnection of any layer of through holes

Abstract

The invention discloses a structure and a manufacturing method of a circuit board with interconnection of any layers of through holes, two ends of an isolation strip which needs to be insulated between layers at the through holes of the circuit board are respectively provided with a concave etching position, the concave etching positions serve as isolation rings, and the concave etching positions are formed after an isolation disc arranged on an inner-layer core plate is etched in a concave mode; the manufacturing method comprises the following steps that a circuit board is provided, a drilling position is arranged on the circuit board, and the drilling position is a position needing to be drilled in subsequent processing; the two ends of the interlayer isolation strip needing insulation at the drilling position of the circuit board are each provided with an isolation disc with the outer diameter larger than the outer diameter of the drilling position. A through hole is drilled in the position, corresponding to the drilling position, of the circuit board, so that the isolation disc on the inner layer is exposed in the through hole, then the isolation disc in the hole is removed through concave etching, and a concave etching position serving as an isolation ring is formed; and after the circuit board is subjected to copper deposition and electroplating, a structure of interconnection of any layers of the through holes is formed. According to the method, a plurality of signals can be transmitted in the same hole, and the purpose of interconnection of any layer in the through hole can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board manufacturing, and particularly relates to a structure and manufacturing method of a through-hole any-layer interconnect circuit board. Background Art

[0002] With the rapid development of communication technologies, the diversification and iterative upgrading of terminal application scenarios have been accelerated. The technologies of AI and artificial intelligence have been continuously evolving, and terminal products are showing trends of being intelligent, thin and light, high-frequency and high-speed, driving the upgrade of PCBs in the direction of high density, high precision, high performance, and high efficiency.

[0003] To meet the requirements of miniaturization, portability, and functional diversification of electronic devices, that is, to accommodate more components within the same size, the technology of PCB processing has been pushed towards higher layers, more dense wiring, smaller line widths, and more high-speed signal lines.

[0004] In the prior art, to transmit multiple signals at a single hole location, the blind via and any-layer interconnect processes can be adopted.

[0005] Compared with the traditional through-hole process, the blind via process can significantly increase the wiring space of the circuit board. Since blind vias and buried vias do not occupy additional space on both the front and back sides of the circuit board, the wiring that was originally restricted by the through-hole occupation can be realized, thereby increasing the wiring density. This not only helps to reduce the size of the circuit board to meet the requirements of miniaturization of electronic devices, but also reduces the signal transmission path length, reduces signal interference, improves signal integrity, and enhances the performance of the circuit. However, the blind via process requires multiple press-fits and electroplating, with complex processes and high costs, and cannot achieve simultaneous connection of the inner layer to adjacent layers.

[0006] The any-layer interconnect (Any Layer Interconnection) process breaks the limitation that traditional multi-layer boards can only be interconnected between adjacent layers, allowing direct connections to be established between any two layers of the circuit board. This process uses laser drilling technology to precisely drill tiny vias between the layers to be interconnected, and then through means such as electroplating, these vias are made into conductive channels to achieve electrical connections between any layers. However, blind via electroplating encounters obstacles when the ratio of the dielectric thickness to the via diameter is relatively large, and the costs of multiple press-fits and electroplating are also very high.

[0007] The PCB signal line manufacturing method, device and printed circuit board of the prior art patent CN119172950A realize the transmission of multiple signal groups through one hole on the PCB board by means of steps such as drilling through holes, first controlled-depth drilling, electroplating, and second controlled-depth drilling. On the premise of meeting the performance of the existing PCB, by optimizing the processing process flow, it is possible to increase the wiring density of signal lines while ensuring the original signal requirements of the traditional through-hole PCB, avoid using the HDI structure for the product, and greatly reduce the cost of the product. However, this method realizes the transmission of two signal groups through one hole through two controlled-depth drillings, with a complex process, insufficient controlled-depth accuracy, and high processing costs. Summary of the Invention

[0008] In view of the above-mentioned existing technical defects, the present invention provides a structure and manufacturing method for a through-hole arbitrary-layer interconnected circuit board, in which paired isolation discs are arranged in the hole to form an insulating isolation belt between two adjacent etched positions after drilling, etching, electroless copper plating and electroplating, so as to realize the transmission of multiple signals in the same hole and achieve the purpose of arbitrary-layer interconnection in the through-hole.

[0009] In the first aspect, in order to solve the above-mentioned technical problems, the present invention provides a structure and manufacturing method for a through-hole arbitrary-layer interconnected circuit board. At both ends of the isolation belt that needs to be insulated between layers at the through-hole of the circuit board, an inwardly concave etched position is provided. This etched position serves as an isolation ring and is formed after the isolation disc provided on the inner-layer core board is etched.

[0010] The manufacturing method includes the following steps:

[0011] S10. Provide a circuit board formed by laminating multiple core boards. The circuit board is provided with drilling positions, which are the positions where drilling is required in subsequent processing. At both ends of the isolation belt that needs to be insulated between layers at the drilling positions of the circuit board, an isolation disc formed by alkali-soluble UV curable ink is provided, and the outer diameter of the isolation disc is larger than the outer diameter of the drilling position.

[0012] S20. Drill through holes at the corresponding drilling positions on the circuit board to expose the inner-layer isolation discs in the through holes, and then remove the isolation discs in the holes by etching to form the etched positions serving as isolation rings.

[0013] S30. The circuit board is subjected to electroless copper plating and electroplating. The etched positions in the hole wall of the through hole and the isolation belt between the two etched positions are not plated with a copper layer, forming a structure for arbitrary-layer interconnection of the through hole.

[0014] Furthermore, the depth of the etched position is 0.1 - 0.25 mm, and the height is 5 - 50 microns.

[0015] Further, when there is a hole wall copper layer connecting at least two inner layers between two isolation strips of the same through hole in the circuit board, this section of the hole wall copper layer is connected to the hole wall copper layer of another through hole through the inner layer circuit and then connected to the outer layer circuit.

[0016] Further, in step S10, before lamination, an isolation disk is pre-formed on the surface of the inner core board corresponding to the isolation ring by coating and curing an alkali-soluble UV curable ink, and the outer diameter of the isolation disk is 0.2 - 0.5 mm larger than the outer diameter of the drilling position, and the thickness of the isolation disk is 5 - 50 microns.

[0017] Further, step S10 specifically includes the following steps:

[0018] S11. Provide a core board with inner layer circuits fabricated thereon, and the core board is provided with drilling positions, where the drilling positions are the positions that need to be drilled in subsequent processing;

[0019] S12. Coat a layer of alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilling position at the drilling positions on the surface of the core board, and expose and cure the alkali-soluble photocurable ink through UV light to form an isolation disk;

[0020] S13. Stack multiple core boards or stack multiple core boards and outer copper foils through prepregs in a preset order and laminate them into a circuit board. In the inner layer of the circuit board, there are a multiple of 2 isolation disks at each corresponding drilling position, and the position of each isolation disk is correspondingly set at the isolation ring position in the circuit board;

[0021] Further, in step S20, during etching, soak the circuit board in a sodium hydroxide solution at 60 degrees Celsius for 30 - 120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

[0022] Further, step S30 specifically includes the following steps:

[0023] S31. Conduct electroless copper plating and DC flash plating on the circuit board in sequence, and no copper layer is plated at the etched positions;

[0024] S32. Then conduct the first pulse electroplating or micro-etching treatment on the circuit board to remove the hole wall copper layer on the isolation strip;

[0025] S33. Finally, conduct DC electroplating or the second pulse electroplating on the circuit board to form a structure with through hole interconnection of any layer.

[0026] Further, in step S31, during DC flash plating, the current density is 0.8 - 1.5 ASD, and the time is 3 - 6 min; during DC flash plating, the hole wall copper layer is thickened by 1 - 5 microns.

[0027] Further, when the first pulse electroplating is carried out after the DC flash plating, the total time of the first pulse electroplating is 6 min, the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 10 mS, the current density of the reverse pulse electroplating is 9 ASD, and the time is 10 mS; after the first pulse electroplating, the circuit board is subjected to the second pulse electroplating, and the second pulse electroplating is plated to the required thickness of the design.

[0028] Further, when the micro-etching treatment is carried out after the DC flash plating, the circuit board is directly immersed in the micro-etching solution for micro-etching, and the micro-etching amount is controlled to be 0.8 - 1.6 microns; after the micro-etching treatment, the circuit board is subjected to DC electroplating, and the hole copper is thickened by 30 microns during the DC electroplating.

[0029] In a second aspect, the present invention also provides another method for manufacturing a circuit board with interconnections between any layers in a through hole. A core board is included between the outer copper foil and the sub-outer layer, and the method includes the following steps:

[0030] S1. Provide a circuit board formed by laminating multiple core boards. Drill positions are provided on the circuit board, and the drill positions are the positions where drilling is required in subsequent processing; an isolation disk is provided at both ends of the isolation belt that needs to be insulated between layers at the drill positions on the circuit board; and the isolation disk is pre-set by coating on the corresponding inner core board before lamination.

[0031] S2. Coat a layer of alkali-soluble photosensitive resin ink with an outer diameter larger than the outer diameter of the drill position at the drill position on at least one surface of the core board, and expose and cure the alkali-soluble photosensitive resin ink by UV light to form an isolation disk.

[0032] S3. Stack multiple core boards or stack multiple core boards and outer copper foils and laminate them into a circuit board in a preset order. A multiple of 2 isolation disks are provided at each drill position in the inner layer of the circuit board.

[0033] S4. Drill through holes at the drill positions on the circuit board to expose the inner isolation disks on the hole walls of the through holes, and an isolation belt is formed between every two adjacent isolation disks in the same through hole.

[0034] S5. Immerse the circuit board in a sodium hydroxide solution to etch away the isolation disks on the hole walls to form etched positions as isolation rings.

[0035] S6. Carry out electroless copper plating and DC flash plating on the circuit board in sequence to metallize the through holes, and then carry out the first pulse electroplating or micro-etching treatment on the circuit board to remove the copper layer on the hole walls of the isolation belt, and finally carry out DC electroplating or the second pulse electroplating on the circuit board.

[0036] Further, in step S2, the outer diameter of the isolation disk is 0.2 - 0.5 mm larger than the outer diameter of the drill position, and the thickness of the isolation disk is 5 - 50 microns.

[0037] Further, in step S4, every two adjacent isolation disks form a group of isolation groups. When there are two groups of isolation groups in the same through hole, the hole wall between the two groups of isolation groups is connected to the hole wall of another through hole through the inner layer circuit.

[0038] Further, in step S5, the circuit board is immersed in a sodium hydroxide solution at 60 °C and soaked for 30 - 120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

[0039] Further, in step S6, the copper layer on the hole wall is thickened by 1 - 5 microns during direct current flash plating.

[0040] Further, in step S6, the current density during direct current flash plating is 0.8 - 1.5 ASD, and the time is 3 - 6 min.

[0041] Further, in step S6, when the first pulse electroplating is carried out after direct current flash plating, the total time of the first pulse electroplating is 6 min, and the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 10 mS, and the current density of the reverse pulse electroplating is 9 ASD, the time is 10 mS.

[0042] Further, after the first pulse electroplating, the circuit board is subjected to the second pulse electroplating, and the second pulse electroplating is plated to the required thickness of the design.

[0043] Further, in step S6, when micro-etching treatment is carried out after direct current flash plating, the circuit board is directly immersed in the micro-etching solution for micro-etching, and the micro-etching amount is controlled to be 0.8 - 1.6 microns.

[0044] Further, in step S6, after micro-etching treatment, direct current electroplating is carried out on the circuit board, and the hole copper is thickened by 30 microns during direct current electroplating.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] In the method of the present invention, at both ends of the isolation belt that needs to be insulated between layers at the drilling positions of the circuit board, there is an isolation disk formed by alkali-soluble UV curable ink. After drilling, the isolation disks in the holes are removed by etching to form etched positions as isolation rings. During copper deposition, the conductivity at the etched positions is very poor and copper will not be deposited. By using the method that copper layers are not deposited at the etched positions, an isolation belt is formed between every two adjacent isolation rings. The copper layers on the hole walls at the isolation belt are dissolved or removed by chemical micro-etching during subsequent electroplating, so as to form a copper-free isolation belt between every two adjacent isolation rings. Only multiple required separated hole wall copper layers are retained in the through holes, thus achieving the purpose of transmitting multiple signals in the same hole and interconnecting any layers in the through hole, that is, achieving the purpose of interconnecting the outer layer with any inner layer and interconnecting at least two arbitrary inner layers. And through this method, there is no need to perform multiple back-drilling to achieve the purpose of transmitting two groups of signals in one hole, with low cost and simple processing. It can replace the existing back-drilling, blind buried holes, and HD I board manufacturing, and can also reduce the number of holes and layers of high-multilayer boards.

[0047] Additional aspects and advantages of the present invention will be given in part in the following description, which will become apparent from the following description or be understood through the practice of the present invention. Brief Description of the Drawings

[0048] Figure 1 Schematic diagram after pressing and synthesizing the circuit board in Embodiment 1;

[0049] Figure 2 Schematic diagram after drilling on the circuit board in Embodiment 1;

[0050] Figure 3 Schematic diagram after etching on the circuit board in Embodiment 1;

[0051] Figure 4 Schematic diagram after chemical copper deposition and DC flash plating on the circuit board in Embodiment 1;

[0052] Figure 5 Schematic diagram after the first pulse electroplating on the circuit board in Embodiment 1;

[0053] Figure 6 Schematic diagram after the second pulse electroplating on the circuit board in Embodiment 1;

[0054] Figure 7 Schematic diagram after pressing and synthesizing the circuit board in Embodiment 2;

[0055] Figure 8 Schematic diagram after drilling on the circuit board in Embodiment 2;

[0056] Figure 9 Schematic diagram after etching on the circuit board in Embodiment 2;

[0057] Figure 10 Schematic diagram after electroless copper plating and direct current flash plating on the circuit board in Example 2;

[0058] Figure 11 Schematic diagram after micro-etching on the circuit board in Example 2;

[0059] Figure 12 Schematic diagram after direct current electroplating on the circuit board in Example 2. Specific implementation manners

[0060] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0061] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0062] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0063] It should be further understood that the term " / and / " used in this specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0064] For a structure and manufacturing method of an interlayer interconnected circuit board in any layer of a through hole shown in this embodiment, a concave etching position is provided at both ends of an isolation strip that needs to be insulated between layers at the through hole of the circuit board, and this etching position serves as an isolation ring. The etching position is formed after the isolation disk provided on the inner layer core board is etched;

[0065] The manufacturing method includes the following steps:

[0066] S10. Provide a circuit board formed by laminating multiple core boards. There are drilling positions on the circuit board, and the drilling positions are the positions where drilling is required in subsequent processing. At both ends of the isolation belt that needs to be insulated between layers at the drilling positions of the circuit board, there is an isolation disk formed by alkali-soluble UV curable ink (that is, there is an isolation disk formed by alkali-soluble UV curable ink at each corresponding etching position in the inner layer of the circuit board), and the outer diameter of the isolation disk is larger than the outer diameter of the drilling position;

[0067] S20. Drill through holes at the positions corresponding to the drilling positions on the circuit board to expose the isolation disks in the inner layer in the through holes, and then remove the isolation disks in the holes by etching to form etching positions as isolation rings;

[0068] S30. Perform copper deposition and electroplating on the circuit board. The etching positions in the hole walls of the through holes and the isolation belts between the two etching positions are not plated with copper layers, forming a structure for interconnecting any layer of the through holes.

[0069] Further, the depth of the etching position is 0.1 - 0.25 mm, and the height is 5 - 50 microns.

[0070] Further, when there is a hole wall copper layer connecting at least two inner layers between the two isolation belts of the same through hole in the circuit board, this section of the hole wall copper layer is connected to the hole wall copper layer of another through hole through the inner layer circuit and then connected to the outer layer circuit.

[0071] Further, in step S10, before lamination, an isolation disk is formed on the surface of the inner layer core board corresponding to the isolation ring by pre-coating and curing alkali-soluble UV curable ink. The outer diameter of the isolation disk is 0.2 - 0.5 mm larger than the outer diameter of the drilling position, and the thickness of the isolation disk is 5 - 50 microns.

[0072] Further, step S10 specifically includes the following steps:

[0073] S11. Provide a core board with inner layer circuits fabricated. There are drilling positions on the core board, and the drilling positions are the positions where drilling is required in subsequent processing;

[0074] S12. Coat a layer of alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilling position at the drilling positions on the surface of the core board, and expose and cure the alkali-soluble photocurable ink by UV light to form an isolation disk;

[0075] S13. Stack multiple core boards in sequence through prepregs or stack multiple core boards and outer copper foils and laminate them into a circuit board. In the inner layer of the circuit board, there are 2 - multiple isolation disks at each corresponding drilling position, and the position of each isolation disk is correspondingly set at the isolation ring position in the circuit board;

[0076] Further, in step S20, during etching, the circuit board is immersed in a sodium hydroxide solution at 60 °C for 30 - 120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

[0077] Further, step S30 specifically includes the following steps:

[0078] S31. Chemically deposit copper and perform direct current flash plating on the circuit board in sequence, and no copper layer is plated at the etched position;

[0079] S32. Then, perform the first pulse electroplating or micro-etching treatment on the circuit board to remove the copper layer on the hole wall of the isolation belt;

[0080] S33. Finally, perform direct current electroplating or the second pulse electroplating on the circuit board to form a structure with through-hole any-layer interconnection.

[0081] Further, in step S31, during direct current flash plating, the current density is 0.8 - 1.5 ASD, and the time is 3 - 6 minutes; during direct current flash plating, the copper layer on the hole wall is thickened by 1 - 5 microns.

[0082] Further, when the first pulse electroplating is used after direct current flash plating, the total time of the first pulse electroplating is 6 minutes, and the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 10 mS, the current density of the reverse pulse electroplating is 9 ASD, and the time is 10 mS; after the first pulse electroplating, the circuit board is subjected to the second pulse electroplating, and the second pulse electroplating is plated to the required thickness of the design.

[0083] Further, when micro-etching treatment is used after direct current flash plating, the circuit board is directly immersed in the micro-etching solution for micro-etching, and the micro-etching amount is controlled to be 0.8 - 1.6 microns; after micro-etching treatment, direct current electroplating is performed on the circuit board, and the hole copper is thickened by 30 microns during direct current electroplating.

[0084] Example 1

[0085] The structure and manufacturing method of a through-hole any-layer interconnection circuit board shown in this example sequentially include the following processing procedures:

[0086] (1) Panel cutting: Cut out multiple FR4 core boards according to the panel size during actual production. The copper layer thickness on both surfaces of the core board is 0.5 oz; drilling positions are provided on the core board, and the drilling positions are the positions where drilling is required in subsequent processing.

[0087] (2) Inner layer circuit manufacturing (negative film process): Inner layer pattern transfer. Use a vertical coater to coat a wet film (i.e., photosensitive alkali-soluble film) on the core board. The film thickness of the wet film is controlled at 10 microns. Use a fully automatic exposure machine to complete the exposure of the inner layer circuit with 5 - 6 exposure scales (21 exposure scales). After development, an inner layer circuit pattern is formed; Inner layer etching. Etch the inner layer circuit on the core board after exposure and development. The measured inner layer line width is 3 mil. In each core board, copper pads are provided at the drilling positions corresponding to the connection with the inner layer circuit and / or the outer layer circuit. The outer diameter of the copper pad is larger than the outer diameter of the drilling position, while no copper pad is provided at the drilling positions not connected to the inner layer circuit and / or the outer layer circuit; Inner layer AOI. After stripping the film, check for defects such as open circuits, short circuits, circuit gaps, and circuit pinholes in the inner layer circuit. Scrape and discard the defective products, and the non-defective products are sent to the next process.

[0088] In one embodiment, the outer diameter of the copper pad is 0.5 mm larger than the outer diameter of the drilling position.

[0089] (3) Coating the protective layer: Coat an alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilling position at the drilling positions on at least one surface of the core board, and expose and cure the alkali-soluble photocurable ink through UV light to form isolation discs, that is, coat and cure the alkali-soluble photocurable ink at the drilling positions on both surfaces or one surface of the core board to form isolation discs. The isolation discs cover the outer surfaces of the copper pads or non-copper pads.

[0090] In one embodiment, the outer diameter of the isolation disc is 0.5 mm larger than the outer diameter of the drilling position, and the thickness of the isolation disc is 50 microns.

[0091] (4) Laminating: As Figure 1 shown, the browning speed is based on the copper thickness of the bottom copper for browning. Stack four core boards 1 and outer copper foils 2 together through prepreg 10 (i.e., PP) in a preset order, and then laminate the stacked boards under appropriate lamination conditions according to the Tg of the board material to form a circuit board; In the inner layer of the circuit board, there are 2 - multiple isolation discs 3 at each drilling position. The isolation discs 3 are arranged in pairs and used in cooperation. Every two adjacent isolation discs 3 form a set of isolation groups. The copper layer on the hole wall between the two isolation discs in the same isolation group needs to be removed. When there are at least two sets of isolation groups at the same drilling position, the copper layer on the hole wall between the adjacent two sets of isolation groups needs to be retained.

[0092] In one embodiment, during stacking, the isolation discs corresponding to the same drilling position in two adjacent core boards can be arranged adjacent to each other, so that an isolation zone will be formed between the isolation discs of the two adjacent core boards in the later stage, separating the copper layers on the hole walls of the two adjacent core boards; Of course, when isolation discs are provided at the drilling positions on both surfaces of the same core board, the copper layers on the hole walls of the upper and lower surfaces of the core board will be separated by the isolation discs on its upper and lower surfaces.

[0093] (5) Drilling: According to the existing drilling technology, through holes 4 are drilled at the corresponding drilling positions on the circuit board according to the design requirements (as shown in Figure 2 ), that is, the through holes penetrate through the middle of the isolation disks 3 in the inner layer up and down, so as to expose the isolation disks 3 on the wall surface of the through holes (as shown in Figure 2 ); and through the isolation disks arranged in groups and pairs, pairwise cooperation is achieved to achieve the purpose of segmented isolation, so that an isolation zone can be designed between every two adjacent isolation disks in the same through hole, that is, an isolation zone is designed between two isolation disks in the same group; when there are two groups of isolation groups in the same through hole, the hole walls between the two groups of isolation groups are connected to the hole wall of another through hole (such as an adjacent through hole or any other through hole connected to this hole) through copper disks and inner layer circuits, that is, the isolation groups in two adjacent through holes or any two connected through holes can be designed with a dislocation design, so that the copper layers on the hole walls between the two connected holes are interconnected and then connected to the outer circuit layer.

[0094] (6) Etching: Immerse the circuit board in a sodium hydroxide solution at 60 °C and soak for 120 minutes to etch away the isolation disks on the hole wall to form an etched position 5 as an isolation ring (as shown in Figure 3 ), the etching depth of the etched position 5 is 250 microns, and the ratio of the depth to the thickness at this etched position is 5:1. The conductivity at the etched position under this ratio is very poor, which can ensure that no copper layer is deposited at the etched position during subsequent electroless copper plating.

[0095] In one embodiment, the concentration of the sodium hydroxide solution is 10%, that is, the mass percentage of the solute (i.e., sodium hydroxide) in the sodium hydroxide solution is 10%, and the rest is water.

[0096] (7) Electroless copper plating: As shown in Figure 3 , a thin layer of copper 6 is deposited on the board surface and hole walls by the method of electroless copper plating (as shown in Figure 4 ) to metallize the through holes, the backlight test is at level 10, and the thickness of the electroless copper deposited in the holes is 0.5 microns.

[0097] (8) DC flash plating: According to the design requirements, DC flash plating is carried out on the circuit board. The current density during DC flash plating is 1.5 ASD and the time is 6 min, so as to thicken the hole copper by 3 - 5 microns; because no copper layer is deposited at the etched position, the conductivity of the copper layer on the hole wall between every two adjacent etched positions (i.e., the etched positions in the same group) is very poor, or even non-conductive, that is, the copper layer on the hole wall at this isolation section is not thickened during DC flash plating.

[0098] (9) First pulse electroplating: The circuit board is electroplated by using periodic positive and negative pulse electroplating. Because no copper layer is deposited at the etched position, the conductivity of the copper layer on the hole wall between every two adjacent etched positions is very poor, or even non-conductive. During positive and negative pulse electroplating, the copper layer on the hole wall of the isolation zone will dissolve into the electroplating solution to form a copper-free isolation zone 7 (as shown in Figure 5As shown, the copper layer on the hole wall with current conduction will be electroplated and thickened.

[0099] In one embodiment, as Figure 5 shown, when there is a copper layer on the hole wall connecting at least two inner layers above and below between two adjacent isolation groups, that is, when there are two isolation groups in the same through hole, in order to prevent the copper layer on the hole wall between the two adjacent isolation groups from being dissolved and removed, this section of the copper layer on the hole wall will be connected to the copper layer on the hole wall of the adjacent hole through the copper pad on the inner layer and the inner layer circuit and then connected to the outer layer circuit. For example, the copper layer in the middle section of hole1 is connected to the copper layer in the upper section of hole2, and the copper layer in the middle section of hole3 is connected to the copper layer in the lower section of hole2.

[0100] In one embodiment, the total time of the first pulse electroplating is 6 min, and the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 10 mS, and the current density of the reverse pulse electroplating is 9 ASD, the time is 10 mS.

[0101] (10) Second pulse electroplating: The circuit board is electroplated by using periodic forward and reverse pulse electroplating, and the copper layer on the hole wall with current conduction will be electroplated and thickened to finally form a conductive layer with the required thickness (as Figure 6 shown).

[0102] In one embodiment, the total time of the second pulse electroplating is 42 min, and the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 20 mS, and the current density of the reverse pulse electroplating is 9 ASD, the time is 10 mS.

[0103] In a specific embodiment, after completing the above step (10), other subsequent processes are sequentially performed on the circuit board according to the prior art, such as manufacturing the outer layer circuit, manufacturing the solder mask, surface treatment, shaping, electrical testing, FQC, FQA, and packaging, etc., and finally the required circuit board is manufactured.

[0104] Embodiment 2

[0105] A method for manufacturing a circuit board with any - layer interconnection in a through hole shown in this embodiment sequentially includes the following processing steps:

[0106] (1) Panel cutting: Cut out multiple FR4 core boards according to the panel size during actual production. The copper layer thickness on both surfaces of the core board is 0.5 oz; drilling positions are provided on the core board, and the drilling positions are the positions where drilling is required in subsequent processing.

[0107] (2) Inner layer circuit manufacturing (negative film process): Inner layer pattern transfer. Use a vertical coater to coat a wet film (i.e., photosensitive alkali-soluble film) on the core board. The film thickness of the wet film is controlled at 10 microns. Use a fully automatic exposure machine to complete the inner layer circuit exposure with 5 - 6 exposure scales (21 exposure scales), and form the inner layer circuit pattern after development; Inner layer etching. Etch the inner layer circuit on the core board after exposure and development. The inner layer line width is measured as 3 mil. In each core board, copper pads are provided at the drilling positions corresponding to the connections with the inner layer circuit and / or the outer layer circuit. The outer diameter of the copper pad is larger than the outer diameter of the drilling position, while no copper pad is provided at the drilling positions not connected to the inner layer circuit and the outer layer circuit; Inner layer AOI. After stripping the film, check for defects such as open circuits, short circuits, circuit gaps, and circuit pinholes in the inner layer circuit. Scrape and discard the defective products, and the non-defective products are sent to the next process.

[0108] In one embodiment, the outer diameter of the copper pad is 0.2 mm larger than the outer diameter of the drilling position.

[0109] (3) Coating the protective layer: Coat a layer of alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilling position at the drilling positions on at least one surface of the core board, and expose and cure the alkali-soluble photocurable ink through UV light to form isolation disks, that is, coat the alkali-soluble photocurable ink at the drilling positions on both surfaces or one surface of the core board and cure it to form isolation disks. The isolation disks cover the outer side surfaces of the copper pads or non-copper pads.

[0110] In one embodiment, the outer diameter of the isolation disk is 0.2 mm larger than the outer diameter of the drilling position, and the thickness of the isolation disk is 25 microns.

[0111] (4) Lamination: The browning speed is based on the copper thickness of the bottom copper for browning. Stack six core boards 1 together through prepreg 10 (i.e., PP) in a preset order (as Figure 7 shown), and then laminate the stacked boards under appropriate lamination conditions according to the Tg of the board material to form a circuit board. The core boards placed on both outer sides are single-sided copper-clad core boards, and the inner layer circuits are not manufactured on the two outer core boards before lamination; In the inner layer of the circuit board, 2 - multiple isolation disks 3 are provided at each corresponding drilling position. The isolation disks 3 are arranged in pairs and used in cooperation. Every two adjacent isolation disks 3 form a set of isolation groups. The copper layer on the hole wall between the two isolation disks in the same isolation group needs to be removed. When there are at least two sets of isolation groups at the same drilling position, the copper layer on the hole wall between the adjacent two sets of isolation groups needs to be retained.

[0112] In this embodiment, the full-core board lamination method is adopted to achieve the purpose of isolating and insulating the outer layer and the sub-outer layer, that is, isolation disks 3 are provided on the adjacent surfaces of the outermost core board and the sub-outermost core board (as shown in the figure).

[0113] In one embodiment, when laminating the plates, the isolation disks corresponding to the same drilling position in two adjacent core plates can be arranged adjacent to each other, so that an isolation zone will be formed between the isolation disks of two adjacent core plates in the later stage, separating the copper layers on the hole walls of the two adjacent core plates; of course, when isolation disks are provided at the drilling positions on both surfaces of the same core plate, the copper layers on the hole walls at the upper and lower surfaces of the core plate will be separated by the isolation disks on its upper and lower surfaces.

[0114] (5) Drilling: According to the existing drilling technology, drill through holes 4 at the corresponding drilling positions on the circuit board according to the design requirements (as Figure 8 shown), that is, the through holes penetrate through the middle of the isolation disks 3 in the inner layer up and down, so as to expose the isolation disks 3 on the wall surface of the through holes (as Figure 8 shown); and through the isolation disks arranged in pairs, the purpose of segmented isolation is achieved by pairwise cooperation, so that an isolation zone can be designed between every two adjacent isolation disks in the same through hole, that is, an isolation zone is designed between two isolation disks in the same group; when there are two groups of isolation groups in the same through hole, the hole walls between the two groups of isolation groups are connected to the hole walls of adjacent through holes through copper disks and inner layer circuits.

[0115] (6) Etching: Immerse the circuit board in a sodium hydroxide solution at 60 °C and soak for 120 minutes to etch away the isolation disks on the hole walls to form an etched position 5 as an isolation ring (as Figure 9 shown), the etching depth of the etched position 5 is 100 microns, and the ratio of the depth to the thickness at this etched position is 4:1. The conductivity at the etched position under this ratio is very poor, which can ensure that no copper layer will be deposited at the etched position during subsequent electroless copper plating.

[0116] In one embodiment, the concentration of the sodium hydroxide solution is 10%, that is, the mass percentage of the solute (i.e., sodium hydroxide) in the sodium hydroxide solution is 10%, and the rest is water.

[0117] (7) Electroless copper plating: As Figure 3 shown, use the method of electroless copper plating to deposit a thin layer of copper 6 on the board surface and hole walls (as Figure 10 shown), metallize the through holes, with a backlight test of 10 levels, and the thickness of the electroless copper deposited in the holes is 0.5 microns.

[0118] (8) DC flash plating: According to the design requirements, perform DC flash plating on the circuit board. The current density during DC flash plating is 1.5 ASD and the time is 6 minutes, so as to thicken the hole copper by 3 - 5 microns; because no copper layer is deposited at the etched position, the conductivity of the copper layer on the hole wall between every two adjacent etched positions (i.e., the etched positions in the same group) is very poor, or even non-conductive, that is, the copper layer on the hole wall at this isolation section is not thickened during DC flash plating.

[0119] (9) Micro-etching: The circuit board is directly immersed in the micro-etching solution for micro-etching treatment, and the micro-etching amount is controlled to be 0.8 - 1.6 microns. The copper layer on the hole wall at the isolation section is not thickened during DC flash plating, and there is only a 0.5-micron-thick electroless copper layer. Thus, this micro-etching amount can ensure that the copper layer on the hole wall at the isolation section is removed by micro-etching to form a copper-free isolation band 7 (as Figure 11 shown), while the copper layer on the hole wall at the non-isolation section remains at least 2 microns thick.

[0120] (10) DC electroplating: DC electroplating is performed on the circuit board. The copper layer on the hole wall with current conduction will be electroplated and thickened by 30 microns to finally form a conductive layer with the required thickness (as Figure 12 shown).

[0121] In a specific embodiment, after completing the above step (10), other subsequent processes are sequentially performed on the circuit board according to the prior art, such as making the outer layer circuit, making the solder mask, surface treatment, shaping, electrical testing, FQC, FQA, and packaging, etc., to finally obtain the required circuit board.

[0122] The technical solutions provided by the embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the embodiments of the present invention. The descriptions of the above embodiments are only applicable to help understand the principles of the embodiments of the present invention; at the same time, for those of ordinary skill in the art, according to the embodiments of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A structure and manufacturing method of a through-hole interconnection circuit board for any layer, characterized in that, At both ends of the insulating isolation belt that needs to be insulated between layers at the through-hole of the circuit board, a concave etching position is provided, and this etching position serves as an isolation ring. The etching position is formed after the isolation disk provided on the inner layer core board is etched. The manufacturing method includes the following steps: S10. Provide a circuit board formed by laminating multiple core boards. The circuit board is provided with drilling positions, and the drilling positions are the positions where drilling is required in subsequent processing. At both ends of the insulating isolation belt that needs to be insulated between layers at the drilling positions of the circuit board, an isolation disk formed by alkali-soluble UV curable ink is provided, and the outer diameter of the isolation disk is larger than the outer diameter of the drilling position. S20. Drill a through-hole at the corresponding drilling position on the circuit board to expose the isolation disk on the inner layer in the through-hole, and then remove the isolation disk in the hole by etching to form an etching position serving as an isolation ring. S30. The circuit board is subjected to electroless copper plating and electroplating. The etching positions in the through-hole wall and the isolation belt between the two etching positions are not plated with a copper layer, forming a structure for interconnecting any layer of the through-hole.

2. The structure and manufacturing method of the through-hole arbitrary layer interconnected circuit board according to claim 1, characterized in that, The depth of the etching position is 0.1 - 0.25 mm, and the height is 5 - 50 microns.

3. The structure and manufacturing method of the through-hole interlayer interconnected circuit board according to claim 1, characterized in that, When there is a hole wall copper layer connecting at least two inner layers between the two isolation belts of the same through-hole in the circuit board, this section of the hole wall copper layer is connected to the hole wall copper layer of another through-hole through the inner layer circuit and then connected to the outer layer circuit.

4. The structure and manufacturing method of the through-hole arbitrary-layer interconnected circuit board according to claim 1, characterized in that In step S10, before lamination, an isolation disk is pre-formed on the surface of the inner layer core board corresponding to the isolation ring by coating alkali-soluble UV curable ink and curing it. The outer diameter of the isolation disk is 0.2 - 0.5 mm larger than the outer diameter of the drilling position, and the thickness of the isolation disk is 5 - 50 microns.

5. The structure and manufacturing method of the through-hole interconnection circuit board with arbitrary layer interconnection according to claim 1 or 4, characterized in that, Step S10 specifically includes the following steps: S11. Provide a core board with inner layer circuits fabricated. The core board is provided with drilling positions, and the drilling positions are the positions where drilling is required in subsequent processing. S12. Coat a layer of alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilling position at the drilling position on the surface of the core board, and expose and cure the alkali-soluble photocurable ink with UV light to form an isolation disk. S13. Stack multiple core boards through prepregs in a preset order or stack multiple core boards and outer copper foils and then laminate them into a circuit board. In the inner layer of the circuit board, a multiple of 2 isolation disks are provided at each corresponding drilling position, and the position of each isolation disk corresponds to the position of the isolation ring in the circuit board.

6. The structure and manufacturing method of the through-hole interconnection circuit board with arbitrary layer interconnection according to claim 1, characterized in that, In step S20, when etching, soak the circuit board in a sodium hydroxide solution at 60 degrees Celsius for 30 - 120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

7. The structure and manufacturing method of the through-hole arbitrary-layer interconnected circuit board according to claim 1, characterized in that, Step S30 specifically includes the following steps: S31. Perform electroless copper plating and DC flash plating on the circuit board in sequence, and no copper layer is plated at the etching position. S32. Then perform the first pulse electroplating or micro-etching treatment on the circuit board to remove the hole wall copper layer on the isolation belt. S33. Finally, perform DC electroplating or the second pulse electroplating on the circuit board to form a structure for interconnecting any layer of the through-hole.

8. The structure and manufacturing method of the through-hole any-layer interconnected circuit board according to claim 7, characterized in that, In step S3, the current density during DC flash plating is 0.8 - 1.5 ASD, and the time is 3 - 6 min; during DC flash plating, the hole wall copper layer is thickened by 1 - 5 microns.

9. The structure and manufacturing method of the through-hole interconnection circuit board with arbitrary layer interconnection according to claim 7, characterized in that, When the first pulse electroplating is carried out after DC flash plating, the total time of the first pulse electroplating is 6 min, and the current density of the forward pulse electroplating in each cycle is 3 ASD, the time is 10 mS, the current density of the reverse pulse electroplating is 9 ASD, and the time is 10 mS; after the first pulse electroplating, the circuit board is subjected to the second pulse electroplating, and the second pulse electroplating is plated to the designed required thickness.

10. The structure and manufacturing method of the through-hole arbitrary-layer interconnected circuit board according to claim 7, characterized in that, When micro-etching treatment is carried out after DC flash plating, the circuit board is directly immersed in the micro-etching solution for micro-etching, and the micro-etching amount is controlled to be 0.8 - 1.6 microns; after the micro-etching treatment, the circuit board is subjected to DC electroplating, and the hole copper is thickened by 30 microns during DC electroplating.

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