Memory controller, memory system, method and storage medium

Abstract

In certain aspects, a method for operating a memory controller is disclosed. The method includes determining a total usage of user data storage space of the memory device. The method further includes determining whether a garbage collection (GC) trigger condition is satisfied based on the total usage of the user data storage space. The method also includes determining whether to perform a GC process on the memory device based on whether a GC trigger condition is satisfied.

Description

Technical Field

[0001] The present disclosure relates to a memory controller, a memory system, and methods of operating the same. Background Art

[0002] Non-volatile storage devices such as solid state drives (SSDs), non-volatile memory express (NVMe), embedded multimedia cards (eMMCs), and universal flash storage (UFS) devices, etc. have gained significant popularity in recent years due to their numerous advantages compared to traditional hard disk drives (HDDs) (e.g., faster read and write speeds, durability and reliability, reduced power consumption, quiet operation, and smaller form factors). For example, non-volatile storage devices such as SSDs can use NAND flash memory for non-volatile storage. The NAND flash memory can perform various operations such as reading, programming (writing), and erasing. For NAND flash memory, the erase operation can be performed at the block level, and the programming operation or the reading operation can be performed at the page level. Summary of the Invention

[0003] In one aspect, a method for operating a memory controller is disclosed. The method includes determining a total usage amount of a user data storage space of a memory device. The method further includes determining whether a garbage collection (GC) trigger condition is satisfied based on the total usage amount of the user data storage space. The method further includes determining whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied.

[0004] In some embodiments, the total usage amount of the user data storage space includes a total number of used data blocks in the user data storage space.

[0005] In some embodiments, determining whether the GC trigger condition is satisfied includes: determining a total number of expected used data blocks in the user data storage space; and determining whether the GC trigger condition is satisfied based on the total number of the used data blocks and the total number of the expected used data blocks.

[0006] In some embodiments, the total number of the used data blocks includes a total number of used virtual blocks in the user data storage space. The total number of the expected used data blocks includes a total number of expected virtual blocks to be used in the user data storage space.

[0007] In some embodiments, determining whether the GC trigger condition is satisfied includes: determining whether the total number of the used data blocks is greater than the total number of the expected used data blocks.

[0008] In some embodiments, in response to the total number of the used data blocks being greater than the total number of the expected used data blocks, it is determined that the GC trigger condition is satisfied. Alternatively, in response to the total number of the used data blocks being less than or equal to the total number of the expected used data blocks, it is determined that the GC trigger condition is not satisfied.

[0009] In some embodiments, determining whether the GC trigger condition is satisfied further includes: determining valid page counts (VPCs) respectively associated with the used data blocks in the user data storage space; and determining whether the minimum VPC among the VPCs is not greater than a VPC threshold.

[0010] In some embodiments, in response to the total number of the used data blocks being greater than the total number of the expected used data blocks and the minimum VPC not being greater than the VPC threshold, it is determined that the GC trigger condition is satisfied. Alternatively, in response to the total number of the used data blocks not being greater than the total number of the expected used data blocks or the minimum VPC being greater than the VPC threshold, it is determined that the GC trigger condition is not satisfied.

[0011] In some embodiments, determining the total number of the expected used data blocks includes: determining a logical saturation degree of the memory device as a ratio between a total size of valid data in the user data storage space and a size of the user data storage space; and determining the total number of the expected used data blocks based on the logical saturation degree.

[0012] In some embodiments, the total size of the valid data in the user data storage space includes a total number of valid pages in the user data storage space.

[0013] In some embodiments, determining the total number of the expected used data blocks based on the logical saturation degree includes: in response to the logical saturation degree not being greater than a first saturation threshold, determining the total number of the expected used data blocks as a predetermined fixed value.

[0014] In some embodiments, determining the total number of the expected used data blocks based on the logical saturation degree further includes: in response to the logical saturation degree not being less than a second saturation threshold, determining the total number of the expected used data blocks as a first saturation variable having a linear relationship with the logical saturation degree.

[0015] In some embodiments, further comprising, based on the degree of logical saturation, determining the total number of data blocks to be used as expected: in response to the degree of logical saturation being greater than the first saturation threshold and less than the second saturation threshold, when the degree of logical saturation is equal to the second saturation threshold, determining a first value of the first saturation variable; determining a second saturation variable having a non-linear relationship with the degree of logical saturation; and determining the total number of data blocks to be used as expected as the minimum of: the first value of the first saturation variable, and the second saturation variable.

[0016] In some embodiments, the GC process is a background GC process. Determining whether to perform the GC process on the memory device includes: in response to satisfying the GC trigger condition, performing the GC process on the memory device by: determining VPCs respectively associated with the used data blocks in the user data storage space; selecting a first data block having the minimum VPC among the VPCs from the used data blocks; generating and sending a read command to instruct the memory device to read data stored in the valid page set from the first data block; receiving the data stored in the valid page set from the first data block of the memory device; and generating and sending a programming command to instruct the memory device to program the data stored in the valid page set into a second data block in the user data storage space.

[0017] In some embodiments, generating and sending an erase command to instruct the memory device to erase data stored in the first data block. Updating the total number of the used data blocks.

[0018] In some embodiments, determining whether the GC termination condition is satisfied. In response to satisfying the GC termination condition, terminating the GC process.

[0019] In some embodiments, determining whether the GC termination condition is satisfied includes: determining whether the total number of the used data blocks is less than or equal to the total number of data blocks to be used as expected; and in response to the total number of the used data blocks being less than or equal to the total number of data blocks to be used as expected, determining that the GC termination condition is satisfied.

[0020] In some embodiments, determining whether the GC termination condition is satisfied includes: determining VPCs respectively associated with the used data blocks in the user data storage space; determining whether the minimum VPC among the VPCs is greater than the VPC threshold; and in response to the minimum VPC being greater than the VPC threshold, determining that the GC termination condition is satisfied.

[0021] In some embodiments, the total number of the used data blocks is extracted from the memory controller.

[0022] In some embodiments, the memory device includes a NAND flash memory.

[0023] In another aspect, a memory controller includes a memory configured to store instructions and a processor coupled to the memory and configured to execute the instructions to perform a process. The process includes determining a total usage amount of a user data storage space of a memory device. The process further includes determining whether a GC trigger condition is satisfied based on the total usage amount of the user data storage space. The process further includes determining whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied.

[0024] In some embodiments, the total usage amount of the user data storage space includes the total number of used data blocks in the user data storage space. Determining whether the GC trigger condition is satisfied includes: determining a total number of data blocks expected to be used in the user data storage space; and determining whether the GC trigger condition is satisfied based on the total number of the used data blocks and the total number of the data blocks expected to be used.

[0025] In some embodiments, determining whether the GC trigger condition is satisfied includes: determining whether the total number of the used data blocks is greater than the total number of the data blocks expected to be used.

[0026] In some embodiments, determining whether the GC trigger condition is satisfied further includes: determining VPCs respectively associated with the used data blocks in the user data storage space; and determining whether a minimum VPC among the VPCs is not greater than a VPC threshold.

[0027] In some embodiments, the process further includes: determining that the GC trigger condition is satisfied in response to the total number of the used data blocks being greater than the total number of the data blocks expected to be used and the minimum VPC not being greater than the VPC threshold; or determining that the GC trigger condition is not satisfied in response to the total number of the used data blocks not being greater than the total number of the data blocks expected to be used or the minimum VPC being greater than the VPC threshold.

[0028] In some embodiments, determining the total number of the data blocks expected to be used includes: determining a logical saturation degree of the memory device as a ratio between a total size of valid data in the user data storage space and a size of the user data storage space; and determining the total number of the data blocks expected to be used based on the logical saturation degree.

[0029] In yet another aspect, a memory system includes a memory device and a memory controller operatively coupled to the memory device. The memory controller is configured to: determine a total usage amount of a user data storage space of the memory device. The memory controller is further configured to: determine whether a GC trigger condition is satisfied based on the total usage amount of the user data storage space. The memory controller is further configured to: determine whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied.

[0030] In some embodiments, the total usage amount of the user data storage space includes a total number of used data blocks in the user data storage space. To determine whether the GC trigger condition is satisfied, the memory controller is configured to: determine a total number of expected used data blocks in the user data storage space; and determine whether the GC trigger condition is satisfied based on the total number of the used data blocks and the total number of the expected used data blocks.

[0031] In some embodiments, to determine whether the GC trigger condition is satisfied, the memory controller is configured to: determine whether the total number of the used data blocks is greater than the total number of the expected used data blocks.

[0032] In some embodiments, to determine whether the GC trigger condition is satisfied, the memory controller is further configured to: determine VPCs respectively associated with the used data blocks in the user data storage space; and determine whether a minimum VPC among the VPCs is not greater than a VPC threshold.

[0033] In some embodiments, to determine the total number of the expected used data blocks, the memory controller is configured to: determine a logical saturation degree of the memory device as a ratio between a total size of valid data in the user data storage space and a size of the user data storage space; and determine the total number of the expected used data blocks based on the logical saturation degree.

[0034] In yet another aspect, a non-transitory computer-readable storage medium including instructions is disclosed, and the instructions, when executed by a processing device, cause the processing device to execute a method. The method includes: determining a total usage amount of a user data storage space of a memory device. The method further includes: determining whether a GC trigger condition is satisfied based on the total usage amount of the user data storage space. The method further includes: determining whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings incorporated herein and forming a part of the specification illustrate aspects of the present disclosure, and together with the description further explain the principles of the present disclosure and enable those skilled in the relevant art to implement and use the present disclosure.

[0036] Figure 1 A block diagram of a system including a memory system is shown in accordance with some aspects of the present disclosure.

[0037] Figure 2A A diagram of a memory card having a memory device is shown in accordance with some aspects of the present disclosure.

[0038] Figure 2B A diagram of a solid state drive (SSD) having a memory device is shown in accordance with some aspects of the present disclosure.

[0039] Figure 3A A block diagram of a memory controller is shown in accordance with some aspects of the present disclosure.

[0040] Figure 3B An exemplary interaction between a memory controller and a non-volatile (NV) memory device is shown in accordance with some aspects of the present disclosure.

[0041] Figure 4 A schematic diagram of a NAND flash memory device including peripheral circuits is shown in accordance with some aspects of the present disclosure.

[0042] Figure 5 A flowchart of a method for operating a memory controller is shown in accordance with some aspects of the present disclosure.

[0043] Figures 6A - 6B An exemplary process for operating a memory controller and a memory device is shown in accordance with some aspects of the present disclosure.

[0044] Figures 7A - 7C An exemplary garbage collection process is shown in accordance with some aspects of the present disclosure.

[0045] Figures 8 - 9 Exemplary simulation results of a garbage collection (GC) scheme in which the degree of logical saturation is applied as disclosed herein are shown in accordance with some aspects of the present disclosure.

[0046] The present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0047] Generally, terms can be understood, at least in part, based on their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or property in a singular sense or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a," "an," or "the" can likewise be understood to express a singular usage or a plural usage, at least in part, depending on the context. Additionally, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but rather, depending at least in part on the context, can alternatively allow for the existence of other factors that are not necessarily expressly described.

[0048] Garbage collection (GC) is a process by which non-volatile memory devices optimize storage space, improve read and write efficiency, and keep the non-volatile memory devices working as efficiently as possible. Non-volatile memory devices can read and write data in pages and erase data in blocks, where each block has hundreds of pages. Although non-volatile memory devices can write new data quickly, they take longer to overwrite data. To erase a block, a non-volatile memory device needs to copy the valid data of the block to another block and then erase all the data in that block. GC can help non-volatile memory devices maintain fast read and write speeds. An exemplary goal of GC is to keep as many empty blocks as possible so that when non-volatile memory devices need to write data, they can write without waiting to erase a block.

[0049] Non-volatile memory devices such as SSDs typically use NAND flash as the non-volatile storage device. A NAND flash device can include multiple die, where each die has multiple planes. Each plane can be divided into multiple physical blocks (e.g., a physical block can be the basic data unit for an erase operation). A virtual block (VB) can include one or more physical blocks. For example, a NAND flash device can have 4 die, where each die has 6 planes, such that the NAND flash device can have a total of 4 × 6 = 24 planes. A virtual block can include one physical block from each plane, such that the virtual block can include 24 physical blocks from 24 planes respectively. Data stored in the physical blocks within the same virtual block can be read out in parallel. Similarly, new data can also be written in parallel to the physical blocks within the same virtual block.

[0050] The number of available virtual blocks released by GC can directly affect the write performance of NAND flash memory devices. Specifically, after a NAND flash memory device has been used for a long time, the available storage space decreases, and write performance may degrade due to the lack of available virtual blocks. In practice, occupied virtual blocks can be released by applying background garbage collection (BGC) with various BGC strategies. However, GC (e.g., BGC) may cause various adverse effects. For example, since NAND flash memory devices write data in pages but erase data in blocks, the amount of data written to the NAND flash memory device during GC is greater than the actual update amount, which is referred to as write amplification. When the amount of data to be written to the NAND flash memory device is large, the write speed may be slow. Therefore, it may be difficult to form a new GC strategy and apply it to NAND flash memory devices because various factors need to be considered.

[0051] To address one or more of the above-mentioned problems, the present disclosure introduces a GC scheme in which the degree of logical saturation is applied, which can greatly enhance write performance. For example, by applying the GC scheme disclosed herein, although the write amplification may increase slightly, the write speed can be significantly improved, especially when the memory device is a dirty disk with high-capacity usage and severe file fragmentation. In addition, the GC scheme disclosed herein can meet the user's requirements for aging tests. For example, when the degree of logical saturation is greater than 95%, the performance degradation of the memory device is less than 20%. In addition to considering the VPC of the used data blocks, the GC scheme disclosed herein also considers the degree of logical saturation of the memory device. Therefore, the GC scheme disclosed herein can flexibly arrange GC strategies based on the total usage of the user data storage space of the memory device.

[0052] Figure 1 FIG. shows a block diagram of a system 100 including a memory system 102 in accordance with some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet device, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As Figure 1As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data (also referred to as user data or host data) to the memory system 102 or receive the data from the memory system 102. The memory system 102 may be a storage product integrating the memory controller 106 and one or more memory devices 104 (e.g., SSD).

[0053] The memory device 104 may be any memory device disclosed in the present disclosure, which includes non-volatile memory devices such as NAND flash memory devices. In some embodiments, the memory device 104 further includes one or more volatile memory devices, such as DRAM devices or static random access memory (SRAM) devices.

[0054] According to some embodiments, the memory controller 106 is operatively coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 may manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in low-duty-cycle environments such as, for example, Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the memory controller 106 is designed to operate in high-duty-cycle environments where Solid State Drives (SSDs) or Embedded Multimedia Cards (eMMCs) are used as data storage devices for mobile devices (e.g., smartphones, tablet devices, laptop computers, etc.) and as enterprise storage arrays. The memory controller 106 may be configured to control the operations of the memory device 104 (e.g., read, program / write, and / or erase operations). The memory controller 106 may also be configured to manage various functions related to data stored in or to be stored in the memory device 104, where these functions include but are not limited to bad block management, garbage collection, logical-to-physical (L2P) address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is further configured to process Error Correction Codes (ECCs) related to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols such as, for example, Non-Volatile Memory Express (NVMe) protocol, fabric-based NVMe (NVMe-over-fabrics, NVMe-oF) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, and the like.

[0055] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, such as included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 may be implemented and packaged into different types of end-user electronic products. In Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 for coupling the memory card 202 to a host (e.g., Figure 1 the host 108 in Figure 2B ). In another example shown in Figure 1 , the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 for coupling the SSD 206 to a host (e.g.,

[0056] Figure 3A the host 108 in Figure 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202. In some embodiments, the memory system 102 is implemented as an SSD 206, and the SSD 206 includes both a non-volatile memory device and a volatile storage device as the memory device 104, such as an enterprise SSD. Figure 3A FIG. shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 can be

[0057] an example of the memory controller 106 in Figure 3AAs shown, the memory controller 300 may further include various input / output (I / O) interfaces (I / F), such as a non-volatile memory interface 312, a DRAM interface 314, and a host interface 316, which are operatively coupled to a non-volatile memory device 302 (e.g., a flash memory), a DRAM 304 (e.g., an example of a volatile memory device), and a host 306 (e.g., an example of the host 108), respectively. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 may be respectively configured to transfer data, commands, clocks, or any suitable signals between the processor 308 and the non-volatile memory device 302, the DRAM 304, and the host 306. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 may implement any suitable communication protocols for facilitating data transfer, communication, and management, such as the NVMe protocol and the PCI-E protocol, the double data rate (DDR) protocol, and so on.

[0058] As described above, it can be considered that both the cache 310 and the DRAM 304 are volatile memory devices that can be controlled and accessed by the memory controller 300 in the memory system. Consistent with the scope of the present disclosure, the cache may be implemented as part of a volatile memory device, for example, the cache may be implemented by SRAM and / or DRAM 304. It should be understood that although Figure 3A the cache 310 is shown within the memory controller 300 and the DRAM 304 is shown outside the memory controller 300, in some examples, both the cache 310 and the DRAM 304 may be within the memory controller 300, or both may be outside the memory controller 300.

[0059] Consistent with the scope of the present disclosure and described in detail below, the memory controller 300 may be configured to determine the total usage of the user data storage space of the non-volatile memory device 302. The memory controller 300 may determine whether a GC trigger condition is met based on the total usage of the user data storage space. The memory controller 300 may further determine whether to perform a GC process on the non-volatile memory device 302 based on whether the GC trigger condition is met. The memory controller 300 is described in more detail below with reference to Figures 5 - 7C The memory controller 300 is described in more detail.

[0060] Figure 3B Shows according to some aspects of the present disclosure Figure 3AExemplary interaction between the memory controller 300 and the non-volatile memory device 302. In some embodiments, the memory controller 300 may send at least one of an address (ADDR) signal, a control (CTRL) signal, or a command (CMD) signal to the non-volatile memory device 302. In some embodiments, the memory controller 300 may receive data to be stored in the non-volatile memory device 302 from a host (e.g., host 108). The memory controller 300 may send a programming command along with the received data to the non-volatile memory device 302 for storage. Alternatively or additionally, the memory controller 300 may send a read command to the non-volatile memory device 302 and extract data corresponding to the read command from the non-volatile memory device 302. The following is with reference to Figures 6A - 6B to illustrate a further exemplary interaction between the memory controller 300 and the non-volatile memory device 302.

[0061] Figure 4 A schematic circuit diagram of a NAND flash device 400 including a peripheral circuit 402 is shown in accordance with some aspects of the present disclosure. The NAND flash device 400 may be Figure 3A an example of the non-volatile memory device 302 in

[0062] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible levels (storage states) and can thus store one bit of data. For example, a first state "0" may correspond to a first range of threshold voltages, and a second state "1" may correspond to a second range of threshold voltages. In some embodiments, each memory cell 406 is an xLC capable of storing more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (also referred to as a multi-level cell (MLC)), three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each xLC can be programmed to exhibit a series of possible nominal storage values (i.e., corresponding to 2 N to N bits of data). In some embodiments, each memory cell 406 is set to one of the levels corresponding to one N-bit data in 2 N levels, where N is an integer greater than 1. N can represent the total number of bits per cell. For example, for an MLC, N = 2, for a TLC, N = 3, or for a QLC, N = 4.

[0063] As Figure 4 shown, each memory string 408 may also include a source select gate (SSG) transistor 410 at its source extreme and a drain select gate (DSG) transistor 412 at its drain extreme. The SSG transistor 410 and the DSG transistor 412 can be configured to activate a selected memory string 408 (a column in the array) during read and program operations. In some embodiments, the sources of the memory strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the drain of each memory string 408 is coupled to a corresponding bit line 416, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 408 is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of the corresponding DSG transistor 412 via one or more DSG lines 413 and / or by applying a select voltage or a deselect voltage to the gate of the corresponding SSG transistor 410 via one or more SSG lines 415.

[0064] As Figure 4As shown, the memory string 408 can be organized into multiple blocks 404, and each block 404 can have a common source line 414 (e.g., coupled to the ACS). In some embodiments, each block 404 is a basic data unit for an erase operation, i.e., all the memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 in a selected block 404, the source line 414 coupled to the selected block 404 and the unselected blocks 404 in the same plane as the selected block 404 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher).

[0065] The memory cells 406 of adjacent memory strings 408 can be coupled by word lines 418, and which row of memory cells 406 is selected by the word lines 418 is affected by read and program operations. Each word line 418 can include multiple control gates (gate electrodes) coupled to the word line 418 at each memory cell 406 and gate lines for coupling the control gates.

[0066] The peripheral circuit 402 can be operatively coupled to the memory cell array 401 through bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 can include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 401 by applying voltage signals and / or current signals to each selected memory cell 406 and sensing voltage signals and / or current signals from each selected memory cell 406 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 can include various types of peripheral circuits formed using complementary metal oxide semiconductor (CMOS) technology.

[0067] Figure 5 A flowchart of a method 500 for operating a memory controller according to some aspects of the present disclosure is shown. The memory controller can be any suitable memory controller disclosed herein, such as the memory controller 300. The memory controller can be operatively coupled to a non-volatile memory device (e.g., the memory device 302) and control the operation of the memory device 302. By way of example, the following is described with reference to the memory controller 300 and the memory device 302 Figure 5 , without loss of generality. It should be understood that the operations shown in the method 500 may not be exhaustive, and other operations may also be performed before, after, or between any of the shown operations. In addition, some of these operations can be performed simultaneously, or in an order different from the Figure 5 order shown.

[0068] Consistent with some aspects of the present disclosure, the memory controller 300 may apply the GC scheme disclosed herein in which the degree of logical saturation is applied to determine whether to perform a GC process on the memory device 302. In some embodiments, the GC scheme disclosed herein may include a foreground GC process or a background GC process, which is not limited herein.

[0069] For example, the GC scheme disclosed herein includes a background GC process. Determine whether the foreground tasks of the memory controller 300 are completed. For example, the memory controller 300 may determine whether there are any foreground tasks to be executed. If at least a part or all of the foreground tasks are completed, the memory controller 300 may continue to execute method 500. Exemplary foreground tasks may include, but are not limited to: bad block management, L2P address translation, L2P table update, error correction operations related to data read from or written to the memory device 302, and so on.

[0070] Refer to Figure 5 , method 500 begins at operation 504, in which the total usage of the user data storage space of the memory device 302 may be determined. The user data storage space of the memory device 302 may be the storage space available for users in the memory device 302. For example, the user data storage space may be the storage space visible to the user, the storage space that the user can use to store data, or the card size of the SSD (referred to as "cardsize"), and so on. The entire storage space of the storage device 302 may include a user data storage space and a redundant storage space. The redundant storage space may be a spare storage space, and the spare storage space may be used as a backup of the user data storage space, which may be referred to as "OP".

[0071] In some embodiments, data blocks may be used to measure each storage space (e.g., user data storage space, redundant storage space, etc.). Each data block may be a virtual block, a physical block, or any other suitable data unit, which is not limited herein. For example, the user data storage space may include a first set of data blocks available for users (e.g., a first set of virtual blocks). The redundant storage space may include a second set of data blocks (e.g., a second set of virtual blocks), which may be used as spare blocks for the first set of data blocks in the user data storage space.

[0072] In some embodiments, the user data storage space may include used data blocks and unused data blocks (e.g., free blocks or empty blocks). Each used or unused data block may include a plurality of pages. For example, each used data block may include at least one of a first set of valid pages, a second set of invalid pages, and a third set of free pages. If the data stored in a page is valid, the page may be referred to as a valid page. If the data stored in a page is invalid, the page may be referred to as an invalid page. A free page may be an empty page in which no data is stored. All pages in an unused data block are free pages (or empty pages). The following will refer to Figures 7A - 7C to illustrate examples of used data blocks and unused data blocks.

[0073] In some embodiments, the memory controller 300 may determine and record the total usage of the user data storage space of the memory device 302. For example, the memory controller 300 may determine and record the total number of used data blocks in the user data storage space. For each used data block, the memory controller 300 may also determine and record the valid page count (VPC) for the used data block.

[0074] For example, the host 108 may send the data to be stored in the memory device 302 to the memory controller 300, causing the memory controller 300 to allocate one or more free pages in one or more used data blocks (or unused data blocks) of the memory device 302 for storing the data. The memory controller 300 may send a programming command, the address information of one or more free pages, and the data to the memory device 302, such that the memory device 302 stores the data in one or more free pages. Then, the memory controller 300 may update the total number of used data blocks in the memory device 302, as well as the VPC of the data blocks involved in the data storage.

[0075] In another example, host 108 may send a delete command to memory controller 300 to delete some data stored in memory device 302. Memory controller 300 may identify one or more pages storing data in one or more used data blocks of memory device 302. Memory controller 300 may update the L2P mapping table and mark the one or more pages as invalid pages. Then, memory controller 300 may update the VPCs of one or more used data blocks involved in data storage. As described in more detail below, if one or more used data blocks involved in data storage are released by the GC scheme disclosed herein, memory controller 300 may also update the total number of used data blocks in memory device 302. For example, after one or more used data blocks are released by the GC process disclosed herein, the one or more used data blocks may be marked as empty blocks.

[0076] In some embodiments, when the firmware of memory controller 300 (e.g., data block management firmware) is executed, the recording and updating of the total number of used data blocks, and the recording and updating of the VPCs in each used data block may be performed. In some embodiments, the recording and updating of the total number of used data blocks, and the recording and updating of the VPCs in each used data block may be performed by hardware (e.g., a hardware accelerator circuit such as accelerator 307). It should be understood that the recording and updating of the total number of used data blocks, and the recording and updating of the VPCs in each used data block may be performed using firmware, software, hardware, or any combination thereof, which is not limited herein.

[0077] Method 500 proceeds to operation 506, as Figure 5 shown, in operation 506, it is determined whether a GC trigger condition is met based on the total usage of the user data storage space. It is also determined whether to perform a GC process on memory device 302 based on whether the GC trigger condition is met. For example, if it is determined based on the total usage of the user data storage space that the GC trigger condition is met, method 500 may proceed to operation 508 to perform a GC process on memory device 302. On the other hand, if the GC trigger condition is not met, method 500 may return to operation 504 and not perform a GC process on memory device 302.

[0078] In some embodiments, the memory controller 300 may determine the total number of data blocks expected to be used in the user data storage space. Specifically, the memory controller 300 may determine the logical saturation level of the memory device 302 as the ratio between (1) the total size of the valid data in the user data storage space and (2) the size of the user data storage space. That is, the logical saturation level = the total size of the valid data in the user data storage space / the size of the user data storage space. In some embodiments, the total size of the valid data in the user data storage space may include the total number of valid pages in the user data storage space, and the size of the user data storage space may include the total number of pages in the user data storage space. For example, the total size of the valid data may be measured as the total size of all valid pages in the user data storage space, such as 100 GB. The size of the user data storage space may be measured as the total size of all pages in the user data storage space, including valid pages, invalid pages, and empty pages, such as 128 GB. Then, the logical saturation level is equal to 100 / 128×100% = 78.1%.

[0079] Then, the memory controller 300 may determine the total number of data blocks expected to be used based on the logical saturation level. The data blocks expected to be used may include the data blocks expected to be used based on the logical saturation level of the memory device 302. The data blocks expected to be used may be the same as or different from the used data blocks. For example, the used data blocks may include the virtual blocks that have been used in the user data storage space. The data blocks expected to be used may include the virtual blocks expected to be used in the user data storage space.

[0080] In a first example, the memory controller 300 may determine whether the logical saturation level is not greater than a first saturation threshold. In response to the logical saturation level not being greater than the first saturation threshold (e.g., the logical saturation level ≤ the first saturation threshold), the memory controller 300 may determine the total number of data blocks expected to be used as a predetermined fixed value. The first saturation threshold may be predetermined or adjusted based on actual needs (e.g., the first saturation threshold may be in the range between 10% and 20%). For example, when the logical saturation level is less than or equal to the first saturation threshold, the memory controller 300 may determine the total number of data blocks expected to be used as follows: the total number of data blocks expected to be used = C1×(cardsize + OP), where cardsize represents the size of the user data storage space, and OP represents the size of the redundant storage space. C1 may be a first coefficient determined based on actual needs or actual measurements in the industry. For example, C1 may be in the range between 20% and 30%. The size of the redundant storage space "OP" may be determined based on the actual storage usage of the memory device 302 through the execution of firmware, software, or hardware (which is not limited herein).

[0081] In a second example, the memory controller 300 may determine whether the logical saturation level is not less than a second saturation threshold. In response to the logical saturation level being not less than the second saturation threshold (e.g., logical saturation level ≥ second saturation threshold), the memory controller 300 may determine the total number of data blocks to be used as a first saturation variable that has a linear relationship with the logical saturation level. The second saturation threshold may be predetermined or adjusted based on actual needs (e.g., the second saturation threshold may be in the range between 80% and 95%). For example, when the logical saturation level is equal to or greater than the second saturation threshold, the memory controller 300 may determine the total number of data blocks to be used as follows: Total number of data blocks to be used = First saturation variable = cardsize × logical saturation level × C2. C2 may be a second coefficient determined based on actual needs or actual measurements in the industry.

[0082] In a third example, the memory controller 300 may determine whether the logical saturation level is greater than a first saturation threshold and less than a second saturation threshold. In response to the logical saturation level being greater than the first saturation threshold and less than the second saturation threshold (e.g., first saturation threshold < logical saturation level < second saturation threshold), when the logical saturation level is equal to the second saturation threshold, the memory controller 300 may determine a first value of the first saturation variable. For example, the first value of the first saturation variable = cardsize × second saturation threshold × C2. The memory controller 300 may also determine a second saturation variable that has a non - linear relationship with the logical saturation level. For example, Second saturation variable = cardsize × [C3 × (logical saturation level) 2 + C4 × logical saturation level + C5]. C3, C4, and C5 may be a third coefficient, a fourth coefficient, and a fifth coefficient determined based on actual needs or actual measurements in the industry. Then, the memory controller 300 may determine the total number of data blocks to be used as the minimum of the following: the first value of the first saturation variable, and the second saturation variable. For example, Total number of data blocks to be used = min{cardsize × [C3 × (logical saturation level) 2 + C4 × logical saturation level + C5], cardsize × second saturation threshold × C2}.

[0083] In some embodiments, the memory controller 300 may determine whether the GC trigger condition is met based on the total number of used data blocks and the total number of expected-to-be-used data blocks. For example, the memory controller 300 may determine whether the total number of used data blocks is greater than the total number of expected-to-be-used data blocks. In response to the total number of used data blocks being greater than the total number of expected-to-be-used data blocks (e.g., total number of used data blocks > total number of expected-to-be-used data blocks), the memory controller 300 may determine that the GC trigger condition is met. Or, in response to the total number of used data blocks being less than or equal to the total number of expected-to-be-used data blocks (e.g., total number of used data blocks ≤ total number of expected-to-be-used data blocks), the memory controller 300 may determine that the GC trigger condition is not met.

[0084] In another example, the memory controller 300 may determine the VPCs respectively associated with the used data blocks in the user data storage space. The memory controller 300 may determine whether the minimum VPC among the VPCs is not greater than the VPC threshold. In response to the minimum VPC not being greater than the VPC threshold (e.g., minimum VPC ≤ VPC threshold), the memory controller 300 may determine that the GC trigger condition is met. Or, in response to the minimum VPC being greater than the VPC threshold (e.g., minimum VPC > VPC threshold), the memory controller 300 may determine that the GC trigger condition is not met. In some embodiments, the VPC threshold may be the product of the total number of pages in a data block and the sixth coefficient C6 (e.g., VPC threshold = total number of pages in a data block × C6). C6 may be determined based on the actual needs or actual measurements in the industry. For example, C6 may be in the range between 80% and 95%.

[0085] In yet another example, the memory controller 300 may determine (1) whether the total number of used data blocks is greater than the total number of expected-to-be-used data blocks, and (2) whether the minimum VPC among the VPCs is not greater than the VPC threshold. In response to (1) the total number of used data blocks being greater than the total number of expected-to-be-used data blocks and (2) the minimum VPC not being greater than the VPC threshold (e.g., total number of used data blocks > total number of expected-to-be-used data blocks, and minimum VPC ≤ VPC threshold), the memory controller 300 may determine that the GC trigger condition is met. Or, in response to (1) the total number of used data blocks not being greater than the total number of expected-to-be-used data blocks or (2) the minimum VPC being greater than the VPC threshold (e.g., total number of used data blocks ≤ total number of expected-to-be-used data blocks, or minimum VPC > VPC threshold), the memory controller 300 may determine that the GC trigger condition is not met.

[0086] In some embodiments, the total number of used data blocks may include the total number of virtual blocks that have been used in the user data storage space. The total number of data blocks expected to be used may include the total number of virtual blocks expected to be used in the user data storage space.

[0087] Method 500 proceeds to operation 508, as Figure 5 shown, in operation 508, a GC process may be performed on the memory device 302. In some embodiments, the GC process may be a background GC process. In response to satisfying a GC trigger condition, the memory controller 300 may perform a GC process on the memory device 302. For example, the memory controller 300 may determine the VPCs respectively associated with the used data blocks in the user data storage space. The memory controller 300 may select a first data block having the smallest VPC among the VPCs from the used data blocks. The memory controller 300 may generate and send a read command to instruct the memory device 302 to read the data stored in the valid page set from the first data block. The memory controller 300 may receive the data stored in the valid page set of the first data block from the memory device 302. The memory controller 300 may generate and send a program command to instruct the memory device 302 to program the data previously stored in the valid page set of the first data block to a second data block in the user data storage space.

[0088] In addition, the memory controller 300 may generate and send an erase command to instruct the memory device 302 to erase the data stored in the first data block. The memory controller 300 may update the records of the used data blocks (e.g., the identifiers of the used data blocks, the total number of used data blocks, the VPCs in the used data blocks, etc.), the records of the unused data blocks, etc. For example, the first data block may be marked as an unused data block after being erased. If the second data block is an empty data block before being programmed with the data previously stored in the valid page set of the first data block, the second data block may be marked as a used data block. The VPC associated with the second data block may also be updated. In some embodiments, the erase of the first data block and the update of various records may be part of the GC process. In some other embodiments, the erase of the first data block and the update of various records are not included in the GC process, and the erase of the first data block and the update of various records may be performed after the GC process is completed. The following refers to Figures 6A - 6B and Figures 7A - 7C illustrates an example of updating the record of the used data block.

[0089] Method 500 proceeds to operation 510, as Figure 5As shown in [Figure], in operation 510, it is determined whether a GC termination condition is satisfied. In response to the GC termination condition being satisfied, the GC process can be terminated. Otherwise, method 500 returns to operation 508.

[0090] In some embodiments, the memory controller 300 can determine whether the total number of used data blocks is less than or equal to the total number of expected used data blocks. In response to the total number of used data blocks being less than or equal to the total number of expected used data blocks (e.g., the total number of used data blocks ≤ the total number of expected used data blocks), the memory controller 300 can determine that the GC termination condition is satisfied. Alternatively or additionally, the memory controller 300 can determine the VPCs respectively associated with the used data blocks in the user data storage space of the memory device. The memory controller 300 can determine whether the minimum VPC among the VPCs is greater than the VPC threshold. In response to the minimum VPC being greater than the VPC threshold (e.g., the minimum VPC > the VPC threshold), the memory controller 300 can determine that the GC termination condition is satisfied.

[0091] Method 500 proceeds to operation 512, as Figure 5 shown, in operation 512, the GC process can be terminated.

[0092] Figures 6A - 6B An exemplary process 600 for operating a memory controller and a memory device in accordance with some aspects of the present disclosure is shown. The memory controller can be any suitable memory controller disclosed herein, such as memory controller 300. The memory controller can be operatively coupled to a non-volatile memory device (e.g., memory device 302) and control the operation of the memory device 302. By way of example, the following is described with reference to memory controller 300 and memory device 302 Figures 6A - 6B , without loss of generality. It should be understood that the operations shown in process 600 may not be exhaustive, and other operations may also be performed before, after, or between any of the shown operations. Additionally, some of these operations can be performed simultaneously, or in an order different from the Figures 6A - 6B order shown.

[0093] Referring to Figure 6A , at operation 604, the memory controller 300 can determine the total number of used data blocks in the user data storage space of the memory device 302.

[0094] At operation 606, the memory controller 300 can determine whether a GC trigger condition is satisfied. In response to the GC trigger condition being satisfied, process 600 can proceed to operation 608. Otherwise, process 600 can return to operation 604.

[0095] At operation 608, the memory controller 300 may determine the VPCs respectively associated with the used data blocks.

[0096] At operation 610, the memory controller 300 may select a first data block having the smallest VPC among the VPCs from the used data blocks.

[0097] At operation 612, the memory controller 300 may generate a read command to instruct the memory device 302 to read the data stored in the valid page set from the first data block.

[0098] At operation 614, the memory controller 300 may send the read command to the memory device 302.

[0099] At operation 616, the memory device 302 may read the data stored in the valid page set from the first data block.

[0100] At operation 618, the memory device 302 may send the data stored in the valid page set of the first data block to the memory controller 300.

[0101] At operation 620, the memory controller 300 may generate a program command to instruct the memory device 302 to program the data previously stored in the valid page set of the first data block into a second data block.

[0102] At operation 622, the memory controller 300 may send the program command and the data previously stored in the valid page set of the first data block to the memory device 302.

[0103] At operation 624, the memory device 302 may program the data previously stored in the valid page set of the first data block into the second data block.

[0104] Reference Figure 6B At operation 626, the memory controller 300 may generate an erase command to instruct the memory device 302 to erase all the data (e.g., including valid data and invalid data) stored in the first data block.

[0105] At operation 628, the memory controller 300 may send the erase command to the memory device 302.

[0106] At operation 630, the memory device 302 may erase all the data stored in the first data block.

[0107] At operation 632, the memory controller 300 may update a record of used data blocks in the memory device 302 (e.g., the total number of used data blocks). For example, assume that before programming data previously stored in a set of valid pages of a first data block into a second data block, the second data block is an empty data block. The memory controller 300 may update the first data block from a used data block to an empty data block. The memory controller 300 may also update the second data block from an empty data block to a used data block. The memory controller 300 may further update the VPC in the second data block. In another example, assume that before programming data previously stored in a set of valid pages of a first data block into a second data block, the second data block is a used data block. In this case, the memory controller 300 may (1) update the first data block from a used data block to an empty data block and (2) update the VPC in the second data block.

[0108] At operation 634, the memory controller 300 may determine whether a GC termination condition is satisfied. In response to the GC termination condition being satisfied, process 600 may proceed to operation 636. Otherwise, the memory controller 300 may return to operation 608.

[0109] At operation 636, the memory controller 300 may terminate the GC process.

[0110] Figures 7A - 7C An exemplary GC process in accordance with some aspects of the present disclosure is shown. In Figures 7A - 7C , a first data block (Data Block 1) and a second data block (Data Block 2) are shown. Each data block includes nine pages (from Page A to Page I). In Figure 7A , there are four valid pages (A, B, C, and D) and five empty pages (E, F, G, H, and I) in the first data block, and the VPC in the first data block may be updated to a total of 4 valid pages. As Figure 7A shown, all pages in the second data block are empty pages. It is contemplated that the second data block may also include one or more valid pages, which is not limited herein.

[0111] Referring to Figure 7B, four pages (A, B, C, and D) in the first data block change from valid pages to invalid pages. For example, a host (e.g., host 108) may instruct a memory controller (e.g., memory controller 300) to delete the data stored in the four pages (A, B, C, and D) of the first data block. In this case, the memory controller 300 may mark the four pages (A, B, C, and D) of the first data block as invalid pages. Additionally, the host 108 may instruct the memory controller 300 to store a new data set. The memory controller 300 may allocate three empty pages (e.g., E, F, and G) in the first data block to store the new data set. Then, in the first data block, the three pages E, F, and G storing the new data set change from empty pages to valid pages. The VPC in the first data block may be updated to a total of 3 valid pages.

[0112] In Figure 7C , a GC process is performed to free the first data block as an empty data block. For example, the data stored in the three valid pages E, F, and G of the first data block (as shown in Figure 7B ) is copied to three empty pages (e.g., pages A, B, and C, or any other empty pages) of the second data block. Then, all the data stored in the first data block (e.g., the data stored in pages A - G of the first data block) can be erased. The first data block can change from the used data block shown in Figures 7A - 7B to the empty data block shown in Figure 7C . For example, if the second data block is an empty data block before copying the data stored in the valid pages of the first data block, the second data block changes from an empty data block to a used data block. The VPC in the second data block may be updated to a total of 3 valid pages.

[0113] Figures 8 - 9 shows exemplary simulation results of the GC scheme applying the degree of logical saturation disclosed herein according to some aspects of the present disclosure. In Figure 8 , the x - axis represents the degree of logical saturation. Figure 8 depicts a curve that represents the ratio of the total number of virtual blocks expected to be used to the size of the user data storage space varying with the degree of logical saturation. T1 and T2 may represent the first saturation threshold and the second saturation threshold, respectively.

[0114] Figure 9 shows exemplary performance of the GC scheme applying the degree of logical saturation disclosed herein. This performance is simulated in a dirty disk scenario with severe file fragmentation in a memory device. In each used virtual block of the memory device, the ratio of the VPC of the virtual block to the total number of pages in the virtual block is equal to the degree of logical saturation. In Figure 9In it, the x-axis represents the degree of logical saturation, and the y-axis represents the number of free virtual blocks after the execution of the GC process. The first curve 902 can indicate the change in the number of free virtual blocks with the degree of logical saturation when the GC scheme disclosed herein is applied. The second curve 904 can indicate the change in the number of free virtual blocks when another GC scheme (without applying the degree of logical saturation) is applied. By comparing the first curve 902 and the second curve 904, it can be seen that the GC scheme disclosed herein can effectively increase the number of free virtual blocks in the dirty disk scenario, thereby enhancing the write performance of the memory device. The GC scheme disclosed herein can pass the aging test, so that even when the degree of logical saturation is greater than 95%, the performance degradation of the memory device can be less than 20%.

[0115] In various aspects of the present disclosure, the functions described herein can be implemented using hardware, software, firmware, or any combination thereof. If the functions are implemented using software, these functions can be stored as instructions on a non-transitory computer-readable medium. The computer-readable medium includes computer storage media. The storage media can be any available medium accessible by a memory controller (e.g., Figure 3A the memory controller 300 in [].) By way of example and not limitation, such computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), read-only optical disc memory (CD-ROM), or other optical disc storage devices, hard disk drives (HDDs) (e.g., magnetic disk storage devices or other magnetic storage devices), flash drives, SSDs, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a processing system (e.g., a mobile device or a computer). As used herein, disk and optical disc include CD, laser disc, optical disc, digital video disc (DVD), and floppy disk, where disks typically reproduce data magnetically, while optical discs reproduce data optically with a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0116] The description of the foregoing specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, these adjustments and modifications are intended to fall within the meaning and scope of the equivalent solutions of the disclosed embodiments.

[0117] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only by the appended claims and their equivalents.

[0118] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. Additionally, the subject matter described in the present disclosure may be used in a variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of the present disclosure.

Claims

1. A method for operating a memory controller, comprising: Determining a total usage amount of a user data storage space of a memory device; Determining whether a garbage collection (GC) trigger condition is satisfied based on the total usage amount of the user data storage space; And Determining whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied.

2. The method according to claim 1, wherein, The total usage amount of the user data storage space includes the total number of used data blocks in the user data storage space.

3. The method according to claim 2, wherein, Determining whether the GC trigger condition is satisfied includes: Determining a total number of data blocks expected to be used in the user data storage space; and Determining whether the GC trigger condition is satisfied based on the total number of the used data blocks and the total number of the data blocks expected to be used.

4. The method according to claim 3, wherein: The total number of the used data blocks includes the total number of virtual blocks that have been used in the user data storage space; and The total number of the data blocks expected to be used includes the total number of virtual blocks expected to be used in the user data storage space.

5. The method according to claim 3 or 4, wherein, Determining whether the GC trigger condition is satisfied includes: Determining whether the total number of the used data blocks is greater than the total number of the data blocks expected to be used.

6. The method according to claim 5, further comprising: Determining that the GC trigger condition is satisfied in response to the total number of the used data blocks being greater than the total number of the data blocks expected to be used; Or Determining that the GC trigger condition is not satisfied in response to the total number of the used data blocks being less than or equal to the total number of the data blocks expected to be used.

7. The method according to claim 5, wherein, Determining whether the GC trigger condition is satisfied further includes: Determining valid page counts (VPCs) respectively associated with the used data blocks in the user data storage space; and Determining whether the minimum VPC among the VPCs is not greater than a VPC threshold.

8. The method according to claim 7, further comprising: Determining that the GC trigger condition is satisfied in response to the total number of the used data blocks being greater than the total number of the data blocks expected to be used and the minimum VPC not being greater than the VPC threshold; or Determining that the GC trigger condition is not satisfied in response to the total number of the used data blocks not being greater than the total number of the data blocks expected to be used or the minimum VPC being greater than the VPC threshold.

9. The method according to any one of claims 3 - 8, wherein, Determining the total number of the data blocks expected to be used includes: Determining a logical saturation degree of the memory device as a ratio between a total size of valid data in the user data storage space and a size of the user data storage space; and Determining the total number of the data blocks expected to be used based on the logical saturation degree.

10. The method according to claim 9, wherein, The total size of the valid data in the user data storage space includes the total number of valid pages in the user data storage space.

11. The method according to claim 9 or 10, wherein, Determining the total number of the data blocks expected to be used based on the logical saturation degree includes: Determining the total number of the data blocks expected to be used as a predetermined fixed value in response to the logical saturation degree not being greater than a first saturation threshold.

12. The method according to claim 11, wherein, Determining the total number of the data blocks to be expected to be used based on the logical saturation degree further includes: In response to the logical saturation degree being not less than a second saturation threshold, determining the total number of the data blocks to be expected to be used as a first saturation variable having a linear relationship with the logical saturation degree.

13. The method according to claim 12, wherein, Determining the total number of the data blocks to be expected to be used based on the logical saturation degree further includes: In response to the logical saturation degree being greater than the first saturation threshold and less than the second saturation threshold, When the logical saturation degree is equal to the second saturation threshold, determining a first value of the first saturation variable; Determining a second saturation variable having a non-linear relationship with the logical saturation degree; and Determining the total number of the data blocks to be expected to be used as the minimum of the following: the first value of the first saturation variable, and the second saturation variable.

14. The method according to any one of claims 3-6, wherein, The GC process is a background GC process, and determining whether to perform the GC process on the memory device includes: In response to satisfying the GC trigger condition, performing the GC process on the memory device by: Determining valid page counts (VPCs) respectively associated with the used data blocks in the user data storage space; Selecting a first data block having the minimum VPC among the VPCs from the used data blocks; Generating and sending a read command to instruct the memory device to read the data stored in the valid page set from the first data block; Receiving the data stored in the valid page set from the first data block of the memory device; and Generating and sending a program command to instruct the memory device to program the data stored in the valid page set to a second data block in the user data storage space.

15. The method according to claim 14, further including: Generating and sending an erase command to instruct the memory device to erase the data stored in the first data block; And Updating the total number of the used data blocks.

16. The method according to claim 14 or 15, further including: Determining whether a GC termination condition is satisfied; And In response to the GC termination condition being satisfied, terminating the GC process.

17. The method according to claim 16, wherein Determining whether the GC termination condition is satisfied includes: Determining whether the total number of the used data blocks is less than or equal to the total number of the data blocks to be expected to be used; and In response to the total number of the used data blocks being less than or equal to the total number of the data blocks to be expected to be used, determining that the GC termination condition is satisfied.

18. The method according to claim 16, wherein, Determining whether the GC termination condition is satisfied includes: Determining valid page counts (VPCs) respectively associated with the used data blocks in the user data storage space; Determining whether the minimum VPC among the VPCs is greater than a VPC threshold; and In response to the minimum VPC being greater than the VPC threshold, determining that the GC termination condition is satisfied.

19. The method according to any one of claims 2-18, wherein, Extracting the total number of the used data blocks from the memory controller.

20. The method according to any one of claims 1-19, wherein The memory device includes a NAND flash memory.

21. A memory controller, comprising: A memory configured to store instructions; And A processor coupled to the memory and configured to execute the instructions to perform a process including the following: Determine the total usage of the user data storage space of the memory device; Based on the total usage of the user data storage space, determine whether a garbage collection (GC) trigger condition is satisfied; And Based on whether the GC trigger condition is satisfied, determine whether to perform a GC process on the memory device.

22. The memory controller according to claim 21, wherein: The total usage of the user data storage space includes the total number of used data blocks in the user data storage space; And Determining whether the GC trigger condition is satisfied includes: Determine the total number of data blocks expected to be used in the user data storage space; And Based on the total number of the used data blocks and the total number of the data blocks expected to be used, determine whether the GC trigger condition is satisfied.

23. The memory controller according to claim 22, wherein, Determining whether the GC trigger condition is satisfied includes: Determine whether the total number of the used data blocks is greater than the total number of the data blocks expected to be used.

24. The memory controller according to claim 23, wherein, Determining whether the GC trigger condition is satisfied further includes: Determine the valid page count (VPC) associated with the used data blocks in the user data storage space respectively; and Determine whether the minimum VPC among the VPCs is not greater than the VPC threshold.

25. The memory controller according to claim 24, wherein, The process further includes: In response to the total number of the used data blocks being greater than the total number of the data blocks expected to be used and the minimum VPC not being greater than the VPC threshold, determine that the GC trigger condition is satisfied; or In response to the total number of the used data blocks not being greater than the total number of the data blocks expected to be used or the minimum VPC being greater than the VPC threshold, determine that the GC trigger condition is not satisfied.

26. The memory controller according to any one of claims 22-25, wherein, Determining the total number of the data blocks expected to be used includes: Determine the logical saturation level of the memory device as the ratio between the total size of the valid data in the user data storage space and the size of the user data storage space; and Based on the logical saturation level, determine the total number of the data blocks expected to be used.

27. A memory system, comprising: A memory device; And A memory controller operably coupled to the memory device and configured to: Determine the total usage of the user data storage space of the memory device; Based on the total usage of the user data storage space, determine whether a garbage collection (GC) trigger condition is satisfied; And Based on whether the GC trigger condition is satisfied, determine whether to perform a GC process on the memory device.

28. The memory system according to claim 27, wherein: The total usage of the user data storage space includes the total number of used data blocks in the user data storage space; and To determine whether the GC trigger condition is satisfied, the memory controller is configured to: Determine the total number of data blocks expected to be used in the user data storage space; And Determine whether the GC trigger condition is satisfied based on the total number of the used data blocks and the total number of the data blocks expected to be used.

29. The memory system according to claim 28, wherein, To determine whether the GC trigger condition is satisfied, the memory controller is configured to: determine whether the total number of the used data blocks is greater than the total number of the data blocks expected to be used.

30. The memory system according to claim 29, wherein, To determine whether the GC trigger condition is satisfied, the memory controller is further configured to: determine the valid page count (VPC) respectively associated with the used data blocks in the user data storage space; and determine whether the minimum VPC among the VPCs is not greater than the VPC threshold.

31. The memory system according to any one of claims 28 - 30, wherein, To determine the total number of the data blocks expected to be used, the memory controller is configured to: determine the logical saturation degree of the memory device as the ratio between the total size of the valid data in the user data storage space and the size of the user data storage space; and determine the total number of the data blocks expected to be used based on the logical saturation degree.

32. A non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform a method including each of the following: Determine the total usage amount of the user data storage space of a memory device; Determine whether a garbage collection (GC) trigger condition is satisfied based on the total usage amount of the user data storage space; and Determine whether to perform a GC process on the memory device based on whether the GC trigger condition is satisfied.

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