Display panel, driving method thereof and electronic paper
By dividing the pixel matrix of vertical screen electronic paper into sub-pixel matrix and designing the layout of gate lines and data lines, the problem of increasing power consumption of parasitic capacitance and resistive capacitance load caused by source traces across a large number of gate traces is solved, simplifying the process flow and reducing manufacturing costs.
Patent Information
- Application Number
- CN202510662524.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-22
- Publication Date
- 2025-07-08
AI Technical Summary
In the panel design of vertical screen electronic paper, the source trace crosses a large number of gate traces, resulting in increased power consumption of parasitic capacitors and resistor capacitance loads, voltage drop, and the need to add a mask as a signal transition layer, resulting in complex process and excessive manufacturing costs.
The pixel matrix is divided into a plurality of sub-pixel matrices. Each sub-pixel matrix includes at least two pixel rows. The gate lines extend in the row direction and are connected to each other. The data lines extend in the column direction. Multiple pixels in the same column are simultaneously controlled through multiple data lines, reducing the data lines cross gate lines, reducing the number of thin film transistors, and avoiding increasing signal conversion layers.
Reduces the power consumption of parasitic capacitors and resistive capacitance loads, avoids voltage drop, simplifies process flow, and reduces manufacturing costs.
Smart Images
Figure CN120279855A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic paper, and in particular, to a display panel, a driving method thereof, and an electronic paper. Background Art
[0002] Currently, in the applications of electronic paper and readers, portrait display is usually the main mode. When in portrait display, the driving IC in landscape mode is usually placed on the short side of the portrait screen body. For example, Figure 1 is the wiring design diagram of a portrait electronic paper in the prior art, as Figure 1 shown. This design has the following problems: Structural limitations of the driving IC: As shown by the driving IC on the right side of Figure 1 , the gate output interfaces (Gate output pins) are concentrated at both ends of the driving IC, and the source output interfaces (Source output pins) are distributed in the middle of the driving IC. In this way, when routing on the screen body, the source line has to cross a large number of gate lines, resulting in an increase in parasitic capacitance and the power consumption of the RC loading, and further leading to problems such as voltage drop; Scanning timing limitations of the electronic paper: Figure 1 In Figure 2 , the driving IC channels are 800 (S) × 600 (G). Due to the scanning timing limitations of the gate and source, the scanning interface sequence needs to be swapped. Therefore, an additional mask is required as a signal conversion layer, as shown in
[0003] . This design has a complex process and a high manufacturing cost. Therefore, how to solve the problems that when designing the panel of a portrait electronic paper, the source line has to cross a large number of gate lines, resulting in an increase in parasitic capacitance and the power consumption of the RC loading, voltage drop, etc., and the problems of complex process and high manufacturing cost caused by the need to add an additional mask as a signal conversion layer have become urgent problems to be solved currently. Summary of the Invention
[0004] In an embodiment of the present invention, a display panel is proposed to solve the problems that when designing the panel of a portrait electronic paper, the source line has to cross a large number of gate lines, resulting in an increase in parasitic capacitance and the power consumption of the RC loading, voltage drop, etc., and the problems of complex process and high manufacturing cost caused by the need to add an additional mask as a signal conversion layer; the display panel includes: A pixel matrix, which is divided into a plurality of sub-pixel matrices, and each sub-pixel matrix includes at least two pixel rows; Multiple gate lines, each gate line including at least two sub - gate lines, each sub - gate line extending along the row direction, all sub - gate lines in each gate line being interconnected, and one of the sub - gate lines serving as a main line leading to the left or right side of the pixel matrix; Multiple data lines, extending along the column direction; The first control terminals of all pixels in each sub - pixel matrix are connected to the same gate line, wherein the first control terminals of all pixels in each pixel row of each sub - pixel matrix are connected to one of the sub - gate lines of the same gate line; The second control terminals of all pixels in the same row and the same column in each sub - pixel matrix are connected to the same data line.
[0005] In one embodiment, for every two adjacent gate lines, their main lines are respectively led to different sides of the pixel matrix.
[0006] In one embodiment, the display panel further includes a driving IC; the driving IC includes a first gate output interface, a second gate output interface, and a data output interface; Connect multiple gate lines on one side of the pixel matrix to the first gate output interface through their respective leads, and connect multiple gate lines on the other side of the pixel matrix to the second gate output interface through their respective leads; Each data line is connected to the data output interface.
[0007] In one embodiment, each pixel includes a first thin - film transistor, a second thin - film transistor, and a pixel capacitor. The drain of the first thin - film transistor is connected to the source of the second thin - film transistor. The source of the first thin - film transistor is connected to the second control terminal of each pixel. The drain of the second thin - film transistor is connected to the first end of the pixel capacitor, and the second end of the pixel capacitor is grounded.
[0008] In one embodiment, the gates of the first thin - film transistor and the second thin - film transistor of each pixel are both connected to the first control terminal of the pixel.
[0009] In one embodiment, in the pixel matrix, the number of pixels in each row direction is less than the number of pixels in the column direction.
[0010] An embodiment of the present invention further provides a driving method, which is applied to the above - mentioned display panel. The driving method includes: Driving all pixels in at least two pixel rows connected to the same gate line to display or turn off simultaneously through one gate line.
[0011] An embodiment of the present invention further provides an electronic paper, including: the above - mentioned display panel.
[0012] In one embodiment, the electronic paper is a portrait - mode electronic paper.
[0013] The display panel provided by the embodiment of the present invention includes: a pixel matrix, which is divided into multiple sub-pixel matrices, and each sub-pixel matrix includes at least two pixel rows; multiple gate lines, each gate line includes at least two sub-gate lines, each sub-gate line extends in the row direction, and all the sub-gate lines in each gate line are connected to each other, and one of the sub-gate lines serves as a main line and leads to the left or right side of the pixel matrix; multiple data lines, extending in the column direction; the first control ends of all the pixels in each sub-pixel matrix are connected to the same gate line, wherein the first control ends of all the pixels in each pixel row in each sub-pixel matrix are connected to one of the sub-gate lines of the same gate line; the second control ends of the pixels that are in the same pixel column in the pixel matrix and are in the same order of pixel rows in each sub-pixel matrix are connected to the same data line. Compared with the prior art, in the embodiment of the present invention, by designing the gate lines to extend in the row direction and the data lines to extend in the column direction, one gate line controls the simultaneous display of multiple rows of pixels, and multiple pixels in the same column are simultaneously controlled by multiple data lines. In this way, it is possible to avoid the data lines crossing a large number of gate lines, and the number of data lines is increased by at least half, so that the number of thin film transistors on one data line is reduced, which is beneficial to reducing the parasitic capacitance and the power consumption of the resistance-capacitance load, and avoiding the drop of the working voltage; in addition, without adding an additional mask as a signal conversion layer, the problem of signal conversion between different signal layers can be solved, and thus the process complexity can be reduced and the manufacturing cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0015] In the drawings: Figure 1 is the wiring design diagram of the vertical screen e-paper in the prior art; Figure 2 is the signal conversion layer design schematic diagram of the driving IC of the vertical screen e-paper in the prior art; Figure 3 is the design schematic diagram of a display panel provided by the embodiment of the present invention; Figure 4 is the design schematic diagram of another display panel provided by the embodiment of the present invention; Figure 5 is the design schematic diagram of another display panel provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention in conjunction with the accompanying drawings. Herein, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.
[0017] In the description of this specification, the terms "comprising", "including", "having", "containing", etc. are all open-ended terms, meaning including but not limited to. The description with reference to terms such as "one embodiment", "one specific embodiment", "some embodiments", "for example", etc. means that the specific features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. The order of steps involved in each embodiment is used to schematically illustrate the implementation of this application, and the order of steps is not limited and can be adjusted appropriately as needed.
[0018] It has been found through research that in the prior art, when designing the panel of a vertical screen e-paper, the source electrode traces need to cross a large number of gate electrode traces, resulting in problems such as increased parasitic capacitance, increased power consumption of the resistance-capacitance load, voltage drop, etc., and problems such as complex process and high manufacturing cost due to the need to add a mask as a signal conversion layer.
[0019] Based on this, the present invention provides a display panel that can solve the above problems.
[0020] Embodiment 1 Figure 3 This is a design schematic diagram of a display panel provided in an embodiment of the present invention. As Figure 3 shown, the display panel includes a pixel matrix, and the pixel matrix includes a plurality of pixels px arranged in rows and columns; a plurality of gate lines G0, G1,...; a plurality of data lines S0, S1,..., Sn-1, Sn.
[0021] Among them, the pixel matrix is divided into a plurality of sub-pixel matrices 1, 2,... (only sub-pixel matrices 1 and 2 are shown in the figure) based on rows. Each sub-pixel matrix 1 includes two pixel rows. That is to say, every two rows of pixels in the pixel matrix form a sub-pixel matrix.
[0022] Each gate line includes two sub-gate lines. Each sub-gate line extends along the row direction, and all the sub-gate lines in each gate line are connected to each other. One of the sub-gate lines serves as the main line and leads to the left or right side of the pixel matrix. For example, as Figure 3As shown, the gate line G0 includes sub-gate lines G00 and G01, G00 and G01 are connected to each other, and G00 is led out as the main line on the left side of the pixel matrix; the gate line G1 includes sub-gate lines G10 and G11, G10 and G11 are connected to each other, and G11 is led out as the main line on the right side of the pixel matrix.
[0023] Each data line extends along a column direction.
[0024] The first control terminals of all pixels in each sub-pixel matrix are connected to the same gate line, wherein the first control terminals of all pixels in each pixel row in each sub-pixel matrix are connected to one of the sub-gate lines of the same gate line. Figure 3 As shown, the sub-pixel matrix 1 includes a first pixel row (the first row of pixels in the sub-pixel matrix 1) and a second pixel row (the second row of pixels in the sub-pixel matrix 1), the first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G00 of the gate line G0, and the first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G01 of the gate line G0; the sub-pixel matrix 2 also includes a first pixel row and a second pixel row, the first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G10 of the gate line G1, and the first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G11 of the gate line G1. In this way, since a plurality of sub-gate lines are connected to each other, one gate line can control the display of two rows of pixels at the same time.
[0025] The second control terminals of all pixels in the same row and column in each sub-pixel matrix are connected to the same data line. Figure 3 As shown, the second control terminals 12 of the pixels in the first row and first column of the sub-pixel matrix 1 and the pixels in the first row and first column of the sub-pixel matrix 2 are connected to the same data line S0; the second control terminals 12 of the pixels in the second row and first column of the sub-pixel matrix 1 and the pixels in the second row and first column of the sub-pixel matrix 2 are connected to the same data line S1; the second control terminals 12 of the pixels in the first row and second column of the sub-pixel matrix 1 and the pixels in the first row and second column of the sub-pixel matrix 2 are connected to the same data line S2, and the connections of the pixels in other rows and columns are similar. In this way, a column of pixels in the pixel matrix can be controlled by two data lines.
[0026] Specifically, taking a screen with a resolution of 272S×792G as an example, Figure 3The panel design method shown has the number of data lines and gate lines changed from the original 272S×792G to 544S×396G. One gate line controls the display of two rows of pixels on the same side. Since it is necessary to ensure that the display of the two rows of pixels controlled by this gate line is completed before turning off for the next row scan, in this way, the opening time of two rows of pixels controlled by one gate line during driving display is twice that of one gate line controlling one row of pixels (single gate). Therefore, the charging time for pixels is also twice that of single gate; moreover, the pixels in the same column are controlled by two data lines simultaneously. In this way, the number of thin-film transistors on one data line is reduced, which is beneficial to reducing parasitic capacitance and the power consumption of the resistance-capacitance load, and avoiding voltage drop; in addition, when designing the lower border, the cross-wiring of data lines and gate lines can be avoided, which can reduce the problem of layer transfer between different signal layers, and thus can reduce the process complexity and manufacturing cost.
[0027] In one embodiment, for every two adjacent gate lines, their main lines are respectively led to different sides of the pixel matrix. That is to say, the main line of gate line G0 is led to the left side of the pixel matrix, the main line of gate line G1 is led to the right side of the pixel matrix, the main line of gate line G2 is led to the left side of the pixel matrix, and so on.
[0028] In one embodiment, the display panel may further include a driving IC; the driving IC includes a first gate output interface, a second gate output interface, and a data output interface; Connect multiple gate lines on one side of the pixel matrix to the first gate output interface through their respective leads, and connect multiple gate lines on the other side of the pixel matrix to the second gate output interface through their respective leads; Each data line is connected to the data output interface.
[0029] In one embodiment, the driving IC can be disposed below the pixel matrix.
[0030] During specific implementation, the first gate output interface can be located on the left side of the driving IC, the second gate output interface is located on the right side of the driving IC, and the data output interface is located in the middle of the first gate output interface and the second gate output interface. In this way, since the gate lines extend in the row direction and the data lines extend in the column direction, the gate lines on the left side can be connected to the first gate output interface on the left side, and the gate lines on the right side can be connected to the second gate output interface on the right side; the data lines can be directly connected downward to the data output interface located in the middle of the driving IC. Furthermore, when designing the lower border of the screen body, the cross-wiring of gate lines and source lines can be avoided, reducing the problem of layer transfer between different signal layers, reducing the mask design cost, and reducing the design complexity.
[0031] In one embodiment, each pixel px includes a first thin film transistor TFT1, a second thin film transistor TFT2, and pixel capacitors Cfpl and Cst. The drain of the first thin film transistor TFT1 is connected to the source of the second thin film transistor TFT2. The source of the first thin film transistor TFT1 is connected to the second control terminal 12 of each pixel. The drain of the second thin film transistor TFT2 is connected to the first ends of the pixel capacitors Cfpl and Cst, and the second ends of the pixel capacitors Cfpl and Cst are grounded to Vcom.
[0032] In one embodiment, the gates of the first thin film transistor TFT1 and the second thin film transistor TFT2 of each pixel are both connected to the first control terminal 11 of the pixel.
[0033] In this way, through two thin film transistors and pixel capacitors, the charging and discharging of the pixel can be better realized, and the display effect can be improved.
[0034] In one embodiment, since the display panel is a vertically used screen body, in the pixel matrix, the number of pixels in each row direction is less than the number of pixels in the column direction.
[0035] Embodiment 2 Figure 4 This is a schematic design diagram of another display panel provided in the embodiment of the present invention. This embodiment is basically the same as Embodiment 1, except that each sub-pixel matrix 1 of the display panel in this embodiment includes three pixel rows; each gate line includes three sub-gate lines. During specific implementation, as Figure 5 shown, every three rows of pixels in the pixel matrix form a sub-pixel matrix. The sub-pixel matrix 1 includes a first pixel row (the first row of pixels in the sub-pixel matrix 1), a second pixel row (the second row of pixels in the sub-pixel matrix 1), and a third pixel row (the third row of pixels in the sub-pixel matrix 1). The first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G00 of the gate line G0. The first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G01 of the gate line G0. The first control terminals 11 of all pixels in the third pixel row are connected to the sub-gate line G02 of the gate line G0; the sub-pixel matrix 2 also includes a first pixel row and a second pixel row. The first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G10 of the gate line G1. The first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G11 of the gate line G1. The first control terminals 11 of all pixels in the third pixel row are connected to the sub-gate line G12 of the gate line G1. In this way, one gate line can control the display of three rows of pixels simultaneously.
[0036] The second control terminals of the pixels at the first row and first column of the sub-pixel matrix 1 and the pixels at the first row and first column of the sub-pixel matrix 2 are connected to the same data line S0; the second control terminals of the pixels at the second row and first column of the sub-pixel matrix 1 and the pixels at the second row and first column of the sub-pixel matrix 2 are connected to the same data line S1; the second control terminals of the pixels at the third row and first column of the sub-pixel matrix 1 and the pixels at the third row and first column of the sub-pixel matrix 2 are connected to the same data line S2; and so on for the pixels in other rows and columns. In this way, a column of pixels in the pixel matrix can be controlled by three data lines.
[0037] Specifically, taking a screen with a resolution of 800S×600G as an example, by using the panel design method described in the embodiments of the present invention, the number of data lines and gate lines is changed from the original 800S×600G to 266S×1800G. One gate line controls the display of three rows of pixels on the same side. Since it is necessary to ensure that all three rows of pixels controlled by this gate line are completely displayed before turning off for the next row scan, in this way, the opening time of one gate line controlling three rows of pixels during driving display is 3 times the opening time of one gate line controlling one row of pixels (single gate). Therefore, the charging time for pixels is also 3 times that of single gate; moreover, the pixels in the same column are simultaneously controlled by three data lines. In this way, the number of thin-film transistors on one data line is further reduced, which is beneficial to reducing parasitic capacitance and the power consumption of the resistance-capacitance load and avoiding voltage drop; in addition, when designing the lower border, the problem of layer transfer between different signal layers can be reduced, thereby reducing the process complexity and manufacturing cost.
[0038] Embodiment III Figure 5 It is a schematic design diagram of another display panel provided in the embodiments of the present invention. This embodiment is basically the same as Embodiment I, except that each sub-pixel matrix 1 of the display panel in this embodiment includes four pixel rows; each gate line includes four sub-gate lines. During specific implementation, as Figure 5As shown, every four rows of pixels in the pixel matrix form a sub-pixel matrix. The sub-pixel matrix 1 includes the first pixel row (the first row of pixels in the sub-pixel matrix 1), the second pixel row (the second row of pixels in the sub-pixel matrix 1), the third pixel row (the third row of pixels in the sub-pixel matrix 1), and the fourth pixel row (the fourth row of pixels in the sub-pixel matrix 1). The first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G00 of the gate line G0, the first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G01 of the gate line G0, the first control terminals 11 of all pixels in the third pixel row are connected to the sub-gate line G02 of the gate line G0, and the first control terminals 11 of all pixels in the fourth pixel row are connected to the sub-gate line G03 of the gate line G0; the sub-pixel matrix 2 also includes the first pixel row and the second pixel row. The first control terminals 11 of all pixels in the first pixel row are connected to the sub-gate line G10 of the gate line G1, the first control terminals 11 of all pixels in the second pixel row are connected to the sub-gate line G11 of the gate line G1, the first control terminals 11 of all pixels in the third pixel row are connected to the sub-gate line G12 of the gate line G1, and the first control terminals 11 of all pixels in the fourth pixel row are connected to the sub-gate line G13 of the gate line G1. In this way, one gate line can control the display of four rows of pixels simultaneously.
[0039] The second control terminals of the pixel at the first row and first column of the sub-pixel matrix 1 and the pixel at the first row and first column of the sub-pixel matrix 2 are connected to the same data line S0; the second control terminals of the pixel at the second row and first column of the sub-pixel matrix 1 and the pixel at the second row and first column of the sub-pixel matrix 2 are connected to the same data line S1; the second control terminals of the pixel at the third row and third column of the sub-pixel matrix 1 and the pixel at the third row and first column of the sub-pixel matrix 2 are connected to the same data line S2; the second control terminals of the pixel at the fourth row and first column of the sub-pixel matrix 1 and the pixel at the fourth row and first column of the sub-pixel matrix 2 are connected to the same data line S3; and so on for the pixels in other rows and columns. In this way, a column of pixels in the pixel matrix can be controlled by four data lines.
[0040] Specifically, taking a screen with a resolution of 800S×600G as an example, by using the panel design method described in the embodiments of the present invention, the number of data lines and gate lines is changed from the original 800S×600G to 200S×2400G. One gate line controls the display of four pixel rows on the same side. Since it is necessary to ensure that all four pixel rows controlled by this gate line are completely displayed before turning off for the next row scan, in this way, the opening time of one gate line controlling four pixel rows during driving display is 4 times that of one gate line controlling one pixel row (single gate). Therefore, the charging time for pixels is also 4 times that of single gate; moreover, the pixels in the same column are controlled by four data lines simultaneously. In this way, the number of thin-film transistors on one data line is further reduced, which is beneficial to reducing the parasitic capacitance and the power consumption of the resistance-capacitance load and avoiding voltage drop; in addition, when designing the lower border, the problem of layer conversion between different signal layers can be reduced, thereby reducing the process complexity and manufacturing cost.
[0041] In summary, the display panel provided by the embodiments of the present invention includes: a pixel matrix, which is divided into multiple sub-pixel matrices, and each sub-pixel matrix includes at least two pixel rows; multiple gate lines, each gate line includes at least two sub-gate lines, each sub-gate line extends along the row direction, and all sub-gate lines in each gate line are connected to each other, and one of the sub-gate lines is used as the main line to lead to the left or right side of the pixel matrix; multiple data lines, extending along the column direction; the first control ends of all pixels in each sub-pixel matrix are connected to the same gate line, wherein the first control ends of all pixels in each pixel row in each sub-pixel matrix are connected to one of the sub-gate lines of the same gate line; the second control ends of pixels that are in the same pixel column in the pixel matrix and have the same order of pixel rows in each sub-pixel matrix are connected to the same data line. Compared with the prior art, in the embodiments of the present invention, by designing the gate lines to extend along the row direction and the data lines to extend along the column direction, one gate line controls the simultaneous display of multiple pixel rows, and multiple pixels in the same column are controlled by multiple data lines simultaneously. In this way, it is possible to avoid a large number of gate lines crossed by the data lines, and the number of data lines is increased by at least half, so that the number of thin-film transistors on one data line is reduced, which is beneficial to reducing the parasitic capacitance and the power consumption of the resistance-capacitance load and avoiding voltage drop; in addition, without adding an extra mask for signal layer conversion, the problem of layer conversion between different signal layers can be solved, thereby reducing the process complexity and manufacturing cost.
[0042] The embodiments of the present invention also provide a driving method. Since this driving method is applied to the above display panel and the principle of solving problems is similar to that of the above display panel, the implementation of this driving method can refer to the implementation of the display panel, and the repeated parts will not be described again.
[0043] The method may include: Drive all the pixels in at least two pixel rows connected to the gate line to display or turn off simultaneously through a gate line.
[0044] An embodiment of the present invention further provides an electronic paper, and the electronic paper film includes the above display panel.
[0045] In one embodiment, the electronic paper is a portrait electronic paper.
[0046] The implementation of the above electronic paper can refer to the description of the above display panel, and no redundant description will be given here.
[0047] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A display panel, characterized in that, Comprising: A pixel matrix, which is divided into a plurality of sub-pixel matrices, and each sub-pixel matrix includes at least two pixel rows; A plurality of gate lines, each gate line includes at least two sub-gate lines, each sub-gate line extends along the row direction, all sub-gate lines in each gate line are connected to each other, and one of the sub-gate lines is used as a main line leading to the left or right side of the pixel matrix; A plurality of data lines, extending along the column direction; The first control terminals of all pixels in each sub-pixel matrix are connected to the same gate line, wherein the first control terminals of all pixels in each pixel row in each sub-pixel matrix are connected to one of the sub-gate lines of the same gate line; The second control terminals of all pixels in the same row and the same column in each sub-pixel matrix are connected to the same data line.
2. The display panel according to claim 1, wherein For every two adjacent gate lines, their main lines are respectively led to different sides of the pixel matrix.
3. The display panel according to claim 2, characterized in that The display panel further includes a driving IC; the driving IC includes a first gate output interface, a second gate output interface, and a data output interface; Connecting a plurality of gate lines on one side of the pixel matrix to the first gate output interface through their respective leads, and connecting a plurality of gate lines on the other side of the pixel matrix to the second gate output interface through their respective leads; Each data line is connected to the data output interface.
4. The display panel according to claim 1, characterized in that, Each pixel includes a first thin-film transistor, a second thin-film transistor, and a pixel capacitor. The drain of the first thin-film transistor is connected to the source of the second thin-film transistor. The source of the first thin-film transistor is connected to the second control terminal of each pixel. The drain of the second thin-film transistor is connected to the first end of the pixel capacitor, and the second end of the pixel capacitor is grounded.
5. The display panel according to claim 4, wherein The gates of the first thin-film transistor and the second thin-film transistor of each pixel are both connected to the first control terminal of the pixel.
6. The display panel according to claim 1, wherein In the pixel matrix, the number of pixels in each row direction is less than the number of pixels in the column direction.
7. A driving method, characterized in that, Applied to the display panel according to any one of claims 1-6, including: Driving all pixels in at least two pixel rows connected to the gate line to display or turn off simultaneously through one gate line.
8. An electronic paper, characterized in that, Comprising: The display panel according to any one of claims 1-6.
9. The electronic paper according to claim 8, characterized in that, The electronic paper is a vertical screen electronic paper.