Packaging method for forming heterogeneous chip and wafer packaging structure
By forming a conductive corrosion-resistant layer on the UBM layer, the corrosion problem of metal layer caused by bump processing is solved, the process flow is simplified and the reliability and conductivity of heterogeneous chips are improved.
Patent Information
- Application Number
- CN202510432116.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, when preparing heterogeneous chips, bump processing technology is prone to corrosion of the metal layer, affecting reliability, and existing corrosion protection solutions increase process complexity or affect conductivity.
The conductive corrosion-resistant layer is formed on the UBM layer to prevent chemical corrosion in the bump structure process, and electroplating on some pads to form bump structures, simplifying the process flow and improving chip reliability.
The process conflict is resolved through the conductive corrosion-resistant layer, the process flow is simplified, the reliability and conductivity of the chip are improved, and the formation of additional passivation layers is avoided.
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Figure CN120280349A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure belong to the technical field of semiconductor integrated circuits, and particularly relate to a packaging method for forming heterogeneous chips and a wafer packaging structure. Background Art
[0002] With the rapid development of semiconductor devices towards high performance, miniaturization, and heterogeneous integration, advanced packaging technologies have become an important breakthrough for continuing Moore's Law. Among them, Wafer-Level Packaging (WLP) and Flip-Chip technologies occupy a core position in three-dimensional integration and system-level packaging due to advantages such as shortening the interconnect path and increasing I / O density. As a key structure for flip-chip interconnection, the preparation process of bumps directly affects the interconnection reliability and packaging yield. Especially in the scenario of multi-chip heterogeneous integration, how to achieve compatible interconnection of different functional chips has become a technical difficulty in the industry.
[0003] In traditional processes, bump processing needs to be performed on some chips, while other chips may be corroded in the metal layer (Under Bump Metallization) due to exposure to bump processes (such as electroplating and etching), affecting reliability.
[0004] Existing anti-corrosion solutions (such as local passivation) may increase the process complexity or affect the conductivity of subsequent packaging interconnections. If the passivation material remains on the electrode surface, it will hinder the reliable contact between conductive particles and the electrode in subsequent flip-chip bonding.
[0005] In view of the above problems, it is necessary to propose a packaging method for forming heterogeneous chips and a wafer packaging structure that are reasonably designed and effectively solve the above problems. Summary of the Invention
[0006] Embodiments of the present disclosure aim to at least solve one of the technical problems existing in the prior art, and provide a packaging method for forming heterogeneous chips and a wafer packaging structure.
[0007] One aspect of the embodiments of the present disclosure provides a packaging method for forming heterogeneous chips, and the method includes:
[0008] Providing a wafer, wherein a plurality of pads and a passivation layer are disposed on a functional surface of the wafer;
[0009] Forming a UBM layer electrically connected to the pads on the passivation layer and the pads;
[0010] Electroplating a conductive anti-corrosion layer corresponding to the pads on the UBM layer;
[0011] Electroplating a bump structure on the conductive anti-corrosion layer corresponding to some of the pads;
[0012] The wafer is cut to form a plurality of first chips and a plurality of second chips. Among them, a conductive anti-corrosion layer and a bump structure are sequentially formed on the UBM layer of the first chip, and only the conductive anti-corrosion layer is formed on the UBM layer of the second chip.
[0013] Optionally, electroplating a conductive anti-corrosion layer on the UBM layer corresponding to the pad includes:
[0014] Form a first photoresist layer on the UBM layer;
[0015] Pattern the first photoresist layer to form a first opening in the first photoresist layer corresponding to the pad;
[0016] Electroplate the conductive anti-corrosion layer at the first opening;
[0017] Remove the remaining first photoresist layer.
[0018] Optionally, the conductive anti-corrosion layer is a gold plating layer, and the thickness range of the gold plating layer is 0.1μm to 1μm.
[0019] Optionally, electroplating a bump structure on the conductive anti-corrosion layer corresponding to some of the pads includes:
[0020] Form a second photoresist layer on all the conductive anti-corrosion layers and the UBM layer;
[0021] Pattern the second photoresist layer to form a second opening in the second photoresist layer corresponding to some of the conductive anti-corrosion layers;
[0022] Electroplate the bump structure at the second opening;
[0023] Remove the remaining second photoresist layer.
[0024] Optionally, forming the bump structure in the second opening by an electroplating process includes:
[0025] Electroplate a gold bump structure in the second opening by an electroplating process.
[0026] Optionally, the thickness range of the gold bump structure is 5μm to 18μm.
[0027] Optionally, before cutting the wafer, the method further includes:
[0028] Remove part of the UBM layer so that the remaining UBM layer is only connected to the conductive anti-corrosion layer.
[0029] Another aspect of the embodiments of the present disclosure provides a wafer packaging structure, the wafer
[0030] The packaging structure includes:
[0031] A wafer, on the functional surface of which there are a plurality of pads and a passivation layer;
[0032] A UBM layer, disposed on the pads and electrically connected to the pads;
[0033] A conductive anti-corrosion layer, disposed on the UBM layer;
[0034] A bump structure, disposed on the conductive anti-corrosion layer corresponding to some of the pads.
[0035] Optionally, the conductive anti-corrosion layer is a gold plating layer.
[0036] Optionally, the thickness range of the gold plating layer is 0.1 μm to 1 μm.
[0037] In the packaging method and wafer packaging structure for forming a heterogeneous chip according to the embodiments of the present disclosure, for the first time, a conductive anti-corrosion layer is formed on the UBM layer to prevent chemical corrosion in the subsequent process of forming the bump structure, and solve the process conflict problem when different chips coexist; the conductive anti-corrosion layer has both anti-corrosion and conductive functions, and the formed second chip does not need to form an additional passivation layer, which simplifies the process flow and improves the reliability of the chip; combining the Bump and COF conductive particle technologies, the conductive anti-corrosion layer is used to meet both the conductive requirements and the anti-corrosion requirements at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 is a schematic flow chart of a packaging method for forming a heterogeneous chip according to an embodiment in the embodiments of the present disclosure;
[0039] Figures 2 to 9 is a schematic process diagram of a packaging method for forming a heterogeneous chip according to another embodiment in the embodiments of the present disclosure;
[0040] Figure 10 is a schematic structural diagram of a wafer packaging structure according to another embodiment in the embodiments of the present disclosure. DETAILED DESCRIPTION
[0041] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following further describes the embodiments of the present disclosure in detail with reference to the drawings and specific embodiments.
[0042] As Figure 1 shown, one aspect of the embodiments of the present disclosure provides a packaging method S100 for forming a heterogeneous chip, and the packaging method S100 includes:
[0043] S110. Provide a wafer, where a plurality of pads and a passivation layer are provided on a functional surface of the wafer.
[0044] Specifically, as Figure 2 shown, provide a wafer 110, where a plurality of pads 111 and a passivation layer 112 are provided on a functional surface of the wafer 110.
[0045] S120. Form a UBM layer electrically connected to the pads on the passivation layer and the pads.
[0046] Specifically, as Figure 3 shown, form a UBM layer 120 on the entire functional surface of the wafer 110 through a sputtering process. Among them, the UBM layer 120 covers the passivation layer 112 and a plurality of pads 111 and is electrically connected to the pads 111. Among them, the UBM layer 120 can adopt a TiW layer or an Au layer.
[0047] In this embodiment, by forming a UBM layer on the functional surface of the wafer, an electroplating conductive foundation is provided, and the adhesion of the conductive anti-corrosion layer 140 is enhanced.
[0048] S130. Electroplate and form a conductive anti-corrosion layer at positions corresponding to the pads on the UBM layer.
[0049] First, form a first photoresist layer 130 on the UBM layer 120.
[0050] Specifically, as Figure 4 shown, coat a layer of the first photoresist layer 130 on the UBM layer 120. Among them, the first photoresist layer 130 can adopt a positive photoresist or a negative photoresist, and can be selected according to actual needs. This embodiment does not make specific limitations.
[0051] Second, pattern the first photoresist layer 130 to form a first opening at a position corresponding to the pad 111 on the first photoresist layer.
[0052] Specifically, as Figure 4 shown, provide a mask, place the mask above the first photoresist layer 130, and use the mask as a mask to expose and develop the first photoresist layer 130 to pattern the first photoresist layer 130, so as to form a first opening at a position corresponding to the pad 111 on the first photoresist layer 130.
[0053] Third, as Figure 5 shown, electroplate and form a conductive anti-corrosion layer 140 at the first opening. That is to say, a conductive anti-corrosion layer 140 is formed on the UBM layer 120 corresponding to each pad 111, preventing chemical corrosion in the subsequent process of forming a bump structure, solving the process conflict problem when different chips coexist, and improving the reliability of the chip.
[0054] Specifically, as Figure 5 shown, a gold plating solution is used to electroplate a gold plating layer at the first opening, and the gold plating layer serves as the conductive and corrosion-resistant layer 140. Using the gold plating layer as the conductive and corrosion-resistant layer 140 can achieve good corrosion resistance while realizing conductivity. Among them, in this embodiment, the thickness range of the gold plating layer is 0.1 μm to 1 μm. Preferably, in this embodiment, the thickness of the gold plating layer is 0.1 μm.
[0055] Finally, the remaining first photoresist layer 130 is removed.
[0056] Specifically, as Figure 5 shown, the remaining first photoresist layer 130 is removed through processes such as etching.
[0057] S140. A bump structure is electroplated on the conductive and corrosion-resistant layer corresponding to part of the pads.
[0058] First, a second photoresist layer is formed on all of the conductive and corrosion-resistant layers and the UBM layer.
[0059] Specifically, as Figure 6 shown, a layer of second photoresist layer 150 is coated on all of the conductive and corrosion-resistant layers 140 and the UBM layer 120. Among them, the second photoresist layer 150 can be a positive photoresist or a negative photoresist, which can be selected according to actual needs, and is not specifically limited in this embodiment.
[0060] Secondly, the second photoresist layer is patterned to form a second opening at the part of the conductive and corrosion-resistant layer corresponding to the second photoresist layer.
[0061] Specifically, as Figure 6 shown, a mask is provided and placed above the second photoresist layer 150. Using the mask as a mask, the second photoresist layer 150 is exposed and developed to pattern the second photoresist layer 150, so as to form a second opening at the part of the conductive and corrosion-resistant layer 140 corresponding to the second photoresist layer 150. That is to say, image formation is only performed at the part of the second photoresist layer 150 corresponding to part of the pads 111 to form a second opening.
[0062] Thirdly, the bump structure 160 is electroplated at the second opening.
[0063] Specifically, as Figure 7 shown, a gold plating solution is used to electroplate a gold bump structure at the second opening. The bump structure 160 is a gold bump structure, which can achieve better electrical connection. Among them, the thickness range of the gold bump structure is 5 μm to 18 μm. Preferably, in this embodiment, the thickness of the gold bump structure is 12 μm.
[0064] Finally, remove the remaining second photoresist layer.
[0065] Specifically, as Figure 7 shown, in this embodiment, processes such as etching can be used to remove the remaining second photoresist layer 150.
[0066] S150. Cut the wafer to form a plurality of first chips and a plurality of second chips. Among them, a conductive anti-corrosion layer and a bump structure are sequentially formed on the UBM layer of the first chip, and only the conductive anti-corrosion layer is formed on the UBM layer of the second chip.
[0067] Among them, before cutting the wafer, the method further includes:
[0068] As Figure 8 shown, remove a part of the UBM layer 120 so that the remaining UBM layer 120 is only connected to the conductive anti-corrosion layer 140. Among them, when removing a part of the UBM layer 120, since the conductive anti-corrosion layer 140 covers the UBM layer 120, each pad 111 of the wafer 110 can be protected from being corroded by the chemical solution, improving the reliability of the wafer.
[0069] In addition, after removing a part of the UBM layer 120, anneal the bump structure 160 so that the hardness of the formed bump structure 160 reaches a preset hardness, improving the bonding strength. Preferably, in this embodiment, the hardness of the bump structure 160 is 50HV.
[0070] The specific process of step S150 can be as follows:
[0071] As Figure 9 shown, cut the wafer along the scribe lines of the wafer 110 to form a plurality of first chips 200 and a plurality of second chips 300.
[0072] Among them, a conductive anti-corrosion layer 140 and a bump structure 160 are sequentially formed on the UBM layer 120 of the first chip 200, and only the conductive anti-corrosion layer 140 is formed on the UBM layer 120 of the second chip 300. That is to say, the first chip 200 and the second chip 300 are heterogeneous chips.
[0073] The bump structure 160 of the first chip 200 can be flip-chip connected to a substrate or other chips. The second chip 300 can be directly bonded to a substrate or other chips through conductive particles of COF (Chip on Film) (such as Anisotropic Conductive Film, ACF), using the conductive anti-corrosion layer 140 as a conductive medium.
[0074] A packaging method for forming a heterogeneous chip according to an embodiment of the present disclosure forms a conductive anti-corrosion layer on the UBM layer for the first time, preventing chemical corrosion in the subsequent process of forming the bump structure, and solving the process conflict problem when different chips coexist; the conductive anti-corrosion layer has both anti-corrosion and conductive functions, and the formed second chip does not need to form an additional passivation layer, simplifying the process flow and improving the reliability of the chip; combining the Bump and COF conductive particle technologies, the conductive anti-corrosion layer simultaneously meets the conductive requirements and anti-corrosion requirements.
[0075] As Figure 10 shown, on the other hand, an embodiment of the present disclosure provides a wafer packaging structure 100, and the wafer packaging structure 100 includes a wafer 110, a UBM layer 120, a conductive anti-corrosion layer 140, and a bump structure 160.
[0076] A plurality of pads 111 and a passivation layer 112 are provided on the functional surface of the wafer 110.
[0077] The UBM layer 120 is disposed on the pad 111 and the passivation layer 112 and is electrically connected to the pad 111. Among them, the UBM layer 120 can adopt a TiW layer or an Au layer.
[0078] The conductive anti-corrosion layer 140 is disposed on the UBM layer 120. Among them, the conductive anti-corrosion layer 140 can adopt a gold plating layer, and the gold plating layer can also play a good anti-corrosion role while realizing conductivity. Among them, in this embodiment, the thickness range of the gold plating layer is 0.1 μm to 1 μm. Preferably, in this embodiment, the thickness of the gold plating layer is 0.1 μm.
[0079] The bump structure 160 is disposed on the conductive anti-corrosion layer 140 corresponding to some of the pads 111. Among them, in this embodiment, the bump structure 160 can adopt a gold bump structure, and the thickness range of the gold bump structure is 5 μm to 18 μm. Preferably, in this embodiment, the thickness of the gold bump structure is 12 μm.
[0080] A wafer packaging structure according to an embodiment of the present disclosure can integrate heterogeneous chips on the functional surface of the wafer by disposing a conductive anti-corrosion layer on the UBM layer and disposing a bump structure on the conductive anti-corrosion layer corresponding to some of the pads, solving the process conflict problem when different chips coexist; by disposing the conductive anti-corrosion layer, the pads of the wafer can be prevented from being corroded, improving the reliability of the wafer. In addition, the conductive anti-corrosion layer has both anti-corrosion and conductive functions, and the formed second chip does not need to form an additional passivation layer, simplifying the process flow and improving the reliability of the chip.
[0081] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the embodiments of the present disclosure.
Claims
1. A packaging method for forming a heterogeneous chip, characterized in that The method includes: providing a wafer, wherein a functional surface of the wafer is provided with a plurality of pads and a passivation layer; forming a UBM layer electrically connected to the pads on the passivation layer and the pads; electroplating a conductive and corrosion-resistant layer corresponding to the pads on the UBM layer; electroplating a bump structure on the conductive and corrosion-resistant layer corresponding to some of the pads; dicing the wafer to form a plurality of first chips and a plurality of second chips, wherein the conductive and corrosion-resistant layer and the bump structure are sequentially formed on the UBM layer of the first chips, and only the conductive and corrosion-resistant layer is formed on the UBM layer of the second chips.
2. The method according to claim 1, wherein The electroplating a conductive and corrosion-resistant layer corresponding to the pads on the UBM layer includes: forming a first photoresist layer on the UBM layer; patterning the first photoresist layer to form a first opening corresponding to the pads on the first photoresist layer; electroplating the conductive and corrosion-resistant layer at the first opening; removing the remaining first photoresist layer.
3. The method according to claim 2, characterized in that The conductive and corrosion-resistant layer is a gold plating layer, and the thickness range of the gold plating layer is 0.1 μm to 1 μm.
4. The method according to any one of claims 1 to 3, characterized in that, The electroplating a bump structure on the conductive and corrosion-resistant layer corresponding to some of the pads includes: forming a second photoresist layer on all of the conductive and corrosion-resistant layer and the UBM layer; patterning the second photoresist layer to form a second opening corresponding to some of the conductive and corrosion-resistant layer on the second photoresist layer; electroplating the bump structure at the second opening; removing the remaining second photoresist layer.
5. The method according to claim 4, wherein The electroplating the bump structure at the second opening includes: electroplating a gold bump structure at the second opening through an electroplating process.
6. The method according to claim 5, wherein The thickness range of the gold bump structure is 5 μm to 18 μm.
7. The method according to claim 3, wherein Before dicing the wafer, the method further includes: removing a part of the UBM layer so that the remaining UBM layer is only connected to the conductive and corrosion-resistant layer.
8. A wafer packaging structure, characterized in that, The wafer packaging structure includes: a wafer, wherein a functional surface of the wafer is provided with a plurality of pads and a passivation layer; a UBM layer disposed on the pads and electrically connected to the pads; a conductive and corrosion-resistant layer disposed on the UBM layer; a bump structure disposed on the conductive and corrosion-resistant layer corresponding to some of the pads.
9. The wafer packaging structure according to claim 8, wherein, The conductive and corrosion-resistant layer is a gold plating layer.
10. The wafer packaging structure according to claim 9, characterized in that, The thickness range of the gold plating layer is 0.1 μm to 1 μm.