Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the steps that operation instruction information is obtained from a host system, the operation instruction information comprises instruction identification information, logic unit information and mapping table item information, and the mapping table item information comprises first coding information and second coding information; obtaining first entity unit information according to the first coding information, the offset information and the logic unit information; verifying the first entity unit information according to the second coding information; and if the verification result meets the preset condition, accessing the memory module according to the first entity unit information. Therefore, the operation stability of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and more particularly to a memory control method and a storage device. Background Art

[0002] Some types of storage devices can reduce operation latency by using the buffer of the host system based on the Host Memory Buffering (HMB) technology or the Host Performance Booster (HPB) technology, thereby improving the overall working efficiency of the storage device.

[0003] However, in some relatively complex operation scenarios or when performing error tests, the storage device cannot effectively detect or verify the correctness of the data currently read from the buffer of the host system, resulting in subsequent operation anomalies. Summary of the Invention

[0004] The present invention provides a memory control method and a storage device, which can improve the above problems and further enhance the operation stability of the storage device.

[0005] An embodiment of the present invention provides a memory control method for a storage device. The storage device includes a memory module, and the memory control method includes: obtaining operation instruction information from a host system, where the operation instruction information carries instruction identification information, logical unit information, and mapping table entry information, and the mapping table entry information includes first coding information and second coding information; after obtaining the operation instruction information, obtaining first physical unit information according to the first coding information, offset information, and the logical unit information; verifying the first physical unit information according to the second coding information to obtain a verification result; and if the verification result meets a preset condition, accessing the memory module according to the first physical unit information.

[0006] Another embodiment of the present invention provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: obtain operation instruction information from the host system, where the operation instruction information carries instruction identification information, logical unit information, and mapping table entry information, and the mapping table entry information includes first coding information and second coding information; after obtaining the operation instruction information, obtaining first physical unit information according to the first coding information, offset information, and the logical unit information; verifying the first physical unit information according to the second coding information to obtain a verification result; and if the verification result meets a preset condition, accessing the memory module according to the first physical unit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0008] Figure 2 FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0009] Figure 3 FIG. 3 is a schematic diagram of a managed memory module according to an embodiment of the present invention;

[0010] Figure 4 FIG. 4 is a schematic diagram of mapping table entry information according to an embodiment of the present invention;

[0011] Figure 5 FIG. 5 is a schematic diagram of a host system generating first encoded information according to an embodiment of the present invention;

[0012] Figure 6 FIG. 6 is a schematic diagram of a host system generating second encoded information according to an embodiment of the present invention;

[0013] Figure 7 FIG. 7 is a schematic diagram of a storage device generating physical unit information according to an embodiment of the present invention;

[0014] Figure 8 FIG. 8 is a schematic diagram of a storage device verifying first physical unit information according to an embodiment of the present invention;

[0015] Figure 9 FIG. 9 is a flowchart of a memory control method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 FIG. 10 is a schematic diagram of a storage system according to an embodiment of the present invention. Please refer to Figure 1, a storage system (also known as a data storage system) 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and is used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The host system 11 includes a processor 111 and a memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 can include a Central Processing Unit (CPU), a Graphical Processing Unit (GPU), or other programmable general-purpose or special-purpose microprocessors, a Digital Signal Processor (DSP), a programmable controller, an Application Specific Integrated Circuits (ASIC), a Programmable Logic Device (PLD), or other similar devices or a combination of these devices.

[0019] The memory 112 is connected to the processor 111 and is used to cache data. For example, the memory 112 can include a Random Access Memory (RAM) or a similar volatile storage device. It should be noted that the memory 112 is installed in the host system 11 (such as installed on the motherboard of the host system 11 or directly installed in the processor 111), rather than in the storage device 12.

[0020] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. The storage device 12 can communicate with the host system 11 via the connection interface 121 (such as exchanging signals, instructions, and / or data).

[0021] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of a voltage (also referred to as a threshold voltage). For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0022] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0023] The memory controller 123 can send an instruction sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0024] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0025] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0026] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0027] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0028] Figure 3 is a schematic diagram of managing a memory module shown in an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0029] In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical programming unit may include a plurality of physical sectors. For example, the data capacity of a physical sector can be 512 bytes (Bytes, B), and a physical programming unit can include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can both be adjusted according to actual needs, which are not limited in the present invention. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit can be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, an entity programming unit is the smallest unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on an entity programming unit to write data to this entity programming unit, multiple memory cells in this entity programming unit can be synchronously programmed to store the corresponding data. For example, when programming an entity programming unit, a write voltage can be applied to this entity programming unit to change the threshold voltage of at least some of the memory cells in this entity programming unit. For example, the threshold voltage of a memory cell can reflect the bit data stored in this memory cell.

[0031] In one embodiment, an entity erasure unit may include multiple entity programming units. The multiple entity programming units in an entity erasure unit can be synchronously erased. For example, when performing an erase operation on an entity erasure unit, an erase voltage can be applied to the multiple entity programming units in this entity erasure unit to change the threshold voltage of at least some of the memory cells in these entity programming units. By performing an erase operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit can be regarded as an entity block.

[0032] In one embodiment, the memory control circuit 23 can logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0033] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the idle area 32. In addition, the entity units in the idle area 32 can be erased to clear the data in this entity unit. In one embodiment, the entity units in the idle area 32 are also referred to as idle entity units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0034] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After the data is stored in the physical unit, the physical unit may be associated with the data area 31. In other words, one or more physical units may be alternately used between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1) to 302(C) to map the physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, one logical unit may correspond to one logical block address (LBA) or other logical management units. One logical unit may be mapped to one or more physical units.

[0036] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in this physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that this physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing according to the information in this management table (i.e., the logical-to-physical mapping table).

[0038] In one embodiment, the processor 111 may configure (e.g., partition) a buffer area (also referred to as a shared buffer area) 101 in the memory 112 of the host system 11. Thereafter, the storage device 12 may perform a preset operation based on the data cached in the shared buffer area 101. For example, the preset operation includes storing data in the memory module 122, reading data from the memory module 122, deleting data in the memory module 122, or other operations related to the access or management of the memory module 122.

[0039] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12. For example, the memory control circuit 23 may perform a handshake operation with the host system 11. The handshake operation is used to exchange information related to the establishment of the connection between the host system 11 and the storage device 12, such as clock information and / or voltage information, etc.

[0040] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12 according to the execution result of the handshaking operation. Thereafter, the memory control circuit 23 may access (also referred to as "visit") the shared buffer 101 through the connection.

[0041] In one embodiment, the shared buffer 101 is also referred to as the host buffer. In one embodiment, the memory control circuit 23 may access the shared buffer 101 based on the Host Memory Buffering (HMB) technology or the Host Performance Booster (HPB) technology. Or, from another perspective, the processor 111 may manage the shared buffer 101 based on the Host Memory Buffering (HMB) technology or the Host Performance Booster (HPB) technology and provide the shared buffer 101 for the storage device 12 to use.

[0042] In one embodiment, the memory control circuit 23 may provide management data to the host system 11. For example, the management data may include logical-to-physical mapping information related to at least one logical unit. For example, the logical-to-physical mapping information may reflect the mapping relationship between the at least one logical unit and the at least one physical unit. Thereafter, the memory control circuit 23 may access the memory module 122 based on the management data (such as logical-to-physical mapping information) in the shared buffer 101.

[0043] In one embodiment, the host system 11 may cache the operation instruction information in the shared buffer 101 according to the management data. Then, the host system 11 may provide the operation instruction information to the storage device 12. For example, the host system 11 may notify the storage device 12 (such as the memory control circuit 23) to actively read the operation instruction information from the shared buffer 101.

[0044] In one embodiment, after obtaining the operation instruction information from the shared buffer 101, the memory control circuit 23 may access the memory module 122 according to the operation instruction information. For example, the memory control circuit 23 may read data from the memory module 122, store data in the memory module 122, or erase the data in the memory module 122 according to the operation instruction information.

[0045] In one embodiment, the operation instruction information may carry instruction identification information, logical unit information, and mapping table entry information. The instruction identification information can be used to reflect the type of access operation indicated by the operation instruction information. For example, the instruction identification information can reflect that the access operation is at least one of a read operation, a write operation, and a delete operation (or erase operation). The logical unit information can be used to reflect the logical unit (also referred to as the target logical unit) targeted by the access operation. For example, the logical unit information may carry identification information corresponding to the target logical unit (such as the number or logical address of the target logical unit). For example, the target logical unit can be Figure 3 at least one of logical units 302(1) to 302(C) in

[0046] In one embodiment, the mapping table entry information may carry a plurality of encoding information. In particular, the plurality of encoding information can be used to verify the correctness and / or integrity of the operation instruction information. Thereby, the operation stability can be improved when the subsequent memory control circuit 23 performs an access operation on the memory module 122 based on the operation instruction information.

[0047] In one embodiment, the mapping table entry information includes first encoding information and second encoding information. In one embodiment, after obtaining the operation instruction information, the memory control circuit 23 can parse the mapping table entry information based on a preset data format to extract the first encoding information and the second encoding information from the mapping table entry information. For example, the preset data format can be used to define or specify the positions (such as storage positions) of the first encoding information, the second encoding information, and other types of information in the mapping table entry information.

[0048] In one embodiment, after obtaining the first encoding information, the memory control circuit 23 can obtain physical unit information (also referred to as first physical unit information) according to the first encoding information, offset information, and the logical unit information. For example, the first physical unit information can reflect at least one physical unit (also referred to as the target physical unit) corresponding to (such as mapped by) the target logical unit. For example, the first physical unit information may carry identification information corresponding to the target physical unit (such as the number or physical address of the target physical unit).

[0049] In one embodiment, the offset information can be used to update (such as modify or compensate) the logical unit information. For example, the offset information may include an offset value. The memory control circuit 23 can update the logical unit information according to this offset value. Then, the memory control circuit 23 can obtain the first physical unit information according to the first encoding information and the updated logical unit information.

[0050] In one embodiment, after obtaining the operation instruction information, the memory control circuit 23 may perform an information combination operation according to the offset information and the logic unit information to obtain transient information (also referred to as first transient information). For example, in the information combination operation, the memory control circuit 23 may add the logic unit information to the offset information (such as the aforementioned offset value) to obtain the first transient information. In one embodiment, the first transient information may include updated logic unit information obtained by updating the logic unit information based on the offset information.

[0051] In one embodiment, after obtaining the first transient information, the memory control circuit 23 may perform an information restoration operation according to the first coding information and the first transient information to obtain the first physical unit information. For example, in the information restoration operation, the memory control circuit 23 may perform a logic operation on the first coding information and the first transient information to obtain the first physical unit information. For example, the logic operation may include an exclusive OR (XOR) operation or other types of logic operations, which are not limited in the present invention. In one embodiment, the first physical unit information may reflect the operation result of performing the aforementioned logic operation on the first coding information and the first transient information.

[0052] In one embodiment, after obtaining the first physical unit information, the memory control circuit 23 may verify the first physical unit information according to the second coding information to obtain a verification result. For example, the verification result may reflect the correctness and / or integrity of the first physical unit information.

[0053] In one embodiment, after obtaining the first physical unit information, the memory control circuit 23 may perform an information generation operation according to the first physical unit information to obtain another coding information (also referred to as third coding information). For example, in the information generation operation, the memory control circuit 23 may perform an operation to generate a Cyclic Redundancy Check (CRC) code according to the first physical unit information to obtain the third coding information including the cyclic redundancy check code. For example, in the information generation operation, the memory control circuit 23 may use the first physical unit information as one of at least one operand. Then, the memory control circuit 23 may perform an operation to generate a cyclic redundancy check code based on the at least one operand to obtain the third coding information. Then, the memory control circuit 23 may verify the first physical unit information based on the second coding information and the third coding information.

[0054] In one embodiment, after obtaining the third encoded information, the memory control circuit 23 may perform an information comparison operation based on the third encoded information and the second encoded information to obtain the verification result. For example, in the information comparison operation, the memory control circuit 23 may compare the third encoded information with the second encoded information to obtain a comparison result. For example, the comparison result may reflect whether the information content of the third encoded information is the same as the information content of the second encoded information. Then, the memory control circuit 23 may obtain the verification result according to the comparison result.

[0055] In one embodiment, if the comparison result reflects that the information content of the third encoded information is the same as the information content of the second encoded information, the memory control circuit 23 may obtain a verification result (also referred to as the first verification result). In other words, the first verification result corresponds to the comparison result that the information content of the third encoded information is the same as the information content of the second encoded information. However, if the comparison result reflects that the information content of the third encoded information is different from the information content of the second encoded information, the memory control circuit 23 may obtain another verification result (also referred to as the second verification result). In other words, the second verification result corresponds to the comparison result that the information content of the third encoded information is different from the information content of the second encoded information.

[0056] In one embodiment, after obtaining the verification result, the memory control circuit 23 may confirm whether the verification result meets a preset condition. For example, the memory control circuit 23 may confirm whether the verification result is the first verification result or the second verification result. If the verification result is the first verification result, the memory control circuit 23 may determine that the verification result meets the preset condition. However, if the verification result is the second verification result, the memory control circuit 23 may determine that the verification result does not meet the preset condition.

[0057] In one embodiment, if the verification result meets the preset condition, the memory control circuit 23 may access the memory module 122 according to the first physical unit information. For example, when the verification result meets the preset condition, the memory control circuit 23 may, according to the first physical unit information, instruct the memory module 122 to read data from a target physical unit, write data to the target physical unit, or delete the data stored in the target physical unit. Thus, the access operation indicated by the operation instruction information can be completed.

[0058] In one embodiment, if the verification result does not meet the preset condition, the memory control circuit 23 may not access the memory module 122 according to the first physical unit information. For example, when the verification result does not meet the preset condition, the memory control circuit 23 may discard (or ignore) the first physical unit information and not access the memory module 122 according to the first physical unit information. Thus, operation errors (such as access errors to the memory module 122) caused in the storage device 12 due to incorrect first physical unit information (or operation instruction information) (such as containing error information) can be avoided.

[0059] In one embodiment, if the verification result does not meet the preset condition, the memory control circuit 23 may query a management table (also referred to as the first management table) according to the logical unit information to obtain physical unit information (also referred to as the second physical unit information). For example, the first management table may include the foregoing logical-to-physical mapping table. Similar to the first physical unit information, the second physical unit information can also reflect at least one physical unit (i.e., the target physical unit) corresponding to (e.g., mapped to) the target logical unit. For example, the second physical unit information may carry identification information corresponding to the target physical unit.

[0060] It should be noted that the second physical unit information may be different from the first physical unit information. For example, assume that the first physical unit information reflects that Figure 3 the physical unit 301(i) in is the target physical unit, then the second physical unit information may reflect that Figure 3 the physical unit 301(j) in is the target physical unit, and i is different from j.

[0061] In one embodiment, after obtaining the second physical unit information, the memory control circuit 23 may access the memory module 102 according to the second physical unit information. For example, when the verification result does not meet the preset condition, the memory control circuit 23 may, according to the first physical unit information, instruct the memory module 122 to read data from the target physical unit, write data to the target physical unit, or delete the data stored in the target physical unit. Thus, even if there are errors in the operation instruction information, the access operation indicated by the operation instruction information can still be successfully completed, thereby greatly improving the operation stability of the storage device 12.

[0062] In one embodiment, the mapping entry information further includes auxiliary information (also referred to as the first auxiliary information). In one embodiment, the memory control circuit 23 may extract the first auxiliary information from the mapping entry information based on the foregoing preset data format.

[0063] In one embodiment, the memory control circuit 23 may also query a management table (also referred to as the second management table) according to the logical unit information to obtain verification information (also referred to as the first verification information) corresponding to the logical unit (i.e., the target logical unit). Then, the memory control circuit 23 may determine whether the verification result meets a preset condition according to the first verification information and the first auxiliary information.

[0064] In one embodiment, the memory control circuit 23 may determine a logical area (also referred to as the target logical area) to which the target logical unit belongs according to the logical unit information. For example, the target logical area may include a plurality of consecutive logical units, and the target logical unit is at least one of the plurality of consecutive logical units. After determining the target logical area, the memory control circuit 23 may query the second management table to obtain verification information (i.e., the first verification information) corresponding to the target logical area. For example, different logical areas may correspond to different verification information.

[0065] For Figure 3 example, assume that logical units 302(1) to 302(C) are divided into a plurality of consecutive logical areas. Each logical area contains n logical units among logical units 302(1) to 302(C). n can be any integer greater than 1. In one embodiment, if the target logical unit is logical unit 302(p), the memory control circuit 23 may determine that the target logical unit belongs to a certain logical area (also referred to as the first logical area) among the plurality of consecutive logical areas. In this case, the memory control circuit 23 may query the second management table to obtain verification information corresponding to the first logical area. For example, the verification information corresponding to the first logical area may include a verification value (also referred to as the first verification value). Then, the memory control circuit 23 may set this verification information (i.e., the first verification value) as the first verification information.

[0066] In one embodiment, if the target logical unit is logical unit 302(q) (where q is different from p), the memory control circuit 23 may determine that the target logical unit belongs to another logical area (also referred to as the second logical area) among the plurality of consecutive logical areas. The second logical area is different from the first logical area. In this case, the memory control circuit 23 may query the second management table to obtain verification information corresponding to the second logical area. For example, the verification information corresponding to the second logical area may include another verification value (also referred to as the second verification value). The second verification value is different from the first verification value. Then, the memory control circuit 23 may set this verification information (i.e., the second verification value) as the first verification information.

[0067] In one embodiment, after obtaining the first verification information, the memory control circuit 23 may determine whether the verification result meets a preset condition according to the first verification information and the first auxiliary information. For example, the memory control circuit 23 may determine whether the first verification information is the same as the first auxiliary information. If the first verification information is the same as the first auxiliary information, the memory control circuit 23 may further refer to the foregoing operations to determine whether the verification result meets the preset condition. However, if the first verification information is different from the first auxiliary information, the memory control circuit 23 may directly determine that the verification result does not meet the preset condition.

[0068] In one embodiment, by comparing the first verification information with the first auxiliary information, the memory control circuit 23 may confirm whether the host system 11 and the storage device 12 have the same recognition of the logical area to which the target logical unit belongs. If the first verification information is the same as the first auxiliary information, it means that the host system 11 and the storage device 12 have the same recognition of the logical area to which the target logical unit belongs. In this case, the memory control circuit 23 may allow the execution of the remaining verification operations. However, if the first verification information is different from the first auxiliary information, it means that the host system 11 and the storage device 12 have different recognitions of the logical area to which the target logical unit belongs. In this case, the memory control circuit 23 may determine that the verification result does not meet the preset condition and prevent access to the memory module 122 based on the foregoing first physical unit information. Thus, subsequent access errors caused by incorrect management data used by the host system 11 or the management data not being updated to the latest state can be avoided.

[0069] In one embodiment, the memory control circuit 23 may perform a random number generation operation to generate a plurality of random numbers (also referred to as pseudo-random numbers). The plurality of random numbers are different from each other. Then, the memory control circuit 23 may set verification information (i.e., verification values) corresponding to the plurality of logical areas according to the plurality of random numbers. Thus, it can be ensured as much as possible that the verification information (i.e., verification values) corresponding to each logical area is unique.

[0070] In one embodiment, the mapping table entry information further includes another auxiliary information (also referred to as second auxiliary information). In one embodiment, the memory control circuit 23 may extract the second auxiliary information from the mapping table entry information based on the foregoing preset data format. The second auxiliary information may reflect whether the physical unit (i.e., the target physical unit) mapped by the logical unit (i.e., the target logical unit) belongs to a plurality of continuously accessed physical units or the total number of the plurality of continuously accessed physical units. For example, the continuous access may refer to continuous writing or continuous reading.

[0071] In one embodiment, after obtaining the second auxiliary information, according to the second auxiliary information, the memory control circuit 23 can confirm whether the target physical unit belongs to a plurality of continuously accessed physical units without querying the mapping relationship between the target logical unit and the target physical unit (such as querying the aforementioned first management table). Alternatively, in one embodiment, according to the second auxiliary information, the memory control circuit 23 can confirm the total number of the plurality of continuously accessed physical units and the plurality of continuously written physical units to which the target physical unit belongs without querying the mapping relationship between the target logical unit and the target physical unit.

[0072] In one embodiment, if the second auxiliary information includes a certain information content (also referred to as the first information content), without querying the mapping relationship between the target logical unit and the target physical unit, the memory control circuit 23 can directly determine, based on the first information content, that the target physical unit does not belong to the plurality of continuously accessed physical units. For example, the first information content may include "00h", which reflects that the access to the target physical unit is a random access (such as a random write or a random read), rather than a continuous access involving a plurality of physical units (such as a continuous write or a continuous read).

[0073] In one embodiment, if the second auxiliary information includes another information content (also referred to as the second information content), then without querying the mapping relationship between the target logical unit and the target physical unit, the memory control circuit 23 can directly determine, based on the second information content, the total number of the plurality of continuously accessed physical units and the plurality of continuously accessed physical units to which the target physical unit belongs. For example, the second information content may include "01h", "02h", or "03h", which sequentially reflect that the access to the target physical unit involves a continuous access to a plurality of physical units (such as a continuous write or a continuous read), and the total number of the plurality of physical units is one, two, or three, respectively. For example, the target physical unit is the first physical unit among these continuously accessed physical units.

[0074] In one embodiment, the aforementioned second auxiliary information can be used to accelerate the access performance of the memory control circuit 23 for the target physical unit (or a plurality of continuously accessed physical units including the target physical unit). In addition, the information content and the information reflected by the first auxiliary information and / or the second auxiliary information can be adjusted according to practical requirements, and the present invention does not impose any limitations.

[0075] In one embodiment, after determining the logical region where the target logical unit is located (i.e., the target logical region), the memory control circuit 23 may further determine whether the target logical region is an active region. Then, the memory control circuit 23 may determine whether the verification result meets the preset condition based on whether the target logical region is an active region. For example, if the target logical region is an active region, the memory control circuit 23 may further refer to the foregoing operations to determine whether the verification result meets the preset condition. However, if the target logical region is not an active region, the memory control circuit 23 may directly determine that the verification result does not meet the preset condition.

[0076] In one embodiment, before obtaining the operation instruction information from the host system 11, the memory control circuit 23 may transmit mapping information related to multiple logical units in the target logical region (also referred to as target mapping information) to the host system 11. For example, the target mapping information may reflect the mapping relationship between multiple logical units in the target logical region and multiple physical units respectively. In response to the target mapping information having been transmitted to the host system 11, the memory control circuit 23 may mark the target logical region as an active region. However, if the memory control circuit 23 does not transmit the target mapping information to the host system 11 before obtaining the operation instruction information from the host system 11, the memory control circuit 23 may mark the target logical region as an inactive region.

[0077] In one embodiment, by confirming whether the target logical region is an active region, it affects the judgment of whether the verification result meets the preset condition, which also helps to avoid subsequent access errors caused by incorrect management data used by the host system 11 or the management data not being updated to the latest state.

[0078] In one embodiment, after obtaining the logical unit information from the operation instruction information, the memory control circuit 23 may further determine whether the mapping table entry information is valid according to the logical unit information. For example, before obtaining the operation instruction information from the host system 11, the memory control circuit 23 may query a management table (also referred to as the third management table) according to the logical unit information to determine whether the mapping table entry information is valid. For example, in response to a change in the mapping relationship between the target logical unit and at least one physical unit, the memory control circuit 23 may mark the mapping table entry information corresponding to the target logical unit as invalid in the third management table. However, if the mapping relationship between the target logical unit and at least one physical unit has not been changed, the memory control circuit 23 may mark the mapping table entry information corresponding to the target logical unit as valid in the third management table. After obtaining the operation instruction information from the host system 11, the memory control circuit 23 may determine whether the verification result meets the preset condition according to whether the mapping table entry information is valid.

[0079] In one embodiment, if the memory control circuit 23 determines that the mapping entry information is valid, the memory control circuit 23 may further refer to the foregoing operations to determine whether the verification result meets a preset condition. However, if the memory control circuit 23 determines that the mapping entry information is invalid, the memory control circuit 23 may directly determine that the verification result does not meet the preset condition.

[0080] In one embodiment, by confirming whether the mapping entry information carried in the operation instruction information is valid, it affects the judgment of whether the verification result meets the preset condition, and also helps to avoid subsequent access errors caused by incorrect management data used by the host system 11 or the management data not being updated to the latest state.

[0081] Figure 4 is a schematic diagram of mapping entry information shown in an embodiment of the present invention. Please refer to Figure 4 , the mapping entry information 41 may include coding information 401 (i.e., first coding information), auxiliary information 411 (i.e., first auxiliary information), coding information 402 (i.e., second coding information), reserved information 421, and auxiliary information 412 (i.e., second auxiliary information). The coding information 401, auxiliary information 411, coding information 402, reserved information 421, and auxiliary information 412 may be stored in the mapping entry information 41 based on a preset data format. For example, in the mapping entry information 41, the 0th to 31st bits belong to the coding information 401, the 32nd to 47th bits belong to the auxiliary information 411, the 48th to 55th bits belong to the coding information 402, the 56th to 58th bits belong to the reserved information 421, and the 59th to 63rd bits belong to the auxiliary information 412. It should be noted that the format of the mapping entry information 41 (i.e., the preset data format) and the types of information included may also be adjusted according to practical requirements, and the present invention does not limit them.

[0082] Figure 5 is a schematic diagram of the host system generating the first coding information shown in an embodiment of the present invention. Please refer to Figure 5 , in one embodiment, the processor 111 may obtain mapping information related to the target logical unit from the storage device 12. This mapping information may reflect the mapping relationship between the target logical unit and the target physical unit. According to this mapping information, the processor 111 may obtain the logical unit information 501 and the physical unit information 502. For example, the logical unit information 501 may carry identification information corresponding to the target logical unit. The physical unit information 502 may carry identification information corresponding to the target physical unit. In addition, the processor 111 may obtain the offset information 503. For example, the offset information 503 may be obtained from the storage device 12 or built into the host system 11. For example, the offset information 503 may include an offset value.

[0083] In one embodiment, the processor 111 may perform an information combining operation 51 according to the logical unit information 501 and the offset information 503 to obtain transient information 504. For example, in the information combining operation 51, the processor 111 may add the logical unit information 501 to the offset information 503 to obtain the transient information 504. Then, the processor 111 may perform an information generating operation 52 according to the physical unit information 502 and the transient information 504 to obtain encoded information 401. For example, in the information generating operation 52, the processor 111 may perform an exclusive OR (XOR) operation or other types of logical operations on the physical unit information 502 and the transient information 504 to obtain the encoded information 401. Then, the processor 111 may add the encoded information 401 to the mapping table entry information 41.

[0084] Figure 6 FIG. is a schematic diagram of a host system generating second encoded information according to an embodiment of the present invention. Please refer to Figure 6 In one embodiment, the processor 111 may perform an information generating operation 61 according to the physical unit information 502, the auxiliary information 411, the auxiliary information 412, and the reserved information 421 to obtain encoded information 402. For example, in the information generating operation 61, the processor 111 may perform a cyclic redundancy check (CRC) code generating operation on the physical unit information 502, the auxiliary information 411, the auxiliary information 412, and the reserved information 421 to obtain the encoded information 402 including the cyclic redundancy check code. Then, the processor 111 may add the encoded information 402 to the mapping table entry information 41.

[0085] In one embodiment, the processor 111 may obtain the auxiliary information 411 from the storage device 12. For example, the memory control circuit 23 may provide the auxiliary information 411 to the host system 11 according to the target logical region to which the target logical unit belongs. For example, the auxiliary information 411 may include verification information corresponding to the target logical unit (or target logical region). Then, the processor 111 may add the auxiliary information 411 to the mapping table entry information 41.

[0086] In one embodiment, the processor 111 may obtain the auxiliary information 412 according to whether the target physical unit belongs to a plurality of continuously accessed physical units and the total number of the plurality of continuously written physical units. Then, the processor 111 may add the auxiliary information 412 to the mapping table entry information 41.

[0087] In one embodiment, the reserved information 421 can be reserved for subsequent provision of other useful information. For example, when the reserved information 421 is reserved, the reserved information 421 can include a plurality of preset bits. For example, the plurality of preset bits can include a plurality of "0"s, a plurality of "1"s, or other types of bit combinations, which are not limited in the present invention. Then, the processor 111 can add the reserved information 421 to the mapping entry information 41.

[0088] In one embodiment, when the processor 111 desires to instruct the storage device 12 to access data belonging to a target logical unit, the processor 111 can automatically add the encoding information 401, the auxiliary information 411, the encoding information 402, the reserved information 421, and the auxiliary information 412 to the mapping entry information 41 according to a preset data format to generate the mapping entry information 41. Then, the operation instruction information including the instruction identification information, the logical unit information 501, and the mapping entry information 41 can be cached in the memory 112 (such as the shared buffer 101) for the storage device 12 to read. Alternatively, the processor 111 can also actively provide the operation instruction information to the storage device 12, which is not limited in the present invention.

[0089] Figure 7 is a schematic diagram of a storage device generating entity unit information shown according to an embodiment of the present invention. Please refer to Figure 7 In one embodiment, after obtaining the operation instruction information from the host system 11, the memory control circuit 23 can extract the logical unit information 501 and the encoding information 401 from the operation instruction information. At the same time, the memory control circuit 23 can obtain the offset information 503. The offset information 503 is the same as Figure 5 the offset information 503 in

[0090] In one embodiment, the memory control circuit 23 can perform an information combination operation 71 according to the logical unit information 501 and the offset information 503 to obtain the transient information 701. For example, in the information combination operation 71, the memory control circuit 23 can add the logical unit information 501 to the offset information 503 (such as the aforementioned offset value) to obtain the transient information 701 (i.e., the first transient information). Then, the memory control circuit 23 can perform an information generation operation 72 (i.e., an information restoration operation) according to the encoding information 401 and the transient information 701 to obtain the entity unit information 502 (i.e., the first entity unit information). For example, in the information generation operation 72, the memory control circuit 23 can perform a logical operation on the encoding information 401 and the transient information 701 to obtain the entity unit information 502. For example, the logical operation can include an exclusive OR (XOR) operation or other types of logical operations, which are not limited in the present invention.

[0091] It should be noted that in Figure 7In the embodiment, it is assumed that the entity unit information 502 dynamically generated according to the encoding information 401 and the transient information 701 is the same as Figure 5 the entity unit information 502 used in Figure 7 However, in another embodiment of Figure 5 , affected by factors such as incorrect management data used by the host system 11 or the management data not being updated to the latest state, the entity unit information 502 dynamically generated according to the encoding information 401 and the transient information 701 may be different from Figure 7 the entity unit information 502 in

[0092] Figure 8 FIG. is a schematic diagram of a storage device verifying first entity unit information according to an embodiment of the present invention. Please refer to Figure 8 , following the embodiment of Figure 7 , after dynamically generating the entity unit information 502, the memory control circuit 23 may perform an information generation operation 81 according to the entity unit information 502 and the auxiliary information 411, auxiliary information 412, and reserved information 421 extracted from the operation instruction information (or mapping table entry information 41) to obtain encoding information 801 (i.e., the third encoding information). For example, in the information generation operation 81, the memory control circuit 23 may perform a cyclic redundancy check code generation operation according to the entity unit information 502, auxiliary information 411, auxiliary information 412, and reserved information 421 to obtain the encoding information 801 including the cyclic redundancy check code.

[0093] In one embodiment, after obtaining the encoding information 801, the memory control circuit 23 may perform an information comparison operation 82 according to the dynamically generated encoding information 801 and the encoding information 402 extracted from the operation instruction information (or mapping table entry information 41) to obtain a verification result 802. For example, the verification result 802 may reflect whether the information content of the encoding information 801 is the same as the information content of the encoding information 402.

[0094] In an embodiment, after obtaining the verification result 802, the memory control circuit 23 may determine whether the verification result 802 meets a preset condition. If the verification result 802 meets the preset condition (for example, the information content of the encoded information 801 is the same as the information content of the encoded information 402), the memory control circuit 23 may access the memory module 122 according to the dynamically generated physical unit information 502. However, if the verification result 802 does not meet the preset condition (for example, the information content of the encoded information 801 is different from the information content of the encoded information 402), the memory control circuit 23 may discard (or ignore) the dynamically generated physical unit information 502. Thus, subsequent access errors caused by incorrect management data used by the host system 11 or the management data not being updated to the latest state can be avoided.

[0095] In an embodiment, if the verification result 802 does not meet the preset condition, the memory control circuit 23 may query a management table (i.e., the first management table) to obtain another physical unit information (i.e., the second physical unit information). Then, the memory control circuit 23 may access the memory module 122 according to the second physical unit information. Thus, even if there is an error in the operation instruction information, the access operation indicated by the operation instruction information can still be successfully completed, thereby greatly improving the operation stability of the storage device 12.

[0096] In an embodiment, the memory control circuit 23 may also assist in confirming whether the verification result 802 meets the preset condition according to the auxiliary information 411 and / or the auxiliary information 412 extracted from the operation instruction information (or the mapping table entry information 41). The relevant operation details have been described in detail above and will not be repeated here.

[0097] Figure 9 is a flowchart of a memory control method shown in an embodiment of the present invention. Please refer to Figure 9 , in step S901, operation instruction information is obtained from the host system, where the operation instruction information carries instruction identification information, logical unit information, and mapping table entry information. In particular, the mapping table entry information includes first encoded information and second encoded information. After obtaining the operation instruction information, in step S902, first physical unit information is obtained according to the first encoded information, offset information, and the logical unit information. In step S903, the first physical unit information is verified according to the second encoded information to obtain a verification result. In step S904, it is confirmed whether the verification result meets the preset condition.

[0098] If the verification result meets the preset conditions, in step S905, access the memory module according to the first entity unit information. However, if the verification result does not meet the preset conditions, in step S906, query the first management table according to the logic unit information to obtain the second entity unit information. In step S907, access the memory module according to the second entity unit information.

[0099] However, Figure 9 The steps in [it] have been described in detail above and will not be elaborated here. It should be noted that, Figure 9 The steps in [it] can be implemented as multiple pieces of program code or circuits, and the present invention does not impose any restrictions. In addition, Figure 9 The method in [it] can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention does not impose any restrictions.

[0100] In summary, for the memory control method and storage device proposed in the embodiments of the present invention, through the specially designed mapping table entry information (including at least the first coding information and the second coding information), it is possible to effectively detect mapping table entry information containing error content (such as incorrect entity unit information) caused by factors such as incorrect management data used by the host system or the management data not being updated to the latest state. In particular, after detecting the mapping table entry information containing error content, by performing a table lookup operation inside the storage device, correct entity unit information can be obtained, and based on this entity unit information, the access operation instructed by the host system can be completed. Thereby, the operation stability of the storage device can be effectively improved.

[0101] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that, For a storage device, the storage device includes a memory module, and the memory control method includes: Obtaining operation instruction information from a host system, where the operation instruction information carries instruction identification information, logical unit information, and mapping table entry information, and the mapping table entry information includes first coding information and second coding information; After obtaining the operation instruction information, obtaining first physical unit information according to the first coding information, offset information, and the logical unit information; Verifying the first physical unit information according to the second coding information to obtain a verification result; and If the verification result meets a preset condition, accessing the memory module according to the first physical unit information.

2. The memory control method according to claim 1, wherein the instruction identification information reflects the type of access operation indicated by the operation instruction information, and the logical unit information reflects the logical unit targeted by the access operation; and The access operation is at least one of a read operation, a write operation, and a delete operation.

3. The memory control method according to claim 1, wherein the step of obtaining the physical unit information according to the first coding information, the offset information, and the logical unit information includes: Performing an information combination operation according to the offset information and the logical unit information to obtain first transient information; And Performing an information restoration operation according to the first coding information and the first transient information to obtain the first physical unit information.

4. The memory control method according to claim 1, wherein the step of verifying the first physical unit information according to the second coding information to obtain the verification result includes: Performing an information generation operation according to the first physical unit information to obtain third coding information; And Performing an information comparison operation according to the third coding information and the second coding information to obtain the verification result.

5. The memory control method according to claim 1, further includes: If the verification result does not meet the preset condition, querying a first management table according to the logical unit information to obtain second physical unit information; And Accessing the memory module according to the second physical unit information.

6. The memory control method according to claim 1, wherein the mapping table entry information further includes first auxiliary information, and the memory control method further includes: Querying a second management table according to the logical unit information to obtain first verification information corresponding to the logical unit; And Determining whether the verification result meets the preset condition according to the first verification information and the first auxiliary information.

7. The memory control method according to claim 1, wherein the mapping table entry information further includes second auxiliary information, and the memory control method further includes: According to the second auxiliary information, without querying the mapping relationship between the logical unit and at least one physical unit, confirming whether the physical unit mapped by the logical unit belongs to the total number of multiple continuously accessed physical units or the multiple continuously written physical units.

8. The memory control method according to claim 7, wherein the step of, according to the second auxiliary information, without querying the mapping relationship between the logic unit and the at least one physical unit, confirming whether the physical unit mapped by the logic unit belongs to the plurality of consecutively accessed physical units or the total number of the plurality of consecutively accessed physical units includes: If the second auxiliary information includes a first information content, without querying the mapping relationship between the logic unit and the at least one physical unit, according to the first information content, determining that the physical unit mapped by the logic unit does not belong to the plurality of consecutively accessed physical units; And If the second auxiliary information includes a second information content, without querying the mapping relationship between the logic unit and the at least one physical unit, according to the second information content, determining the total number of the plurality of consecutively accessed physical units, wherein the second information content is different from the first information content.

9. The memory control method according to claim 1, further comprising: Determining a target logic area according to the logic unit information, wherein the logic unit is included in the target logic area; And Determining whether the verification result meets the preset condition according to whether the target logic area is an active area.

10. The memory control method according to claim 1, further comprising: Determining whether the mapping table entry information is valid according to the logic unit information; And Determining whether the verification result meets the preset condition according to whether the mapping table entry information is valid.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; And A memory controller connected to the connection interface and the memory module, Wherein the memory controller is configured to: Obtain operation instruction information from the host system, wherein the operation instruction information carries instruction identification information, logic unit information, and mapping table entry information, and the mapping table entry information includes first coding information and second coding information; After obtaining the operation instruction information, according to the first coding information, offset information, and the logic unit information, obtain first physical unit information; Verify the first physical unit information according to the second coding information to obtain a verification result; And If the verification result meets the preset condition, access the memory module according to the first physical unit information.

12. The storage device according to claim 11, wherein the instruction identification information reflects the type of the access operation indicated by the operation instruction information, and the logic unit information reflects the logic unit targeted by the access operation; and The access operation is at least one of a read operation, a write operation, and a delete operation.

13. The storage device according to claim 11, wherein the operation of the memory controller obtaining the physical unit information according to the first coding information, the offset information, and the logic unit information includes: Performing an information combination operation according to the offset information and the logic unit information to obtain first transient information; And Perform an information restoration operation according to the first encoding information and the first transient information to obtain the first entity unit information.

14. The storage device according to claim 11, wherein the operation of the memory controller verifying the first entity unit information according to the second encoding information to obtain the verification result includes: Performing an information generation operation according to the first entity unit information to obtain third encoding information; And Performing an information comparison operation according to the third encoding information and the second encoding information to obtain the verification result.

15. The storage device according to claim 11, wherein the memory controller is further configured to: If the verification result does not meet the preset condition, query a first management table according to the logical unit information to obtain second entity unit information; and Access the memory module according to the second entity unit information.

16. The storage device according to claim 11, wherein the mapping table entry information further includes first auxiliary information, and the memory controller is further configured to: Query a second management table according to the logical unit information to obtain first verification information corresponding to the logical unit; and Determine whether the verification result meets the preset condition according to the first verification information and the first auxiliary information.

17. The storage device according to claim 11, wherein the mapping table entry information further includes second auxiliary information, and the memory controller is further configured to: According to the second auxiliary information, without querying the mapping relationship between the logical unit and at least one entity unit, confirm whether the entity unit mapped by the logical unit belongs to a plurality of consecutively accessed entity units or the total number of the plurality of consecutively accessed entity units.

18. The storage device according to claim 17, wherein the operation of the memory controller confirming whether the entity unit mapped by the logical unit belongs to the plurality of consecutively accessed entity units or the total number of the plurality of consecutively accessed entity units according to the second auxiliary information without querying the mapping relationship between the logical unit and the at least one entity unit includes: If the second auxiliary information includes a first information content, without querying the mapping relationship between the logical unit and the at least one entity unit, determine according to the first information content that the entity unit mapped by the logical unit does not belong to the plurality of consecutively accessed entity units; And If the second auxiliary information includes a second information content, without querying the mapping relationship between the logical unit and the at least one entity unit, determine the total number of the plurality of consecutively accessed entity units according to the second information content, wherein the second information content is different from the first information content.

19. The storage device according to claim 11, wherein the memory controller is further configured to: Determine a target logical area according to the logical unit information, wherein the logical unit is included in the target logical area; and Determine whether the verification result meets the preset condition according to whether the target logical area is an active area.

20. The storage device according to claim 11, wherein the memory controller is further configured to: Determine whether the mapping table entry information is valid according to the logical unit information; and Determine whether the verification result meets the preset condition according to whether the mapping table entry information is valid.

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