Method, device and medium for simulating wafer processing process

Abstract

The embodiment of the invention provides a method, equipment and medium for simulating a wafer processing process. In the method, aiming at a moment in an electrochemical deposition process of a wafer, based on a deposition state of the wafer, a target processing stage to be carried out on the wafer at the moment is determined from a plurality of processing stages of the electrochemical deposition process. And simulating the target processing stage based on the feature structure information of the wafer and the process parameters related to the electrochemical deposition process so as to determine a simulation result corresponding to the moment and aiming at the electrochemical deposition speed. And determining a target parameter value of the process parameter based on the plurality of simulation results respectively determined for the plurality of moments.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of integrated circuits, and more specifically, to methods, devices, and media for simulating wafer processing Background Art

[0002] Electrochemical deposition is a technique that promotes the deposition of substances from an electrolyte onto an electrode by applying an electric field to the electrode surface, and is widely used in fields such as the microelectronics industry, materials science, and semiconductor manufacturing. Electrochemical deposition simulation plays an important role in wafer fabrication, and can improve the reliability, efficiency, and cost-effectiveness of the process. However, there are some problems with current electrochemical deposition techniques that affect the deposition effect. Summary of the Invention

[0003] In a first aspect of the present disclosure, a method for simulating a wafer processing process is provided. In this method, for a moment during the electrochemical deposition process of a chip, based on the deposition state of the chip, a target processing stage to be performed on the chip at this moment is determined from multiple processing stages of the electrochemical deposition process; based on the characteristic structure information of the chip and process parameters related to the electrochemical deposition process, the target processing stage is simulated to determine a simulation result for the electrochemical deposition rate corresponding to this moment; and based on multiple simulation results respectively determined for multiple moments, a target parameter value of the process parameters is determined.

[0004] In some embodiments, the target processing stages include a channel filling stage and a channel overfilling stage, and simulating the target processing stage includes: For a target region among multiple regions of the chip, Based on the characteristic structure information corresponding to the target region at this moment, a time evolution factor for the process parameters is determined, and the time evolution factor indicates the influence of the previous moment on this moment; Based on the time evolution factor, a correction coefficient for the process parameters, and the parameter value of the process parameters at the previous moment, the parameter value of the process parameters at this moment is determined; Based on the parameter value of the process parameters at this moment, the target processing stage is simulated to obtain a regional simulation result for the electrochemical deposition rate of the target region; and Based on multiple regional simulation results respectively determined for multiple regions, a simulation result corresponding to this moment is determined.

[0005] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform the method according to the first aspect of the present disclosure.

[0006] In a third aspect of the present disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0007] It will be understood from the following description that, according to embodiments of the present disclosure, based on the deposition state of the chip, the processing stage to be performed on the chip at each moment is determined. Subsequently, the corresponding processing stage is simulated based on the characteristic structure information and process parameters of the chip. Thereby, the accuracy of the simulation of the corresponding processing stage is improved. In addition, based on each simulation result, the target parameter value of the process parameter is determined, improving the accuracy of the determined process parameter. Further, using the target parameter value of the determined process parameter for electrochemical deposition of the chip can improve the quality of the chip. Other benefits will be described in conjunction with the corresponding embodiments below.

[0008] It should be understood that the content described in the present invention content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where: Figure 1 A schematic diagram of an example environment in which the embodiments of the present disclosure can be implemented is shown; Figure 2 A flowchart for simulating a chip processing process according to some embodiments of the present disclosure is shown; Figure 3 A schematic diagram of an electrochemical deposition surface topography according to some embodiments of the present disclosure is shown; Figure 4 A schematic diagram of an example architecture of multiple simulation models according to some embodiments of the present disclosure is shown; Figure 5A A flowchart of a process for determining a correction coefficient for a process parameter according to some embodiments of the present disclosure is shown; Figure 5B Another flowchart of a process for determining a correction coefficient for a process parameter according to some embodiments of the present disclosure is shown; Figure 5C Yet another flowchart of a process for determining a correction coefficient for a process parameter according to some embodiments of the present disclosure is shown; Figure 6 Another flowchart for simulating a chip processing process according to some embodiments of the present disclosure is shown; and Figure 7 A block diagram of a server or electronic device in which one or more embodiments of the present disclosure may be implemented is shown. Detailed implementation manners

[0010] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not used to limit the protection scope of the present disclosure.

[0011] In the description of the embodiments of the present disclosure, the term "including" and its like should be understood as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0012] Figure 1 A schematic diagram of an example environment 100 in which the embodiments of the present disclosure can be implemented is shown. The example environment 100 may generally include an electronic device 110. The electronic device 110 can be used to simulate a wafer processing process. For example, the electronic device 110 can be used to generate a wafer processing model 120 or update the wafer processing model 120. In this document, the wafer processing process may be an electrochemical deposition process. The wafer processing model 120 can be used to simulate or mimic the electrochemical deposition process. The wafer processing model 120 can be initialized in any manner. For example, the wafer processing model 120 can perform an electrochemical deposition process simulation on a target wafer 130 to be processed to obtain a (simulated) processed target wafer 132. In some embodiments, a certain wafer may include multiple chips, and processing a certain wafer using the wafer processing model 120 may include processing a certain chip on the wafer using the wafer processing model 120.

[0013] In some embodiments, the electronic device 110 may generate or update the wafer processing model 120 based on a set of measurement parameter information of the target wafer (e.g., measurement parameter information 102-1, 102-2...) and a set of simulation parameter information (e.g., simulation parameter information 104-1, 104-2...). Generating or updating the wafer processing model 120 refers to determining or updating the respective parameters of the wafer processing model 120. A set of measurement parameter information may be parameter information determined by actually processing the target wafer, such as the channel height and non-channel height obtained by performing electrochemical deposition processing and then measuring the topography of the processed target wafer. A set of simulation parameter information may be parameter information of the wafer obtained by simulating the processing of the target wafer using the wafer processing model 120.

[0014] In some embodiments, the electronic device 110 may be communicatively connected to a wafer processing platform, such as an electrochemical deposition platform. The electronic device 110 may also be communicatively connected to various positions on the wafer processing platform or one or more sensors adjacent to the wafer processing platform. The wafer processing platform may actually process the wafer and transmit a set of measurement parameter information to the electronic device 110.

[0015] In some embodiments, the electronic device 110 may also be communicatively connected to the electrochemical deposition platform and control the electrochemical deposition platform to process the wafer (e.g., encapsulation). The electronic device controls the electrochemical deposition platform to perform polishing work on the surface of the target wafer 130 to achieve wafer processing. The electrochemical deposition operation may include more than one deposition stage. Exemplarily, the multiple deposition stages may include a channel filling stage, a channel overfill stage, and a horizontal filling stage.

[0016] The electronic device 110 may determine the process parameter values ultimately used for the wafer processing platform, such as the electrochemical deposition platform, based on the process parameter values of the obtained or updated wafer processing model 120. These process parameter values may include the values of the respective process parameters for the multiple stages of electrochemical deposition.

[0017] In the exemplary environment 100, the electronic device 110 can be any type of computing device, including a terminal device or a server device. The terminal device can be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / video camera, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device can, for example, include a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and so on.

[0018] It should be understood that the structure and function of the environment 100 are described only for exemplary purposes, without implying any limitation on the scope of the present disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings.

[0019] As briefly mentioned above, electrochemcial deposition technology, as a core technology in semiconductor manufacturing and the microelectronics industry, the accuracy of its process parameters directly determines the performance and reliability of the chip. During the electrochemcial deposition process, the high aspect ratio of the channel region in the chip easily leads to problems such as void filling, uneven electric field distribution, or uneven distribution of additives (e.g., inhibitors or promoters, etc.), thus affecting the quality of the chip after electrochemcial deposition treatment. To further improve the quality of the chip, it is necessary to simulate the electrochemcial deposition process and detect defects.

[0020] Currently, the simulation methods for electrochemcial deposition simulation mainly include numerical simulation, level set function simulation, and semi-empirical physical formula simulation. The simulation efficiency of numerical simulation and level set function simulation is relatively low. Facing full-chip scale and complex structure simulation, it is difficult to complete the simulation within an effective time. Although semi-empirical physical formula simulation has the ability to predict the surface topography of full-chip chemical deposition, its calculation accuracy is relatively low. Therefore, how to more accurately simulate the chip processing process is an urgent problem to be solved by those skilled in the art.

[0021] To this end, embodiments of the present disclosure provide a method for layout processing to solve or at least partially solve the above problems and / or other potential problems in traditional methods. According to embodiments of the present disclosure, for a moment among multiple moments in the electrochemical deposition process of a chip, based on the deposition state of the chip, a target processing stage to be performed on the chip at this moment is determined from multiple processing stages of the electrochemical deposition process. Based on the characteristic structure information of the chip and process parameters related to the electrochemical deposition process, the target processing stage is simulated to determine the simulation result for the electrochemical deposition rate corresponding to this moment. Based on multiple simulation results respectively determined for multiple moments, the target parameter value of the process parameters is determined.

[0022] In this way, based on the deposition state of the chip, the processing stage to be performed on the chip at each moment is determined. Subsequently, the corresponding processing stage is simulated based on the characteristic structure information of the chip and process parameters. Thereby, the accuracy of the simulation of the corresponding processing stage is improved. In addition, based on each simulation result, the target parameter value of the process parameters is determined, improving the accuracy of the determined process parameters. The target parameter value of the process parameters is used to perform electrochemical deposition on the chip. In this way, in view of the more accurate determined process parameters, the quality of the chip can be improved.

[0023] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0024] In some embodiments, during the process of performing electrochemical deposition on a chip, the electronic device 110 can use the chip processing model 120 to simulate the deposition process of the chip to obtain the simulation result for the morphology of the chip. Exemplarily, for each moment among multiple moments in the electrochemical deposition process of the chip, the electronic device 110 can determine the simulation result for the electrochemical deposition rate at each moment through the chip processing model, and further determine the simulation result for the morphology of the chip.

[0025] In some embodiments, the process of performing electrochemical deposition on a chip can be divided into multiple stages based on the effect of the electrochemical deposition. Exemplarily, the electrochemical deposition process can include at least one of a channel filling stage, a channel overfilling stage, or a horizontal filling stage. In the channel filling stage, the channel region on the chip is filled using the electrochemical deposition technique so that the channel is completely filled with metal. In the channel overfilling stage, an additional layer is deposited above the channel using the electrochemical deposition technique to facilitate protecting the filled structure in the trench in subsequent processes (e.g., chemical mechanical polishing process). In the horizontal filling stage, deposition is performed above the non-channel region and the already filled channel region using the electrochemical deposition technique to form a uniform horizontal layer on the chip surface, further improving the flatness and electrical performance of the device.

[0026] In some embodiments, at the end of each deposition stage, the electronic device 110 may determine the subsequent stage to be performed based on the deposition effect of the deposition stage and the process requirements. Exemplarily, at the end of the channel filling stage, if pores are detected in the channel region, enter the channel overfill stage. Otherwise, enter the horizontal filling stage.

[0027] Figure 2 FIG. 4 shows a flowchart of a process 200 for simulating a chip processing process according to some embodiments of the present disclosure. As Figure 2 shown, the process 200 may be implemented or included at the electronic device 110. It should be understood that the process 200 may further include additional blocks not shown and / or certain (or some) of the shown blocks may be omitted, and the scope of the present disclosure is not limited in this regard.

[0028] In some embodiments, the process parameters corresponding to different filling stages are not the same. In order to more accurately simulate the deposition state of the chip, different simulation models may be used to simulate different filling stages. In some embodiments, the target processing stage includes a channel filling stage and a channel overfill stage, and simulating the target processing stage includes: for a target region among a plurality of regions of the chip, based on the characteristic structure information corresponding to the target region at this moment, determining a time evolution factor for the process parameters, where the time evolution factor indicates the influence of the previous moment on this moment. Based on the time evolution factor, a correction coefficient for the process parameters, and the parameter value of the process parameters at the previous moment, determining the parameter value of the process parameters at this moment. Based on the parameter value of the process parameters at this moment, simulating the target processing stage to obtain a regional simulation result of the electrochemical deposition rate for the target region. Based on the plurality of regional simulation results respectively determined for the plurality of regions, determining the simulation result corresponding to this moment.

[0029] As Figure 2 shown, at block 210, during the electrochemical deposition process for the wafer, the electronic device 110 may first obtain the deposition state of the target chip 130 to be processed. The deposition state indicates the deposition effect of the channel region on the chip. Figure 3 FIG. 5 shows a schematic diagram of an electrochemical deposition surface topography 300 according to some embodiments of the present disclosure. As Figure 3As shown, the chip includes a channel region 311 and a non-channel region 312. During the deposition process, metal ions are deposited on the bottom 314 of the channel region 311, the sidewalls 313 of the channel region 311, and the non-channel region 312. Exemplarily, the deposition state may include the deposition thickness at the bottom of the channel region, the deposition thickness on the sidewalls of the channel region, and the filling thickness of the non-channel region, etc. During the deposition process, the processing stage corresponding to the current moment can be determined based on the deposition state of the chip. For example, if the deposition thickness on the sidewalls of the channel region is lower than the first deposition thickness threshold, it indicates that the current stage is the channel filling stage. If the deposition thickness on the sidewalls of the channel region exceeds the first deposition thickness threshold and the deposition thickness of the non-channel region is lower than the second deposition thickness threshold, it indicates that the current stage is the channel overfill stage.

[0030] In some embodiments, the electronic device 110 can simulate the target processing stage based on the characteristic structure information of the chip and the process parameters related to the electrochemical deposition process to determine the simulation result of the electrochemical deposition rate corresponding to this moment. The characteristic structure information of the chip can refer to any suitable information representing or describing the characteristic structure of the chip. The characteristic structure of the chip can refer to the structure of the target type or the structure of the type of interest in the chip. The characteristic structure can include but is not limited to the channels in the chip. For example, the characteristic structure information of the chip can include the channel density on the chip (i.e., the area ratio occupied by the channel region), the perimeter of the channel region, the number of channels, the channel width, and the deposition thickness on the sidewalls of the channel, etc. The process parameters can include parameters related to process conditions or machine settings, such as deposition time, deposition rate, initial coverage rate of the promoter, and initial coverage rate of the inhibitor, etc.

[0031] In some embodiments, in order to simulate the electrochemical deposition process of the chip more accurately, different simulation models can be used to simulate different stages of the electrochemical deposition process. Figure 4 The schematic diagram of an example architecture 400 of multiple simulation models according to some embodiments of the present disclosure is shown. As Figure 4 shown, the architecture 400 may include a first simulation model 440-1 for simulating the channel filling stage 410, a second simulation model 440-2 for simulating the channel overfill stage 420, and a third simulation model 440-3 for simulating the horizontal filling stage 430, which can be individually or collectively referred to as the simulation model 440. In some embodiments, the simulation model 440 can be a semi-empirical physical model, characterizing the relationship between the process parameters for electrochemical deposition on the chip and the characteristic structure information of the chip to describe the different morphologies generated on the chip after electrochemical deposition due to different metal wire distributions.

[0032] At block 220, if it is determined that the processing stage for the channel at the current moment is the channel filling stage, the electronic device 110 may simulate the channel overcharge state based on the feature structure information to obtain a plurality of first simulation results. Exemplarily, the electronic device 110 may utilize the first simulation model 440-1 to simulate the target processing stage based on the feature structure information of the chip and the process parameters related to the electrochemical deposition process. In some embodiments, the electronic device 110 may divide the chip into grids based on the layout information of the chip to determine a plurality of regions related to the chip.

[0033] For a target region among the plurality of regions of the chip, based on the feature structure information corresponding to the target region at that moment, determine a time evolution factor for the process parameters, where the time evolution factor indicates the influence of the previous moment on the current moment. At time t, the channel perimeter corresponding to the target region can be determined by the following method: (1) Where is the channel perimeter of the target region at the initial moment, is the perimeter of the target region at time t, is the thickness of the sidewall of the target region at time t, and N is the number of trenches in the target region.

[0034] The channel density corresponding to the target region can be determined by the following method: (2) Where is the channel density of the target region at time t, is the channel density of the target region at the initial moment, is the area of the target region.

[0035] In some embodiments, the promoter coverage rate and inhibitor coverage rate at the current moment may be determined based on the initial promoter coverage rate, initial inhibitor coverage rate, and feature structure information, so as to determine the metal ion deposition rate at the current moment.

[0036] During the channel filling stage and channel overcharge stage, the promoter coverage rate and inhibitor coverage rate can be determined by the following method: (3) (4) Where , represent the coverage rates of the promoter and inhibitor at the next moment at the bottom of the channel, sidewall of the channel, and non-trench region, , represent the coverage rates of the promoter and inhibitor at the current moment at the bottom of the channel, sidewall of the channel, and non-trench region, is a dimensionless optimizable parameter (i.e., correction coefficient), is the coverage rate of the promoter at the initial moment. is an optimizable coefficient (i.e., correction coefficient), is a time evolution factor, which can be determined by the following method: (5) where the deposition rate at time t is , is the initial deposition rate, is the initial coverage rate of the inhibitor, is the initial coverage rate of the promoter, and k is a coefficient.

[0037] In the calculation method of the promoter coverage rate shown in formula (3), the time evolution factor can be a coverage rate coefficient. As shown in formula (5), the electronic device 110 can determine the initial value of the time evolution factor based on the initial characteristic structure of the target area. For example, the initial characteristic structure can include the initial density of the channel, the initial perimeter of the channel area, the initial number of channels, and the initial width of the channel, etc. Subsequently, the electronic device 110 can determine the value of the time evolution factor at this moment based on the initial value and at least one area simulation result corresponding to at least one previous moment at this moment. In some embodiments, the area simulation result can include the simulation result of the deposition thickness (or deposition speed) of the channel area (for example, the deposition thickness of the channel sidewall, the deposition thickness of the channel bottom), and can also include the simulation result of the deposition thickness of the non-channel area. As shown in the above formulas (1) and (2), in the channel filling stage, the time evolution factor can be determined based on the difference between the initial value and at least one area simulation result. Exemplarily, for a certain moment during the deposition process, the corresponding area simulation result at this moment includes at least the deposition thickness of the channel sidewall . It can be seen from the above formula (5) that based on the channel perimeter , channel density at this moment and the channel perimeter and channel density at the previous moment, the time evolution factor corresponding to this moment can be determined. As shown in formula (1), the channel perimeter at this moment can be determined based on the sum of the initial channel perimeter and the area simulation result (for example, the deposition thickness of the channel sidewall) at this moment. As shown in formula (2), the channel density at this moment can be determined based on the sum of the initial channel density and the area simulation result (for example, the deposition thickness of the channel sidewall) at this moment.

[0038] At block 230, the electronic device 110 determines whether the channel is filled. If it is filled, it proceeds to block 240 to simulate the overcharge state of the channel based on the feature structure information to obtain a plurality of second simulation results. During the channel overcharge stage, the thickness of metal ions in the channel is greater than that in the non-channel region, and the deposition state of the metal ions changes. The time evolution factor can be determined in the following manner: (6) (7) As shown in formulas (6) and (7), the time evolution factor can be determined based on the sum of the initial value and at least one regional simulation result. As shown in formula (6), the channel perimeter at this moment can be determined based on the sum of the initial channel perimeter and the regional simulation result at this moment (e.g., the deposition thickness of the channel sidewall). As shown in formula (7), the channel density at this moment can be determined based on the sum of the initial channel density and the regional simulation result at this moment (e.g., the deposition thickness of the channel sidewall).

[0039] In some embodiments, the time evolution factors corresponding to the channel sidewall and the channel bottom are not the same. Exemplarily, the time evolution factor can include a first time evolution factor corresponding to the channel sidewall of the target region or a second time evolution factor corresponding to the channel bottom of the target region. In some embodiments, the first time evolution factor can be 1, and the second time evolution factor can be as shown in formula (5). In this case, the promoter coverage rate at the channel bottom can be determined in the following manner: (8) where is the promoter coverage rate at the channel bottom at time t + 1, is the promoter coverage rate at the channel bottom at time t.

[0040] In some embodiments, the electronic device 110 can determine the parameter value of the process parameter at this moment (e.g., the parameter value of the promoter coverage rate at this moment or the parameter value of the inhibitor coverage rate at this moment, etc.) based on the time evolution factor, the correction coefficient for the process parameter, and the parameter value of the process parameter at the previous moment. Subsequently, based on the parameter value of the process parameter at this moment, the target processing stage is simulated to obtain a regional simulation result of the electrochemical deposition rate for the target region. In some embodiments, the regional simulation result can be the deposition rate of this region at the current moment, e.g., the electrochemical deposition rate at time t . The regional simulation result can be the deposition thickness in this region at the current moment. The deposition thickness of the target region can be determined in the following manner: (9) wherein is the deposition thickness at the previous moment, is the deposition thickness at the current moment.

[0041] In some embodiments, the electronic device 110 may determine the simulation result corresponding to this moment based on multiple regional simulation results respectively determined for multiple regions. In some embodiments, the determined simulation result may be the average deposition rate of each region on the chip at the current moment, or the average deposition thickness of each region on the chip at the current moment.

[0042] In some embodiments, the target processing stage may include a horizontal filling stage. At block 250, the electronic device 110 determines whether the channel is overcharged. If overcharged, it proceeds to block 260. At block 260, the horizontal filling state is simulated based on the feature structure information to obtain multiple third simulation results. For the target region among the multiple regions of the chip, the electronic device 110 may determine the regional simulation result corresponding to this moment for the target region based on the regional simulation result corresponding to the moment when the previous stage of the horizontal filling stage ends for the target region and the correction coefficient for the process parameters. Based on the multiple regional simulation results respectively determined for multiple regions, the simulation result corresponding to this moment is determined. The regional simulation result for the target region may be determined by the following method: (10) wherein is the metal ion deposition rate corresponding to the end moment of the previous stage of the horizontal filling stage (for example, the channel overcharging stage). is the end moment of the previous stage of the horizontal filling stage, is the dimensionless correction coefficient.

[0043] In some embodiments, the electronic device 110 determines the target parameter value of the process parameter based on multiple simulation results respectively determined for multiple moments. The target parameter value is the process parameter value used for actual chip production. The electronic device 110 may determine the topography simulation result for the chip based on multiple simulation results. Exemplarily, the topography simulation result may include the simulation result of the deposition thickness for the non-channel region on the chip and the simulation result of the deposition thickness for the channel region on the chip. Subsequently, the electronic device 110 may update the process parameter to determine the target parameter value based on the difference between the topography simulation result and the topography reference result, and the topography reference result includes the channel reference height and the non-channel reference height. The topography reference result may include the channel design height and the non-channel design height of the chip, or the measured height of the channel region of the chip and the measured height of the non-channel region, etc. In some embodiments, the target parameter value of the process parameter may be determined based on an empirical model, or determined using other machine learning models, which is not limited herein.

[0044] In the above embodiments, the multiple simulation models 440 are used to simulate the electrochemical deposition process and update the process parameters of the chip based on the simulation results to improve the quality of the chip during production. As described above, there are some correction factors in Formulas (1) to (10). To further improve the accuracy of the simulation model 440, the correction factors can be optimized.

[0045] Figure 5A FIG. shows a flowchart of a process 500A for determining correction factors for process parameters according to some embodiments of the present disclosure. As Figure 5A shown, at block 510, the electronic device 110 first obtains a plurality of training feature structure information related to the chip. Each piece of training feature structure information in the plurality of training feature structure information can be for a certain chip or a certain area to be processed in the chip.

[0046] In some embodiments, the electronic device 110 can define an optimization target and constraint conditions according to the simulation model 440 to be optimized. The optimization target is the deposition thickness of metal ions in the channel region and the non-channel region in the training feature structure information. The constraint condition is the value range of each correction factor to be optimized. Each parameter needs to be adjusted in a predefined search space to make the objective function reach the optimal value.

[0047] At block 511, the electronic device 110 generates a first set of parameter sets based on the initial values of the correction factors. The parameter sets in the first set of parameter sets include the corresponding coefficient values of a plurality of correction factors. For a certain area to be processed in the chip, a set of initial populations (i.e., the first set of parameter sets) is randomly generated, that is, a combination of all correction factors to be optimized. The ways to obtain the initial population include, but are not limited to, the full orthogonal method, the Taguchi experiment method, the response surface method, the random method, etc. The number of populations can be set according to the specific parameters to be optimized. Generally, the more parameters need to be optimized, the larger the population size. It should be noted that the initial value of each parameter should be within the search space of the parameter.

[0048] At block 512, the electronic device 110 performs combination operations and mutation operations on the parameter sets in the first set of parameter sets using a genetic algorithm to generate a second set of parameter sets. Figure 5B FIG. shows another flowchart of a process 500B for determining correction factors for process parameters according to some embodiments of the present disclosure. As Figure 5BAs shown, at block 520, the electronic device 110 can simulate each parameter combination (i.e., each parameter set) in the first set of parameter sets to determine the training simulation results corresponding to the respective parameter sets. At block 521, for each parameter combination (i.e., each parameter set in the second set of parameter sets), the electronic device 110 can use an objective function to determine the fitness based on the difference between the training simulation results and the reference simulation results. The value of the fitness is related to the true solution that the objective function needs to achieve. In this example, specifically, it refers to the deposition thickness of metal ions in the channel region and non-channel region after the electrochemical deposition process. For each parameter set, the electronic device 110 can determine the root mean square error between the measured value (i.e., the reference value of the electrochemical deposition morphology of the chip) corresponding to the parameter set and the simulated value (i.e., the simulation result of the electrochemical deposition morphology of the chip) to determine the fitness corresponding to the parameter set. The smaller the root mean square error, the greater the fitness of the parameter set.

[0049] At block 522, the electronic device 110 can determine the elite individuals based on the multiple fitness values determined for the multiple training simulation results. During the process of optimizing the correction coefficient, an individual refers to a certain parameter set in a set of parameter sets, and the elite individuals are the parameter sets whose fitness exceeds the fitness threshold among the multiple parameter sets. The methods for selecting elite individuals include, but are not limited to, roulette wheel selection, tournament selection, etc. Based on the above methods, the optimal individual is obtained from the current population to generate a new second set of parameter sets. In some embodiments, the electronic device 110 can perform individual crossover based on the selected elite individuals to generate new individuals. The crossover operation is to take out some parameters from two individuals for combination to generate a new solution. This process can explore new regions of the solution space. At the same time, random fluctuations of parameters (i.e., mutation operation) are performed on the elite individuals, aiming to increase the diversity of the solution space. The mutation operation helps to avoid falling into local optimal solutions.

[0050] At block 523, the electronic device 110 can determine whether the population iteration count of the genetic algorithm exceeds the first threshold number. If it does not exceed the first threshold number, the steps shown in blocks 520 to 523 above are continued. At block 524, if the electronic device 110 determines that the population iteration count exceeds the first threshold number, it obtains the globally superior individual.

[0051] At block 513, the electronic device 110 obtains the globally superior individual. At block 514, the electronic device 110 uses the Monte Carlo search tree algorithm to optimize the correction coefficient. Figure 5CAnother flowchart of process 500C for determining a correction factor for process parameters according to some embodiments of the present disclosure is shown. Exemplarily, after the genetic algorithm iterates for several generations, at block 530, the electronic device 110 may select multiple sets of optimal (or relatively optimal parameter combinations) as the starting nodes of the Monte Carlo search tree algorithm. Subsequently, at block 531, the electronic device 110 may use the Monte Carlo search tree algorithm to expand the tree starting from the current solution. The Monte Carlo search tree algorithm evaluates the quality of the solution by simulating possible future parameter combination configurations. Each tree node represents a parameter combination, and the child nodes represent possible next optimal solutions. At block 532, the electronic device 110 may perform a Monte Carlo simulation at each tree node. During the simulation process, the quality of the node is evaluated according to the root mean square difference between the simulated deposition thickness and the measured value, and the expected value of each node is updated by backtracking according to the simulation results. At block 533, through continuous simulation and backtracking, the electronic device 110 may expand and select the optimal path through the Monte Carlo search tree algorithm. At block 534, the electronic device 110 may obtain a locally optimal individual based on the selected optimal path.

[0052] At block 515, the electronic device 110 may obtain a locally optimal individual to determine a third set of parameter sets.

[0053] At block 516, the electronic device 110 may determine whether the coefficient value in the second set of parameter sets is less than the root mean square difference threshold. If it is less than the root mean square difference threshold, the coefficient value of the correction factor is updated; otherwise, the process of updating the correction factor using the genetic algorithm and the Monte Carlo search tree algorithm (i.e., the steps shown in blocks 512 to 516) is continued. In some embodiments, through repeated alternating optimization of the genetic algorithm and the Monte Carlo search tree algorithm, the global optimal solution is obtained by utilizing the global search characteristics of the genetic algorithm for crossover and mutation, and the local optimal solution is obtained by combining the local refinement optimization characteristics of the Monte Carlo search tree algorithm for each candidate solution. Through multi-generation evolution, the optimal parameter combination is finally found. The optimization termination condition may stop the optimization by setting the number of iterations or the root mean square difference threshold, etc., to obtain a set of optimal solutions corresponding to the objective function.

[0054] At block 517, the electronic device 110 may update the coefficient value of the correction factor based on the coefficient value in the third set of parameter sets.

[0055] In some embodiments, the above-described alternating optimization method of the genetic algorithm and the Monte Carlo search tree algorithm can also be used to determine the target parameter values of process parameters based on multiple simulation results. Exemplarily, the electronic device 110 can determine an initial population for the genetic algorithm based on the initial values of the process parameters. Subsequently, the electronic device 110 performs crossover operations or mutation operations on the individuals in the initial population to obtain multiple candidate solutions. Subsequently, the electronic device 110 performs local refinement optimization on each candidate solution in combination with the Monte Carlo search tree algorithm to obtain local optimal solutions. Through multiple generations of evolution, the optimal target parameter values for determining the process parameters are finally found.

[0056] Figure 6 FIG. shows another flowchart of a process 600 for simulating a chip processing process according to some embodiments of the present disclosure. As Figure 6 shown, the process 600 can be implemented at the electronic device 110. Reference is made below to Figure 1 to describe the process 600.

[0057] As Figure 6 shown, at block 610, the electronic device 110 determines, based on the deposition state of the chip, the target processing stage to be performed on the chip at this moment from among multiple processing stages of the electrochemical deposition process for the moment during the electrochemical deposition process of the chip.

[0058] At block 620, the electronic device 110 simulates the target processing stage based on the characteristic structure information of the chip and process parameters related to the electrochemical deposition process to determine the simulation result for the electrochemical deposition rate corresponding to this moment.

[0059] In some embodiments, the target processing stage includes a channel filling stage and a channel overfill stage, and simulating the target processing stage includes: for a target region among multiple regions of the chip, determining a time evolution factor for the process parameters based on the characteristic structure information corresponding to the target region at this moment, where the time evolution factor indicates the influence of the previous moment of this moment; determining the parameter value of the process parameters at this moment based on the time evolution factor, a correction coefficient for the process parameters, and the parameter value of the process parameters at the previous moment; simulating the target processing stage based on the parameter value of the process parameters at this moment to obtain a regional simulation result for the electrochemical deposition rate of the target region; and determining the simulation result corresponding to this moment based on the multiple regional simulation results respectively determined for multiple regions.

[0060] In some embodiments, determining the time evolution factor of the target region includes: determining an initial value of the time evolution factor based on the initial characteristic structure of the target region; and determining the value of the time evolution factor at this moment based on the initial value and at least one regional simulation result respectively corresponding to at least one previous moment of this moment.

[0061] In some embodiments, determining the parameter value of the time evolution factor at this moment is based on at least one of the following: the sum of the initial value and at least one regional simulation result, or the difference between the initial value and at least one regional simulation result.

[0062] In some embodiments, the time evolution factor includes at least one of the following: a first time evolution factor corresponding to the channel sidewall of the target region, or a second time evolution factor corresponding to the channel bottom of the target region.

[0063] In some embodiments, the target processing stage includes a horizontal filling stage, and simulating the target processing stage includes: for the target region among multiple regions of the chip, determining the regional simulation result corresponding to this moment for the target region based on the regional simulation result corresponding to the moment when the previous stage of the horizontal filling stage ends for the target region and the correction coefficient for the process parameters; and determining the simulation result corresponding to this moment based on the multiple regional simulation results respectively determined for the multiple regions.

[0064] At block 630, the electronic device 110 determines the target parameter value of the process parameters based on the multiple simulation results respectively determined for multiple moments.

[0065] In some embodiments, determining the target parameter value of the process parameters includes: based on the multiple simulation results, determining the topography simulation result for the chip, the topography simulation result including the channel simulation height and the non-channel simulation height; and updating the process parameters based on the difference between the topography simulation result and the topography reference result to determine the target parameter value, the topography reference result including the channel reference height and the non-channel reference height.

[0066] In some embodiments, the correction coefficient for the process parameters used in the simulation is determined by the following method: based on the initial value of the correction coefficient, generating a first set of parameter sets, where the parameter sets in the first set of parameter sets include the coefficient values of the correction coefficient; generating a second set of parameter sets through the combination operation and mutation operation of the coefficient values of the correction coefficient in the first set of parameter sets; and updating the coefficient value of the correction coefficient based on the coefficient values in each parameter set in the second set of parameter sets until the number of updates exceeds the threshold number.

[0067] In some embodiments, updating the coefficient value of the correction coefficient includes: determining a plurality of training simulation results based on a second set of parameter sets, where the training simulation results in the plurality of training simulation results include simulation values of the electrochemical deposition morphology of the chip; determining the corresponding quality of the parameter values in the second set of parameter sets based on the difference between the plurality of training simulation results and the corresponding reference simulation results, where the reference simulation results include reference values of the electrochemical deposition morphology of the chip; updating the coefficient value in the second set of parameter sets using the Monte Carlo search tree algorithm based on the quality to determine a third set of parameter sets; and updating the coefficient value of the correction coefficient based on the coefficient value in the third set of parameter sets.

[0068] Figure 7 FIG. shows a block diagram of a server or electronic device 700 in which one or more embodiments of the present disclosure may be implemented. The electronic device 700 may be used, for example, to implement an electronic device 110 as shown in Figure 1 It should be understood that Figure 7 The electronic device 700 shown is merely exemplary and should not impose any limitation on the functions and scope of the embodiments described herein.

[0069] As Figure 7 shown, the electronic device 700 is in the form of a general-purpose electronic device. The components of the electronic device 700 may include, but are not limited to, one or more processors 710 or processing units, a memory 720, a storage device 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. The processing unit may be an actual or virtual processor and is capable of performing various processes according to the programs stored in the memory 720. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing ability of the electronic device 700.

[0070] The electronic device 700 generally includes multiple computer storage media. Such media may be any accessible media available to the electronic device 700, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 720 may be volatile memory (such as registers, caches, random access memory (RAM)), non-volatile memory (such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 730 may be removable or non-removable media and may include machine-readable media, such as a flash drive, a magnetic disk, or any other medium that can be used to store information and / or data (such as training data for training) and can be accessed within the electronic device 700.

[0071] The electronic device 700 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown inFigure 7 As shown, a disk drive for reading from and writing to a removable, non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading from and writing to a removable, non-volatile optical disk can be provided. In these cases, each drive can be connected to a bus (not shown) by one or more data medium interfaces. Memory 720 can include a computer program product 725 having one or more program modules configured to perform the various methods or acts of the various embodiments of the present disclosure.

[0072] Communication unit 740 enables communication with other electronic devices via a communication medium. Additionally, the functions of the components of electronic device 700 can be implemented by a single computing cluster or multiple computer machines capable of communicating via a communication link. Thus, electronic device 700 can operate in a networked environment using a logical connection to one or more other servers, network personal computers (PCs), or another network node.

[0073] Input device 750 can be one or more input devices such as a mouse, keyboard, trackball, etc. Output device 760 can be one or more output devices such as a display, speaker, printer, etc. Electronic device 700 can also communicate with one or more external devices (not shown) as needed via communication unit 740, external devices such as storage devices, display devices, etc., communicate with one or more devices that enable a user to interact with electronic device 700, or communicate with any device that enables electronic device 700 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication can be performed via an input / output (I / O) interface (not shown).

[0074] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, and the one or more computer instructions are executed by a processor to implement the method described above.

[0075] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0076] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processing unit of the computer or other programmable data processing apparatus, result in an apparatus that implements the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions that implement various aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0077] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other devices implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0078] The flowchart and block diagram in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart, and combinations of blocks in the block diagrams and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0079] The various implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The choice of terms used herein is intended to best explain the principles of the implementations, the practical application, or improvements made to the technology in the marketplace, or to enable other ordinary skill in the art to understand the implementations disclosed herein.

Claims

1. A method for simulating a wafer processing process, comprising: At a moment of the electrochemical deposition process of a chip, Based on the deposition state of the chip, determine the target processing stage to be performed on the chip at this moment from multiple processing stages of the electrochemical deposition process; Based on the characteristic structure information of the chip and process parameters related to the electrochemical deposition process, simulate the target processing stage to determine the simulation result for the electrochemical deposition rate corresponding to this moment; And Based on multiple simulation results respectively determined for multiple such moments, determine the target parameter value of the process parameters.

2. The method according to claim 1, characterized in that, The target processing stage includes a channel filling stage and a channel overfilling stage, and simulating the target processing stage includes: For a target area among multiple areas of the chip, Based on the characteristic structure information corresponding to the target area at this moment, determine the time evolution factor for the process parameters, and the time evolution factor indicates the influence of the previous moment of this moment; Based on the time evolution factor, the correction coefficient for the process parameters, and the parameter value of the process parameters at the previous moment, determine the parameter value of the process parameters at this moment; Based on the parameter value of the process parameters at this moment, simulate the target processing stage to obtain the regional simulation result of the electrochemical deposition rate for the target area; and Based on multiple regional simulation results respectively determined for multiple such areas, determine the simulation result corresponding to this moment.

3. The method according to claim 2, characterized in that, Determining the time evolution factor of the target area includes: Based on the initial characteristic structure of the target area, determine the initial value of the time evolution factor; Based on the initial value and at least one regional simulation result respectively corresponding to at least one previous moment of this moment, determine the value of the time evolution factor at this moment.

4. The method according to claim 3, characterized in that, Determining the parameter value of the time evolution factor at this moment is based on at least one of the following: The sum of the initial value and the at least one regional simulation result, or The difference between the initial value and the at least one regional simulation result.

5. The method according to claim 2, wherein The time evolution factor includes at least one of the following: The first time evolution factor corresponding to the channel sidewall of the target area, or The second time evolution factor corresponding to the channel bottom of the target area.

6. The method according to claim 1, wherein The target processing stage includes a horizontal filling stage, and simulating the target processing stage includes: For a target area among multiple areas of the chip, based on the regional simulation result corresponding to the moment when the previous stage of the horizontal filling stage ends for the target area and the correction coefficient for the process parameters, determine the regional simulation result corresponding to this moment for the target area; and Based on multiple regional simulation results respectively determined for multiple such areas, determine the simulation result corresponding to this moment.

7. The method according to claim 1, characterized in that, Determining the target parameter value of the process parameters includes: Based on the multiple simulation results, determine the topography simulation result for the chip, and the topography simulation result includes the channel simulation height and the non-channel simulation height; and Based on the difference between the topography simulation result and the topography reference result, update the process parameters to determine the target parameter value, where the topography reference result includes the channel reference height and the non-channel reference height.

8. The method according to claim 1, characterized in that The correction factor for the process parameters used in the simulation is determined by the following method: Based on the initial value of the correction factor, generate a first set of parameter sets, where the parameter sets in the first set of parameter sets include the coefficient values of the correction factor; Generate a second set of parameter sets through the combination operation and mutation operation of the coefficient values of the correction factor in the first set of parameter sets; And Based on the coefficient values in each parameter set in the second set of parameter sets, update the coefficient values of the correction factor until the number of updates exceeds the threshold number.

9. The method according to claim 8, wherein Updating the coefficient values of the correction factor includes: Based on the second set of parameter sets, determine a plurality of training simulation results, where the training simulation results in the plurality of training simulation results include the simulation values of the electrochemical deposition topography of the chip; Based on the difference between the plurality of training simulation results and the corresponding reference simulation results, determine the corresponding quality of the parameter values in the second set of parameter sets, where the reference simulation results include the reference values of the electrochemical deposition topography of the chip; Based on the quality, use the Monte Carlo search tree algorithm to update the coefficient values in the second set of parameter sets to determine a third set of parameter sets; and Update the coefficient values of the correction factor based on the coefficient values in the third set of parameter sets.

10. An electronic device, characterized in that, Includes: At least one processing unit; And At least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit, and the instructions, when executed by the at least one processing unit, cause the electronic device to execute the method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, A computer program is stored thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 9.

Images