Low parasitic inductance multilayer vertical capacitor with multi-via-hole parallel structure

Abstract

The invention provides a low parasitic inductance multilayer vertical capacitor with a multi-via-hole parallel structure, which comprises an electrode plate group formed by alternately and vertically stacking input side electrode plate groups and output side electrode plate groups, the input side electrode plate group and the output side electrode plate group are respectively connected in parallel through a plurality of input side metal via holes and output side metal via holes, and the input side metal via holes and the output side metal via holes are respectively provided with input ports and output ports; according to the invention, the parasitic inductance of the capacitor is reduced, the self-resonant frequency of the capacitor is improved, the performance consistency of the capacitor is improved, and the capacitor is compatible with the existing production process.

Description

Technical Field

[0001] The present invention relates to a capacitor, in particular to a low-parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure. Background Art

[0002] The information provided in this section is only background information related to the present disclosure, and it does not necessarily constitute prior art.

[0003] With the continuous improvement of the requirements for miniaturization and low power consumption in mobile communication devices, lumped capacitance elements are increasingly used in RF front-end design to replace distributed parameter elements. The size of lumped capacitance elements is independent of the wavelength, and miniaturization can be achieved through vertical stacking, which is suitable for fields such as 5G communication and millimeter-wave communication.

[0004] Traditional lumped parameter multi-layer capacitors form a parallel capacitance network by vertically stacking metal electrode plates (as shown in Figure 1 , Figure 2 ). Under the same horizontal area, the larger the capacitance value, the more layers of electrode plates will be. However, in RF circuits, the metal vias connecting the electrode plates will introduce parasitic inductance (such as vias 5 and 6 in Figure 1 ). This results in a hybrid of the ideal capacitance and parasitic inductance, and the impacts on the capacitor are specifically manifested as follows:

[0005] (1) Parasitic inductance accumulation. A single via is equivalent to a series parasitic inductance, and its value is determined by the via diameter and length. A via with a diameter of 0.2 mm and a length of 1 - 2 mm can have a parasitic inductance in the nH level at 5 GHz. As the number of electrode plate layers increases, the parasitic inductance introduced by the vias will also increase.

[0006] (2) Reduction of self-resonant frequency. The parasitic inductance and the intrinsic capacitance of the capacitor form an LC resonant circuit, resulting in a significant decrease in the self-resonant frequency (SRF), which severely limits its application in 5G communication and millimeter-wave frequency bands.

[0007] (3) Process sensitivity. The inductance value of a single via is highly sensitive to processing errors (such as aperture deviation), resulting in poor parameter consistency of the capacitor, which brings difficulties to subsequent circuit optimization and fine-tuning.

[0008] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Summary of the Invention

[0009] Object of the Invention: The technical problem to be solved by the present invention is to provide a low-parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure in view of the deficiencies of the prior art.

[0010] To solve the above technical problems, the present invention discloses a low parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure, comprising:

[0011] An electrode plate group formed by alternately and vertically stacking an input-side electrode plate group and an output-side electrode plate group. The input-side electrode plate group and the output-side electrode plate group are respectively connected in parallel through a plurality of input-side metal vias and output-side metal vias, and an input port and an output port are respectively provided on the input-side metal vias and the output-side metal vias.

[0012] Furthermore, the input-side metal vias and the output-side metal vias are used to reduce the parasitic inductance and the self-resonant frequency, specifically as follows:

[0013] Assume that the inductances of each input-side metal via and output-side metal via are the same, both being L0, then the total inductance L A is:

[0014]

[0015] Assume that the capacitance value is C, then the self-resonant frequency f SFR is:

[0016]

[0017] wherein, N is the number of metal vias, which is used to reduce the parasitic inductance and the self-resonant frequency.

[0018] Furthermore, the number of layers of the input-side electrode plate group is odd, one layer more than the number of layers of the output-side electrode plate group, and the input-side electrode plate group is located on the outside of the capacitor.

[0019] Furthermore, the input-side metal vias are arranged at equal intervals on one side of the input-side electrode plate group, and the center distance between adjacent input-side metal vias is 1 to 3 times the diameter of the input-side metal vias;

[0020] The output-side metal vias are arranged at equal intervals on the corresponding side of the output-side electrode plate group, and the center distance between adjacent output-side metal vias is 1 to 3 times the diameter of the output-side metal vias.

[0021] Furthermore, the numbers of the input-side metal vias and the output-side metal vias are both more than 3.

[0022] Furthermore, the input-side electrode plate group is composed of 3 electrode plates, and the output-side electrode plate group is composed of 2 electrode plates; the aspect ratio of the electrode plates ≤ 2.

[0023] Furthermore, the thickness of the electrode plates is 18 - 36 μm.

[0024] Furthermore, the vertical distance between the electrode plates is 0.05 - 1 mm.

[0025] Further, the aspect ratio of the electrode plate is 1.5, and the vertical distance between the electrode plates is 0.254 mm.

[0026] Further, the diameters of the input-side metal vias and the output-side metal vias are 0.1 - 1 mm.

[0027] Beneficial effects:

[0028] (1) Reduces the parasitic inductance of the capacitor and increases the self-resonant frequency of the capacitor

[0029] Measurements and comparisons were made on the capacitor samples using the solution of the present invention and the capacitor samples using the traditional design solution. The average value of the parasitic inductance of the former decreased by about 20% - 30% compared with the latter. The direct reduction of the parasitic inductance increases the self-resonant frequency of the capacitor, thereby effectively broadening the working bandwidth of the device and providing better signal processing capabilities for the RF circuit.

[0030] (2) Improves the performance consistency of the capacitor

[0031] Capacitors using a single via are extremely sensitive to processing errors. After introducing the multi-via parallel structure, the influence of the processing errors of a single via on the total parasitic inductance is dispersed, and the more the number of vias, the smaller the influence of the processing errors on the magnitude of the parasitic capacitance. Since the metal via is one of the basic structures in the PCB production process, the improvement of the capacitance performance consistency can be achieved at low cost.

[0032] (3) Compatible with existing production processes

[0033] The structural design of the present invention is similar to that of the traditional multi-layer structure capacitor, and the performance is improved by optimizing the device layout. Therefore, the processes such as its design, production, and testing are completely compatible with the existing CMOS, LTCC, and PCB manufacturing processes, without the need to add special process steps. Description of the drawings

[0034] The following further detailed description of the present invention will be made in conjunction with the drawings and specific embodiments, and the above and / or other advantages of the present invention will become clearer.

[0035] Figure 1 It is a three-dimensional view of a traditional lumped-parameter multi-layer vertical structure capacitor.

[0036] Figure 2 It is a cross-sectional schematic view of a traditional lumped-parameter multi-layer vertical structure capacitor.

[0037] Figure 3 It is a three-dimensional view of the multi-layer vertical structure capacitor with low parasitic inductance of the present invention.

[0038] Figure 4 Schematic diagram of the input side part of the capacitor.

[0039] Figure 5 Schematic diagram of the output side part of the capacitor.

[0040] Figure 6 Partial enlarged schematic diagram of the output port and the metal via group.

[0041] In the figure, 11 is the first electrode plate on the input side, 13 is the second electrode plate on the input side, 15 is the third electrode plate on the input side; 12 is the first electrode plate on the output side, 14 is the second electrode plate on the output side; 16 is the via group on the input side, 17 is the via group 17 on the output side, 18 is the input port, and 19 is the output port Specific implementation mode

[0042] The overall idea of the present invention is as follows: Provide a multi-layer vertical structure capacitor based on a multi-via parallel structure. By optimizing the connection method and layout parameters of the electrode plates, the parasitic inductance in the multi-layer vertical structure capacitor is reduced, the sensitivity to processing errors is reduced, and the self-resonant frequency of the capacitor is increased to meet the requirements of the RF circuit for capacitor performance.

[0043] The novel multi-layer vertical capacitor structure reduces the magnitude of parasitic inductance and the sensitivity to processing errors through a multi-via parallel layout, and is also compatible with standard PCB / LTCC processes to meet the requirements of the RF circuit for low parasitic parameters and high stability.

[0044] Hierarchical design of electrode plates. The electrode plates on the input side (odd layers) and the electrode plates on the output side (even layers) are alternately arranged to form a parallel capacitor network. The number of layers of the electrode plates can be varied to meet the requirements of different capacitance values.

[0045] Multi-via parallel layout. Each group of electrode plates is connected in parallel through more than 3 metal vias (such as Figure 3 the via groups 16 and 17 in the figure), reducing the total parasitic inductance and at the same time reducing the influence of processing errors on the parasitic inductance.

[0046] Production process compatibility. The structure of the capacitor, the diameter of the vias, and the via pitch meet the requirements of the standard PCB production process, and no special processing steps are required.

[0047] 1. Overall structure description

[0048] Referring to Figures 3 to 6 , the present invention provides a low-parasitic inductance multi-layer vertical capacitor based on a multi-via parallel structure, including the following core components:

[0049] (1) Multi-layer electrode plate group

[0050] The input-side electrode plates 11, 13, and 15 (white markings) and the output-side electrode plates 12 and 14 (dot markings) are alternately stacked vertically, and adjacent electrode plates are isolated by a dielectric layer to form a parallel capacitor network. The number of electrode plates is preferably 5 layers, and can also be increased according to the circuit structure. Among them, the odd-numbered layers are the input side, and the even-numbered layers are the output side. The aspect ratio of the electrode plates ≤ 2 (preferably 1.5), and the thickness is 18 - 36 μm, which can be adapted to the standard copper foil process. The vertical distance between the electrode plates is 0.05 - 1 mm, preferably 0.254 mm.

[0051] (2) Multi-via parallel connection structure

[0052] The input-side via group 16 consists of 3 identical metal vias (diameter 0.1 - 1 mm) arranged at equal intervals along the x-axis, connecting the input port 18 to the input-side electrode plates 11, 13, and 15. The structure of the output-side via group 17 is symmetric to that of the input side, connecting the output port 19 to the output-side electrode plates 12 and 14. The center distance between adjacent vias is 1 - 3 times the via diameter. When the size of the electrode plate changes, the number of metal vias in the via group can continue to increase based on 3. However, in any case, the number of metal vias in the via group should not be less than 3. At the same time, the number of metal vias in the input-side via group and the output-side via group can be different, but the same number is convenient for design and simulation.

[0053] (3) Input and output ports

[0054] The input port 18 and the output port 19 are composed of rectangular metal sheets. The ports can be on the same layer as the middle electrode plate of the capacitor, or can be placed on the top layer, bottom layer or other layers of the capacitor according to needs. One end of the input port is connected to the input-side via group, and the other end is connected to the external circuit. One end of the output port is connected to the output-side via group, and the other end is connected to the external circuit. When the port is connected to the external circuit, the length of the connection part can be adjusted according to the circuit layout.

[0055] 2. Key improvement points

[0056] (1) Reducing parasitic inductance and self-resonant frequency through multi-via parallel connection

[0057] Traditional multi-layer vertical structure capacitors use a single metal via to connect each electrode plate, resulting in a relatively high parasitic inductance, which limits their high-frequency performance. The present invention introduces multiple parallel metal vias to connect each electrode plate. Each via is in a parallel relationship, and its total inductance is:

[0058]

[0059] Assuming that the inductance of each metal via is the same, all being L0, then the total inductance of N metal vias is:

[0060]

[0061] That is, as the number of vias increases, the total parasitic inductance brought by the vias decreases significantly.

[0062] In terms of the self-resonant frequency, if the capacitance value is C, then:

[0063]

[0064] That is, as the number of vias increases, the self-resonant frequency of the capacitor increases significantly.

[0065] (2) Improving performance consistency through parallel connection of multiple vias

[0066] The capacitor using a single via design is extremely sensitive to processing errors. For example, a slight deviation in the via diameter or length will cause a large fluctuation in the parasitic inductance, affecting the performance consistency of the capacitor. In the present invention, through the parallel structure of multiple vias, the influence of the processing error of a single via on the total parasitic inductance is effectively dispersed, and the more the number of vias, the more stable the value of the total parasitic inductance, thereby effectively improving the performance consistency of the capacitor.

[0067] Embodiment:

[0068] In a preferred embodiment of the present invention, a multi-layer vertical structure capacitor with low parasitic inductance is formed. The capacitor is composed of 5 electrode plates. In each drawing and embodiment of the embodiment of the present invention, the same symbols represent the same elements.

[0069] Figure 3 FIG. is a perspective view of the multi-layer vertical structure capacitor with low parasitic inductance of the present invention. The capacitor includes electrode plates 11, 12, 13, 14, 15, includes metal via groups 16, 17, and includes input / output ports 18, 19. For clearer display, electrode plates 11, 13, 15, metal via group 16, and input port 18 are shown in white, and electrode plates 12, 14, metal via group 17, and output port 19 are shown in a dotted pattern. Among them, 11, 13, 15, 16, 18 together constitute the input side of the capacitor, and 12, 14, 17, 19 together constitute the output side of the capacitor. There is an insulating dielectric layer with a certain thickness between adjacent electrode plates.

[0070] The thickness of the insulating dielectric layer is limited by the processing technology and application scenarios, and the preferred thickness is 0.05 mm to 1 mm. The thickness of the insulating dielectric layer affects the capacitance value and parasitic inductance of the capacitor. When other dimensions remain unchanged, the smaller the thickness of the insulating dielectric layer, the larger the capacitance value and the smaller the parasitic inductance of the capacitor. The thicknesses of each insulating dielectric layer are preferably kept consistent, thereby simplifying the design process of the capacitor. The dielectric constant of the insulating dielectric layer can take common values, and is preferably 2.2.

[0071] The electrode plates 11 and 12 form a sub-capacitor 1112 , the electrode plates 12 and 13 form a sub-capacitor 1213 , the electrode plates 13 and 14 form a sub-capacitor 1314 , the electrode plates 14 and 15 form a sub-capacitor 1415 . The sub-capacitors 1112 , the sub-capacitor 1213 , the sub-capacitor 1314 , the sub-capacitor 1415 are in a parallel relationship. The capacitance value C of each sub-capacitor can be calculated by the formula C = εS / d. Where ε is the dielectric constant of the insulating dielectric layer. S is the area of the overlapping part after the adjacent electrode plates are projected onto the x-y plane. d is the distance between the adjacent electrode plates along the z-axis. The total capacitance value of the capacitor is the sum of the capacitance values of each sub-capacitor. The thickness of the electrode plates is preferably 18um or 36um.

[0072] Figure 4 is the input side part of the capacitor. The electrode plates 11, 13, and 15 are parallel to the x-y plane and are equally spaced along the z-axis. The electrode plates 11, 13, and 15 have the same size and can be designed as a square, a rectangle, or other shapes according to needs. If designed as a rectangle, the ratio of the length of the long side to the short side should be less than 2, preferably 1.5. In Figure 4 , the electrode plates 11, 13, and 15 are rectangles. Their sides along the y-axis are the long sides, and their sides along the x-axis are the short sides. The electrode plates 11, 13, and 15 are connected by the metal via group 16 to ensure equal electric potential. The metal via group 16 contains three identical metal vias. In Figure 4 , these three identical metal vias are arranged at a certain interval along the x-axis. The parasitic inductances introduced by the three identical metal vias are in a parallel relationship, so the total parasitic inductance is one-third of the parasitic inductance of a single via. The larger the diameter of the metal via, the smaller the parasitic inductance. When selecting the diameter of the metal via, it should be greater than the limit of the selected processing technology. However, in all cases, it should be ensured that the diameter of the metal via is less than one-fourth of the side length of the electrode plate where the via is located. Preferably, it is about 0.1mm - 1mm. The distance between adjacent metal vias should be between 1 - 3 times the diameter of the metal via.

[0073] The input port 18 is used to connect the input end of the capacitor to the circuit. The size of the input port is limited by the circuit layout and there is no fixed requirement.

[0074] Figure 5This is the output side portion of the capacitor. The electrode plates 12 and 14 have the same dimensions. However, the dimensions of the electrode plates 12 and 14 can be made consistent with those of the electrode plates 11, 13, and 15, thus simplifying the design. The metal via group 17 also includes three identical metal vias. They are in parallel connection and connect the electrode plates 12 and 14 simultaneously, thereby serving to reduce the parasitic inductance. The output port 19 is used to connect the capacitor to an external circuit.

[0075] Figure 6 This is a partial enlarged view of the output port 19 and the metal via group 17. Among them, the output port 19 is shown using a dot pattern. In order to achieve the connection between the external circuit and the metal via group 17, the output port 19 is composed of two parts, 191 and 192, which are separated by the line segment m1 - m2. The width of 191 is the same as 18, but the length has no specific requirement and needs to be determined according to the external circuit. The function of 192 is to parallel the three metal vias of the metal via group 17 and connect them to 191. For simplicity of design, the dimension of 192 in the x - direction can be made the same as the dimensions of 12 and 17 in the x - direction, and at the same time, the dimension of 192 in the y - direction can be made 1.5 - 2 times the diameter of the metallized via in 17.

[0076] In a preferred embodiment of the present invention, the positions of the metal via groups 16 and 17 have a certain degree of flexibility. As Figure 4 shown, when the space of the capacitor is limited, the positions of the metal via groups 16 and 17 can be moved along the x - direction. However, during the movement, it is necessary to ensure the close contact between the metal via group and the electrode plate.

[0077] Although the top view of the previously discussed embodiment has five electrode plates, those skilled in the art can understand that the present invention can be applied to the case of having six or more electrode plates. By changing the outer contour of the electrode plate, capacitors of other shapes such as circular and elliptical can also be formed.

[0078] With the above - mentioned technical solutions, the present invention has conducted actual experiments.

[0079] 1. The First Experiment

[0080] In this experiment, using known techniques, a batch of capacitor samples were fabricated through the PCB process according to the Figure 4 shown structure. The target capacitance value of the samples was 6 pF. During fabrication, the thickness of a single insulating dielectric layer was 0.254 mm, the relative dielectric constant was 2.2, and the copper foil thickness was 18 μm. For comparison, a batch of capacitors with the same target capacitance value based on the traditional lumped - parameter multi - layer vertical structure were fabricated using the same process. As shown in Table 1 and Table 2, the self - resonance frequency values of the capacitors measured using a vector network analyzer, and the parasitic inductance values calculated based on the self - resonance frequency and the target capacitance value are presented.

[0081] Table 1 Test Results of Multilayer Vertical Structure Capacitor Samples with Low Parasitic Inductance (First Batch)

[0082]

[0083]

[0084] Table 2 Test Results of Traditional Lumped Parameter Multilayer Vertical Structure Capacitor Samples (First Batch)

[0085] Sample number Self-resonant frequency (GHz) Parasitic inductance value (nH) 1 3.215 0.408 2 3.078 0.446 3 3.240 0.402 4 3.214 0.409 5 3.123 0.433 Average value 3.174 0.419

[0086] As shown in Table 1 and Table 2, when the target capacitance values are the same, the average parasitic inductance of the multilayer vertical structure capacitor with low parasitic inductance of the present invention is 0.300 nH, while the average parasitic inductance of the traditional lumped parameter multilayer vertical structure capacitor is 0.419 nH.

[0087] 2. Second Experiment

[0088] In this experiment, using known techniques, a batch of capacitor samples was fabricated through PCB technology according to the Figure 4 shown structure. The target capacitance value of the samples was 50 pF. During fabrication, the thickness of a single insulating dielectric layer was 0.508 mm, the relative dielectric constant was 2.2, and the copper foil thickness was 18 μm. For comparison, a batch of capacitors with the same target capacitance value and based on the traditional lumped parameter multilayer vertical structure was fabricated using the same process. The following table shows the self-resonant frequency values of the capacitors measured using a vector network analyzer, and the parasitic inductance values calculated based on the self-resonant frequency and the target capacitance value.

[0089] Table 3 Test Results of Multilayer Vertical Structure Capacitor Samples with Low Parasitic Inductance (Second Batch)

[0090] Sample number Self-resonant frequency (GHz) Parasitic inductance value (nH) 1 1.564 0.207 2 1.556 0.209 3 1.612 0.195 4 1.538 0.214 5 1.595 0.199 Average value 1.573 0.205

[0091] Table 4 Test Results of Traditional Lumped Parameter Multilayer Vertical Structure Capacitor Samples (Second Batch)

[0092] Sample number Self-resonant frequency (GHz) Parasitic inductance value (nH) 1 1.308 0.296 2 1.403 0.258 3 1.358 0.275 4 1.322 0.290 5 1.383 0.265 Average value 1.355 0.277

[0093] As shown in Table 3 and Table 4, when the target capacitance values are the same, the average parasitic inductance of the multilayer vertical structure capacitor with low parasitic inductance of the present invention is 0.205 nH, while the average parasitic inductance of the traditional lumped parameter multilayer vertical structure capacitor is 0.277 nH.

[0094] In summary, the present invention introduces a multi-via parallel structure design, effectively reducing the parasitic inductance value and increasing the self-resonant frequency. Traditional multi-layer vertical capacitors usually use a single metal via to connect the electrode plates. Due to the relatively high parasitic inductance of a single via, the performance of the capacitor under high-frequency conditions is limited. The present invention innovatively uses multiple metal vias (such as 3) in parallel to connect the electrode plates, effectively reducing the parasitic inductance. In a preferred embodiment, the parasitic inductance is reduced to approximately 0.3 nH by the 3 parallel vias, which is approximately 25% lower than the traditional design. The significant reduction in parasitic inductance increases the self-resonant frequency of the capacitor, thereby broadening the operating bandwidth and enabling it to meet the requirements of high-frequency applications such as 5G communication.

[0095] The present invention introduces a multi-via parallel structure design, effectively reducing the influence of processing errors on the performance consistency of the capacitor. The traditional single-via design is extremely sensitive to processing errors. The present invention innovatively uses multiple metal vias (such as 3) in parallel to connect the electrode plates, converting the parasitic inductance of a single via into a parallel structure of the parasitic inductances of multiple vias, and dispersing the fluctuations in the magnitude of a single parasitic inductance, thereby improving the performance consistency of the capacitor.

[0096] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit. Among them, the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, it can run the content of the present invention of a low-parasitic-inductance multi-layer vertical capacitor with a multi-via parallel structure and some or all of the steps in each embodiment. The storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), etc.

[0097] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of a computer program and its corresponding general hardware platform. Based on such an understanding, the technical solutions in the embodiments of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer program, that is, a software product. This computer program software product can be stored in a storage medium and includes several instructions to enable a device (which can be a personal computer, a server, a single-chip microcomputer, an MCU, or a network device, etc.) including a data processing unit to execute the methods described in each embodiment or some parts of the embodiments of the present invention.

[0098] The present invention provides an idea and method for a low parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure. There are many methods and ways to specifically implement this technical solution. The above description is only a preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented by existing technologies.

Claims

1. A low parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure, characterized in that, Comprising: An electrode plate group formed by alternately and vertically stacking an input-side electrode plate group and an output-side electrode plate group. The input-side electrode plate group and the output-side electrode plate group are respectively connected in parallel through a plurality of input-side metal vias and output-side metal vias, and input ports and output ports are respectively provided on the input-side metal vias and the output-side metal vias.

2. The multi-via parallel structure low parasitic inductance multi-layer vertical capacitor according to claim 1, wherein The input-side metal vias and the output-side metal vias are used to reduce parasitic inductance and self-resonant frequency, specifically as follows: Assume that the inductances of each input-side metal via and output-side metal via are the same, both being L0, then the total inductance L A is: If the capacitance value is C, then the self-resonant frequency f SFR is: Wherein, N is the number of metal vias, which is used to reduce parasitic inductance and self-resonant frequency.

3. The low-parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure according to claim 1, characterized in that, The number of layers of the input-side electrode plate group is odd, one layer more than the number of layers of the output-side electrode plate group, and the input-side electrode plate group is located outside the capacitor.

4. The low-parasitic-inductance multi-layer vertical capacitor with a multi-via parallel structure according to claim 1, characterized in that The input-side metal vias are arranged at equal intervals on one side of the input-side electrode plate group, and the center distance between adjacent input-side metal vias is 1 to 3 times the diameter of the input-side metal vias; The output-side metal vias are arranged at equal intervals on the corresponding side of the output-side electrode plate group, and the center distance between adjacent output-side metal vias is 1 to 3 times the diameter of the output-side metal vias.

5. A low parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure according to claim 1, characterized in that, The number of the input-side metal vias and the output-side metal vias is more than 3 respectively.

6. The low-parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure according to claim 1, characterized in that, The input-side electrode plate group is composed of 3 electrode plates, and the output-side electrode plate group is composed of 2 electrode plates; the aspect ratio of the electrode plates ≤ 2.

7. The low parasitic inductance multi-layer vertical capacitor with a multi-via parallel structure according to claim 6, wherein The thickness of the electrode plates is 18 - 36 μm.

8. The multi-via parallel structure low parasitic inductance multi-layer vertical capacitor according to claim 6, characterized in that, The vertical distance between the electrode plates is 0.05 - 1 mm.

9. The multi-via parallel structure low parasitic inductance multi-layer vertical capacitor according to claim 7, wherein, The aspect ratio of the electrode plates is 1.5, and the vertical distance between the electrode plates is 0.254 mm.

10. The multi-via parallel structure low parasitic inductance multi-layer vertical capacitor according to claim 1, wherein The diameters of the input-side metal vias and the output-side metal vias are 0.1 - 1 mm.

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