Power device and preparation method thereof, and electronic equipment

Abstract

The present application relates to a power device, a method for manufacturing the same, and an electronic device, comprising: providing a substrate and an epitaxial layer; forming a source region, a base region, and a first shielding region in the epitaxial layer, arranged in sequence along a first direction toward the substrate through a first surface of the epitaxial layer; the first shielding region having a first preset thickness and a first doping concentration, wherein the thickness is used to characterize the dimension along the first direction; forming second shielding regions spaced apart along a second direction parallel to the first surface, the second shielding regions having a second doping concentration and extending through the first shielding region along the first direction and into the epitaxial layer; forming a gate between adjacent second shielding regions, extending through the first surface toward the epitaxial layer into the first shielding region; a preset distance between the bottom surface of the gate and the bottom surface of the first shielding region. By precisely controlling the gate depth and the doping concentration of the first shielding region, the formation of a conductive channel in the first shielding region in the on state is avoided, thereby affecting the device's conduction characteristics.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a power device and a preparation method thereof, and an electronic device. Background Art

[0002] Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a widely used power device with excellent performance, which has the advantages of fast switching speed, low loss and simple driving circuit.

[0003] Existing trench-gate silicon carbide (SiC) MOSFET device structures are highly sought after for their advantages, including high trench gate crystal mobility, small cell size, and high channel density. However, they also face the problem of electric field concentration at the trench corners, which can impact gate oxide reliability. To prevent breakdown due to electric field concentration at the bottom of the trench gate, a sufficiently thick epitaxial layer is required to mitigate the electric field strength. To effectively mitigate the risk of dielectric breakdown caused by excessive electric field concentration at the bottom of the trench gate, the industry typically implants P-type pillars at the bottom of the trench and its surrounding areas to create a shielding area that mitigates the electric field strength experienced by the trench dielectric layer.

[0004] However, the introduction of the shielding region will inevitably lead to an increase in the on-resistance of the device, which will have a negative impact on the conductive performance of the device. Summary of the Invention

[0005] Based on this, it is necessary to provide a power device and its preparation method, and an electronic device to address the technical problems in the existing technology, which can at least improve the gate oxide reliability of the device while reducing its specific on-resistance while ensuring the cell size.

[0006] In a first aspect, the present application provides a method for manufacturing a power device, comprising: providing a substrate; the top surface of the substrate comprises an epitaxial layer;

[0007] A source region, a base region, and a first shield region are formed in the epitaxial layer, arranged in sequence along a first direction toward the substrate through the first surface of the epitaxial layer; the first shield region has a first predetermined thickness and a first doping concentration; wherein the thickness is used to represent the dimension along the first direction;

[0008] Second shielding regions are formed and arranged in a second direction parallel to the first surface. The second shielding regions have a second doping concentration and penetrate the first shielding region along the first direction and extend into the epitaxial layer. The second doping concentration is related to the thickness of the second shielding region and the first predetermined thickness. The second shielding regions include:

[0009] a first portion, wherein a bottom surface of the first portion is flush with a top surface of the first shielding area;

[0010] a second portion, wherein a top surface of the second portion is flush with a top surface of the first shielding area;

[0011] The second doping concentration of the first portion first increases and then decreases in a direction away from the first direction;

[0012] The second doping concentration of the second portion first increases and then decreases along the first direction;

[0013] A gate is formed between adjacent second shielding regions, extending from the first surface toward the epitaxial layer to the first shielding region; a preset distance value is provided between the bottom surface of the gate and the bottom surface of the first shielding region; and the second doping concentration peak of the second portion is located 0.3μm-0.5μm away from the bottom surface of the gate.

[0014] In the fabrication method of the above embodiment, a first shielding region is formed at the bottom of the gate to reduce the electric field strength of the gate oxide layer at the bottom of the trench gate. A second shielding region is also provided to form a superjunction structure with the epitaxial layer in the second direction, thereby assisting in epitaxial layer depletion and improving the device's voltage withstand capability. Compared to the traditional method of forming a shielding region solely through ion implantation at the bottom of the trench, the first shielding region is formed simultaneously with the source and base regions and extends through the epitaxial layer in the second direction to connect to the second shielding region. This facilitates short-circuiting between the first shielding region and the source region while avoiding damage to the trench structure and without reducing the number of conductive paths.

[0015] In addition, in order to reduce the impact of the first shielding region that fully surrounds the trench gate on the device's conduction characteristics, the doping concentration (first doping concentration), thickness (first preset thickness) of the first shielding region, and the depth of the gate embedded in the first shielding region are controlled. This can prevent the first shielding region from forming a conductive channel when the device is in the on state, and reduce its on-resistance, thereby achieving a balanced optimization of the device's conduction characteristics and gate oxide reliability.

[0016] In some embodiments, a method for preparing a power device includes at least one of the following features:

[0017] The first preset thickness ranges from 50nm to 150nm;

[0018] The second preset thickness ranges from 0.8 μm to 1 μm;

[0019] The first doping concentration range is: 2e16cm -3 -5e17cm -3 ;

[0020] The preset distance value range is: 20nm-80nm.

[0021] In some embodiments, forming a gate includes:

[0022] forming a trench between adjacent second shield regions, extending from the first surface toward the epitaxial layer to the first shield region;

[0023] forming a first oxide layer covering the inner surface of the trench by a thermal oxidation process;

[0024] forming a second oxide layer covering a top surface of the first oxide layer;

[0025] A gate conductive layer is formed to at least fill the trench.

[0026] In some embodiments, before forming the gate, the method further includes:

[0027] An ion implantation process is used to form a current expansion region in the epitaxial layer between adjacent second shielding regions. The top surface of the current expansion region contacts the bottom surface of the first shielding region, and the bottom surface is lower than the bottom surface of the second shielding region.

[0028] In some embodiments, the groove has a rounded arc surface.

[0029] In some embodiments, a method for preparing a power device includes at least one of the following features:

[0030] The spacing between adjacent second shielding areas ranges from 0.6 μm to 1.1 μm;

[0031] The width of the groove ranges from 0.5 μm to 0.7 μm; the width is used to represent the size along the second direction;

[0032] The crystal planes of the trench sidewalls are (1-100) and (-1100);

[0033] The conductivity type of the epitaxial layer is the same as that of the base region and the current extension region, and is different from that of the source region, the first shielding region and the second shielding region.

[0034] In some embodiments, the ratio of the radius of the rounded arc surface at the bottom of the groove to the width of the groove is in the range of 0.3-0.4;

[0035] The ratio of the radius of the rounded arc surface at the top of the groove to the width of the groove is in the range of 0.6-0.7.

[0036] In some embodiments, a dimension of the trench along the first direction ranges from 0.8 μm to 1 μm.

[0037] In a second aspect, the present application further provides a power device, which is prepared using the preparation method in any of the above embodiments.

[0038] In a third aspect, the present application further provides an electronic device comprising the power device in any one of the above embodiments.

[0039] Since the power devices and electronic devices of the above embodiments and the method for preparing the power devices provided by the present invention are based on the same inventive concept, the power devices and electronic devices using this preparation method have all the advantages of the preparation method provided by the present invention, and are not described in detail here.

[0040] The power device and its preparation method, and the electronic device provided by this application have the following unexpected technical effects:

[0041] Compared with traditional preparation methods, the preparation method provided in the embodiment of the present application is compatible with existing processes, and by preparing the first shielding area, source area, and base area at the same time, the independent shielding area injection process is eliminated, the number of photolithography mask layers and the number of ion injections are reduced, the process cycle is shortened, and the process cost is reduced; the introduced dual shielding area structure works synergistically to optimize the electric field distribution at the bottom of the trench and near the gate oxide layer in both vertical and horizontal directions, and transfers the peak electric field from the gate oxide interface to the edge of the shielding area, avoiding premature breakdown due to electric field concentration, and ensuring the reliability of the device gate oxide.

[0042] In addition, by precisely designing the geometric parameters of the gate, first shielding area, and second shielding area (such as thickness, spacing, and doping concentration gradient), the influence of the first shielding area of the fully surrounded trench gate on the device's conduction characteristics is minimized, thereby preventing the first shielding area from forming a conductive channel when the device is in the on state and reducing its on-resistance, thereby achieving a balanced optimization of the device's conduction characteristics and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 Schematic diagram of the structure of a trench-gate SIC MOSFET device in the prior art;

[0045] Figure 2 is a flow chart of a preparation method provided in one embodiment;

[0046] Figure 3 Schematic cross-sectional view of the substrate structure in step S20 of the preparation method provided in one embodiment;

[0047] Figure 4 4 is a schematic cross-sectional view of a structure obtained after forming a source region, a base region, and a first shielding region in step S40 of a preparation method provided in one embodiment;

[0048] Figure 51 is a schematic cross-sectional view of a structure obtained after forming the second shielding region in step S60 of the preparation method provided in one embodiment;

[0049] Figure 6 for Figure 5 A schematic cross-sectional view of the structure obtained after the current expansion region is formed;

[0050] Figure 7 FIG1 is a schematic cross-sectional view of a structure obtained after forming a groove in step S802 of a preparation method provided in an embodiment;

[0051] Figure 8 for Figure 7 Schematic diagram of the position of the rounded arc surface;

[0052] Figure 9 1 is a schematic cross-sectional view of a structure obtained after forming a gate oxide layer in step S806 of a preparation method provided in an embodiment;

[0053] Figure 10 1 is a schematic cross-sectional view of a structure obtained after forming a gate conductive layer in step S808 of a preparation method provided in an embodiment;

[0054] Figure 11 for Figure 10 Schematic diagram of the cross-section of the resulting structure after the back metal layer is finally formed.

[0055] Description of reference numerals:

[0056] 1. Initial substrate; 10. Substrate; 11. Buffer layer; 20. Epitaxial layer; 21. First shielding region; 22. Base region; 23. Source region; 24. Second shielding region; 25. Current extension region; 301. Trench; 30. Gate; 31. Gate oxide layer; 311. First oxide layer; 312. Second oxide layer; 32. Gate conductive layer; 12. Dielectric layer; 13. Contact layer; 14. Front metal layer; 15. Passivation layer; 16. Back metal layer. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0060] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0061] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0063] Currently, the industry mainly protects the gate oxide layer by introducing various shielding layer structures during device design, which include two types: symmetrical shielding structure and asymmetrical shielding structure. The typical implementation method of the symmetrical shielding structure is: after the gate trench is formed, the ion implantation process is performed on the bottom of the trench to add a shielding area at the bottom of the gate oxide layer. Figure 1 As shown in Figure (1), the shielding area is concentrated at the bottom of the trench gate, which is not conducive to short-circuiting with the source. The floating shielding area is difficult to fully play its role in protecting the trench gate dielectric. At the same time, parasitic transistor conduction is prone to occur under extreme working conditions, resulting in device failure. Figure 1 In the asymmetric shielding structure shown in Figure (2), the shielding areas on both sides of the gate are asymmetric, and the gate trench is embedded in the shielding area at the bottom. Although this solves the short-circuit problem of the symmetrical shielding structure, only one side of the channel is conductive.

[0064] Therefore, how to ensure the conduction characteristics of the device without sacrificing the number of conduction channels has become one of the technical problems that workers in this field need to solve urgently.

[0065] In an embodiment of the present application, the epitaxial layer may include a first surface located on the front side and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, the direction toward the substrate is defined as comprising a first direction perpendicular to the first surface of the substrate and a second direction parallel to the first surface. The first direction and the second direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0066] See also Figure 2-Figure 10 , the present application provides a method for preparing a power device, including: steps S20 to S80.

[0067] Step S20 : providing a substrate 10 , wherein the top surface of the substrate 10 includes an epitaxial layer 20 .

[0068] Step S40: A source region 23, a base region 22, and a first shield region 21 are formed in the epitaxial layer 20 through the first surface 20a of the epitaxial layer 20 and arranged in sequence along a first direction (OY direction) toward the substrate; the first shield region 21 has a first preset thickness and a first doping concentration; wherein the thickness is used to characterize the size along the first direction (OY direction).

[0069] Step S60: Forming second shielding regions 24 spaced apart along a second direction (OX direction) parallel to the first surface 20a. The second shielding regions 24 have a second doping concentration and extend along the first direction through the first shielding region 21 and into the epitaxial layer 20. The second doping concentration is related to the thickness of the second shielding region 24 and the first predetermined thickness. The second shielding regions 24 include: a first portion, the bottom surface of the first portion being flush with the top surface of the first shielding region 21; and a second portion, the top surface of the second portion being flush with the top surface of the first shielding region 21. The second doping concentration of the first portion first increases and then decreases in a direction away from the first direction; the second doping concentration of the second portion first increases and then decreases along the first direction.

[0070] Step S80: A gate 30 is formed between adjacent second shielding regions 24, extending through the first surface 20a toward the epitaxial layer 20 to the first shielding region 21; a preset distance value is provided between the bottom surface of the gate 30 and the bottom surface of the first shielding region 21; the second doping concentration peak of the second portion is located at 0.3μm-0.5μm away from the bottom surface of the gate 30.

[0071] The power device obtained after step S20 to step S80 can be referred to Figure 10 To facilitate understanding of this application, Figure 10 This is an example of a power device prepared using the preparation method provided in this application. There may be other suitable examples of power devices prepared using the preparation method provided in this application, and this application does not limit them here.

[0072] The above steps are described in detail with reference to the accompanying drawings.

[0073] See also Figure 3 In step S20 , the extension step further includes: providing an initial substrate 1 , and sequentially forming a buffer layer 11 and an epitaxial layer 20 on the top surface of the initial substrate 1 along the YO direction (the opposite direction of the OY direction).

[0074] For example, the initial substrate 1 and the buffer layer 11 are used to form the substrate 10. The thickness of the substrate 10 ranges from 0.5 μm to 3 μm, for example, 0.5 μm, 1 μm, 2 μm, or 3 μm. The thickness and specific doping concentration of the epitaxial layer 20 are selected based on the product design voltage and are used to serve as the drift region of the power device. It should be understood that the above data mentioned in this application are for illustrative purposes only and will be adjusted according to actual cases in actual implementations. The above data are not limiting.

[0075] For example, in the embodiments mentioned in this application, the materials of the substrate 10 and the epitaxial layer 20 are both silicon carbide (SiC).

[0076] See also Figure 4 Step S40 specifically includes performing an ion implantation process three times from top to bottom (via the first surface 20a) within the epitaxial layer 20 to form a first shield region 21, a base region 22, and a source region 23. In an embodiment where the substrate 10 comprises an N-type substrate, P-type ions can be implanted to form the first shield region 21 and the base region 22, while N-type ions can be implanted to form the source region 23. Accordingly, the above method can be followed by simply swapping "P" and "N" in each step.

[0077] For example, the thickness (first preset thickness) and concentration (first doping concentration) of the first shielding region 21 are limited. In some embodiments, the first preset thickness is in the range of 50 nm to 150 nm, such as 50 nm, 100 nm, or 150 nm. The first doping concentration is in the range of 2e16 cm -3 -5e17cm -3 , for example 2e16cm -3 、5e16cm -3 、1e17cm -3 or 5e17cm -3 wait.

[0078] In the above embodiment, the first shielding region 21, the epitaxial layer 20, and the base region 22 form a junction field effect transistor (JFET). The thickness of the first shielding region 21 is closely related to its shielding effect and the resistance of the JFET region. Therefore, the thickness of the first shielding region 21 needs to be reasonably set to balance the breakdown voltage and the specific on-resistance.

[0079] See also Figure 5 Step S60 specifically includes: using high energy to implant P-type ions at different doses to form second shielding regions 24 spaced apart along the OX direction. Considering the lateral diffusion of the second shielding regions 24 and the formation of a JFET region between the epitaxial layer 20 and the impact on the conduction characteristics, in some embodiments, the distance between adjacent second shielding regions 24 is limited to between 0.6μm and 1.1μm, such as 0.6μm, 0.8μm, 1.0μm, or 1.1μm.

[0080] In the above embodiment, the second shielding region 24 and the epitaxial layer 20 form a semi-superjunction structure. When withstand voltage, the P-type second shielding region and the N-type epitaxial layer 20 are mutually depleted to withstand high voltage, and act simultaneously with the first shielding region 21 to reduce the electric field strength at the bottom and corners of the gate groove, thereby protecting the gate oxide layer 31.

[0081] In addition, the adjacent second shielding region 24 and the epitaxial layer 20 constitute another JFET region. By reasonably increasing the spacing between the second shielding regions 24, the resistance value of the JFET region can be effectively reduced, thereby reducing the overall on-resistance of the device. At the same time, the setting of the first shielding region 21 can compensate for the weakening of the protective effect of the gate oxide layer caused by the increase in the spacing between the second shielding regions 24, thereby maintaining reliable protection of the gate oxide layer 31 while optimizing the conduction characteristics.

[0082] For further information, please refer to Figure 5 In some embodiments, the second shielding region 24 includes:

[0083] a first portion (not shown), the bottom surface of the first portion being flush with the top surface of the first shielding area 21;

[0084] a second portion (not shown), the top surface of the second portion being flush with the top surface of the first shielding region 21;

[0085] The second doping concentration of the first portion first increases and then decreases in a direction away from the first direction (YO direction);

[0086] The second doping concentration of the second portion first increases and then decreases along the first direction (OY direction).

[0087] In some embodiments, the second doping concentration peak of the second portion is located at a distance of 0.3 μm-0.5 μm from the bottom surface of the gate 30 , for example, 0.3 μm, 0.4 μm, or 0.5 μm.

[0088] The second doping concentration range is 2e16cm -3 -1e18cm -3 , for example 2e16cm -3 、1e17cm -3 or 1e18cm -3 wait.

[0089] In the above embodiment, the second shielding region 24 is divided into a first part and a second part with the first shielding region 21 as the boundary. The first part has a high doping concentration close to the first surface 20a and is used for source contact; the second doping concentration peak of the second part is located at 0.3μm-0.5μm from the bottom surface of the gate, which can enhance the charge balance of the second shielding region 24, the first shielding region 21 and the gate 30, and together with the segmented design and the doping concentration gradient distribution, further optimizes the electric field distribution, conduction characteristics and voltage resistance of the device.

[0090] See also Figure 6 In some embodiments, before step S80, the process further includes: using a high-energy ion implantation process or channeling ion implantation (Channeling IMP) to form a current spreading region 25 (CSL) in the epitaxial layer 20 between adjacent second shielding regions 24; the top surface of the current spreading region 25 contacts the bottom surface of the first shielding region 21, and the bottom surface is lower than the bottom surface of the second shielding region 24.

[0091] In the above embodiment, the current extension region 25 is placed below the first shielding region 21 , and the doping concentration of the current extension region 25 is greater than the doping concentration of the epitaxial layer 20 , which promotes faster diffusion of electrons toward the drift region and reduces the resistance of the JFET region.

[0092] Please continue reading Figure 7-10 In some embodiments, step S80 further includes:

[0093] Step S802 : forming a trench 301 between adjacent second shielding regions 24 , the trench 301 extending through the first surface 20 a toward the inside of the epitaxial layer 20 to the first shielding region 21 .

[0094] Specifically, the above structure is formed by dry etching, and it is necessary to ensure that the bottom of the trench 301 does not pass through the first shielding area 21, and the crystal planes of the sidewalls of the trench 301 are (1-100) and (-1100).

[0095] See also Figure 7-Figure 8 Furthermore, in some embodiments, the groove 301 formed by etching is smoothed.

[0096] The ratio of the radius R1 of the bottom rounded arc surface of the groove 301 to the width W of the groove 301 (the dimension along the OX direction) is in the range of 0.3-0.4, for example, 0.3, 0.35 or 0.4; the ratio of the radius R2 of the top rounded arc surface to the width of the groove 301 is in the range of 0.6-0.7, for example, 0.6, 0.65 or 0.7; the specific position of the rounded arc surface is as follows: Figure 8 In the above embodiment, the rounded arc surface can alleviate the electric field concentration caused by the curvature effect of the trench, and at the same time remove the epitaxial layer 20 damaged by etching near the trench 301.

[0097] The width of the trench 301 is in the range of 0.5 μm-0.7 μm, for example, 0.5 μm, 0.6 μm or 0.7 μm, and the etching depth along the OY direction is in the range of 0.8 μm-1 μm, for example, 0.8 μm, 0.9 μm or 1 μm.

[0098] Step S804: forming a first oxide layer 311 covering the inner surface of the trench 301 by a thermal oxidation process;

[0099] Step S806 : forming a second oxide layer 312 covering the top surface of the first oxide layer 311 .

[0100] See also Figure 9 A thermal oxidation process is first used to grow a first oxide layer 311 covering the inner surface of the trench 301 , and then a chemical vapor deposition (CVD) process is used to form a second oxide layer 312 covering the first oxide layer 311 . At this point, the first oxide layer 311 and the second oxide layer 312 together constitute the gate oxide layer 31 of the gate 30 . This effectively avoids the problem of uneven oxide layers caused by differences in growth rates within the trench 301 , thereby ensuring the consistency and reliability of the device's electrical characteristics.

[0101] The thickness of the gate oxide layer 31 is specifically set according to the requirement of the driving voltage. In this embodiment, the thickness of the gate oxide layer 31 is in the range of 40 nm to 80 nm, such as 40 nm, 50 nm, 60 nm, 70 nm or 80 nm.

[0102] See also Figure 10 , step S808 : forming a gate conductive layer 32 that at least fills the trench 301 .

[0103] For example, after the trench 301 is filled with polysilicon using any deposition method, the polysilicon material outside the trench 301 is removed by etching or chemical mechanical polishing (CMP) to form the gate conductive layer 32 .

[0104] Furthermore, the preset distance between the bottom surface of the gate 30 and the bottom surface of the first shielding region 21 is in the range of 20 nm to 80 nm, such as 20 nm, 40 nm, 60 nm or 80 nm.

[0105] In the above embodiment, the preset distance value of 20nm-80nm ensures that there is enough space at the bottom of the gate, while maintaining the doping concentration of the first shielding region 21 at 2e16cm -3 to 5e17cm -3 to avoid the formation of a conductive channel between the gate and the source.

[0106] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0107] See also Figure 11 After step S80, the process further includes: depositing a dielectric layer 12 on the top surface of the gate 30, and forming a contact layer 13 of the source region 23 through a photolithography mask; combining photolithography with metal gridding to form a front metal layer 14 on the top surface of the contact layer 13; depositing a passivation layer 15 on the top surface of the front metal layer 14 to protect the power device; and finally reducing the thickness of the substrate 10 by wafer thinning, and forming a back metal layer 16 on the back surface of the substrate 10.

[0108] By way of example, the material of the dielectric layer 12 may include, but is not limited to, undoped silicate glass, borophosphate glass, and silicon nitride (SiN).

[0109] For example, the material of the contact layer 13 may include, but is not limited to, titanium silicon alloy and cobalt silicon alloy.

[0110] For example, the material of the front metal layer 14 may include, but is not limited to, aluminum (Al) and copper (Cu).

[0111] For example, the material of the passivation layer 15 includes at least silicon nitride (SiN) and polyimide. The passivation layer 15 is removed where metal contact is required. The specific pattern is related to the layout.

[0112] For example, the material of the back metal layer 16 may include, but is not limited to, nickel (Ni), titanium (Ti), and silver (Ag).

[0113] In some embodiments, the present application also provides a power device, which is prepared using the preparation method in any of the above embodiments.

[0114] In the above embodiment, compared to the conventional trench-gate power device fabrication process, which reduces the electric field at the bottom of the trench gate by implanting a single shielding region at the bottom of the gate, the first shielding region is formed simultaneously with the source and base regions, and penetrates the epitaxial layer to connect to the second shielding region, thereby avoiding damage to the trench structure during the ion implantation process and simplifying the fabrication process. The second shielding region works synergistically with the first shielding region. By precisely controlling the structural parameters (such as size, spacing, and doping concentration) of the first shielding region, gate, and second shielding region, the shorting effect with the source and the conduction characteristics are improved without sacrificing the number of conductive channels, thereby achieving simultaneous optimization of the specific on-resistance and breakdown voltage.

[0115] In some embodiments, the present application also provides an electronic device, comprising the power device in any one of the above embodiments.

[0116] In electronic devices equipped with the above-mentioned power devices, the dual shielding zone structure can reduce the chip area (such as reducing the thickness of the drift zone) through parameter optimization, meet the development needs of miniaturized and highly integrated devices, and significantly enhance long-term reliability (such as anti-electromigration capability).

[0117] The power device and its preparation method, and the electronic device provided by this application have the following unexpected technical effects:

[0118] Compared with traditional preparation methods, the preparation method provided in this application is compatible with existing processes. At the same time, the first shielding region is prepared at the same time as the source region and the base region, which can eliminate the independent shielding region injection process, reduce the number of photolithography mask layers and the number of ion injections, and shorten the process cycle; the synergistic effect of the double shielding region structure can effectively optimize the electric field distribution at the bottom of the trench and near the gate oxide layer, and transfer the peak electric field from the gate oxide interface to the edge of the shielding region, avoiding premature breakdown due to electric field concentration.

[0119] In addition, by precisely designing the geometric parameters of the gate, first shielding region, and second shielding region (such as thickness, spacing, and doping concentration gradient), it is possible to prevent the first shielding region from forming a conductive channel when the device is in the on state, and reduce its on-resistance, thereby achieving a balanced optimization of the device's conduction characteristics and reliability.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a power device, characterized in that: include: providing a substrate; The top surface of the substrate includes an epitaxial layer; forming a source region, a base region, and a first shield region in the epitaxial layer, arranged in sequence along a first direction toward the substrate through the first surface of the epitaxial layer; the first shield region having a first predetermined thickness and a first doping concentration; wherein the thickness is used to represent a dimension along the first direction; forming second shielding regions spaced apart along a second direction parallel to the first surface, the second shielding regions having a second doping concentration and penetrating the first shielding region along the first direction and extending into the epitaxial layer; the second doping concentration being associated with a thickness of the second shielding region and the first predetermined thickness; and the second shielding regions comprising: a first portion, wherein a bottom surface of the first portion is flush with a top surface of the first shielding area; a second portion, wherein a top surface of the second portion is flush with a top surface of the first shielding area; The second doping concentration of the first portion first increases and then decreases in a direction away from the first direction; The second doping concentration of the second portion first increases and then decreases along the first direction; A gate is formed between adjacent second shielding regions and extends into the epitaxial layer through the first surface to the first shielding region; a preset distance value is provided between the bottom surface of the gate and the bottom surface of the first shielding region; and the second doping concentration peak of the second portion is located at 0.3μm-0.5μm away from the bottom surface of the gate.

2. The preparation method according to claim 1, characterized in that Include at least one of the following features: The first preset thickness ranges from 50 nm to 150 nm; The range of the first doping concentration is: 2e16cm -3 -5e17cm -3 ; The preset distance value range is: 20nm-80nm.

3. The preparation method according to claim 1, characterized in that Forming the gate includes: forming a trench between adjacent second shielding regions, extending through the first surface toward the epitaxial layer and into the first shielding region; forming a first oxide layer covering the inner surface of the trench by a thermal oxidation process; forming a second oxide layer covering a top surface of the first oxide layer; A gate conductive layer is formed to at least fill the trench.

4. The preparation method according to claim 3, characterized in that Before forming the gate, the method further includes: An ion implantation process is used to form a current extension region in the epitaxial layer between adjacent second shielding regions; the top surface of the current extension region contacts the bottom surface of the first shielding region, and the bottom surface is lower than the bottom surface of the second shielding region.

5. The preparation method according to claim 4, characterized in that The groove has a rounded arc surface.

6. The preparation method according to claim 5, characterized in that Include at least one of the following features: The spacing between adjacent second shielding areas ranges from 0.6 μm to 1.1 μm; The width of the groove is in the range of 0.5 μm to 0.7 μm; the width is used to characterize the size along the second direction; The crystal planes of the trench sidewalls are (1-100) and (-1100); The epitaxial layer has the same conductivity type as the base region and the current extension region, and has a different conductivity type from the source region, the first shield region, and the second shield region.

7. The preparation method according to claim 6, characterized in that The ratio of the radius of the rounded arc surface at the bottom of the groove to the width of the groove is in the range of 0.3-0.4; The ratio of the radius of the rounded arc surface at the top of the groove to the width of the groove is in the range of 0.6-0.

7.

8. The preparation method according to claim 6, characterized in that The size of the groove along the first direction ranges from 0.8 μm to 1 μm.

9. A power device, characterized in that: The method is described in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The power device according to claim 9.

Images