Thermal tuning laser chip with novel structure and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor laser chips, and provides a thermal tuning laser chip with a novel structure and a manufacturing method thereof. The ridge waveguide structure comprises a substrate and a plurality of functional layers which are sequentially grown on the substrate, and specifically, a plurality of heat insulation grooves are respectively etched in channels on two sides of a ridge waveguide; the plurality of heat insulation grooves are mutually spaced, and each heat insulation groove comprises a first heat insulation part and a second heat insulation part; a supporting structure grows on the inner wall of the heat insulation groove, the supporting structure comprises a first supporting part and a second supporting part, the first supporting part completely covers the first heat insulation part, and the second supporting part covers the third functional layer of the second heat insulation part; and the space between the third functional layer and the first functional layer is hollowed to form a hollow heat insulation area penetrating through the plurality of heat insulation grooves. According to the invention, heat loss in the chip is avoided, and the thermal insulation effect of the chip is improved, so that the thermal tuning efficiency of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor laser chips, and in particular to a thermally tunable laser chip with a novel structure and a manufacturing method thereof. Background Art

[0002] As a laser that can continuously change the laser output wavelength within a certain range, a tunable semiconductor laser is a key device for dense wavelength division multiplexing systems and future all-optical networks. Its superiority will become increasingly prominent under the current situation where people's demand for the transmission speed and capacity of network systems is getting higher and higher. The unique advantages of tunable lasers in terms of tuning range and narrow linewidth have attracted many researchers to study the structure to adjust parameters such as temperature and current in the laser cavity so that different wavelengths can be emitted.

[0003] In a tunable semiconductor laser, the temperature in the optical cavity is mainly adjusted by a resistor. However, in the prior art, the heat insulation effect of the semiconductor laser is poor, and the heat generated by the resistor is easily transmitted to the outside, resulting in low utilization rate of the heat of the resistor and the temperature in the optical cavity not reaching the expected temperature, thus affecting the thermal tuning efficiency of the chip.

[0004] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the heat insulation effect of the tunable semiconductor laser chip is poor and the thermal tuning efficiency of the chip is low.

[0006] The present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a thermally tunable laser chip with a novel structure, including a substrate 1 and a plurality of functional layers 2 sequentially grown on the substrate 1;

[0008] A plurality of heat insulation grooves 3 are respectively etched in the channels on both sides of the ridge waveguide; wherein, the plurality of heat insulation grooves 3 are spaced apart from each other, and the heat insulation groove 3 includes a first heat insulation part 31 leading to the first functional layer 211 and a second heat insulation part 32 leading to the second functional layer 212;

[0009] A support structure 4 is grown on the inner wall of the heat insulation groove 3, and the support structure 4 includes a first support part 41 and a second support part 42. The first support part 41 completely covers the first heat insulation part 31, and the second support part 42 covers the third functional layer 213 of the second heat insulation part 32; wherein, the third functional layer 213 is located above the second functional layer 212, and the second functional layer 212 is located above the first functional layer 211;

[0010] A hollow heat insulation area 5 penetrating through a plurality of heat insulation grooves 3 is formed by hollowing out between the third functional layer 213 and the first functional layer 211; wherein, the hollow heat insulation area 5 is formed by pouring a corrosive liquid into the second heat insulation part 32 and performing lateral corrosion by the corrosive liquid.

[0011] Preferably, there are three functional layers 2 spaced between the third functional layer 213 and the first functional layer 211, which are the second functional layer 212, the fourth functional layer 214, and the fifth functional layer 215 in sequence from the substrate 1 upwards.

[0012] Using the second heat insulation part 32 as a longitudinal channel, pouring a first corrosive liquid into the longitudinal channel to corrode away the fourth functional layer 214 to form a lateral channel 6, and pouring a second corrosive liquid into the longitudinal channel and the lateral channel 6 to corrode away the second functional layer 212 and the fifth functional layer 215 to form a complete hollow heat insulation area 5.

[0013] Preferably, the support structure 4 includes an inner layer and an outer layer, the inner layer is a metal layer, and the outer layer is an oxide film; wherein, the inner layer is the layer close to the heat insulation groove 3.

[0014] Preferably, the plurality of functional layers 2 grown sequentially on the substrate 1 includes at least one of a lower cladding layer 221, a lower sacrificial layer 222, a lower etch stop layer 223, a middle sacrificial layer 224, an upper etch stop layer 225, an upper sacrificial layer 226, an active layer 227, and a contact layer 228.

[0015] In a second aspect, the present invention also provides a method for fabricating a novel structure of a thermal tuning laser chip, which pre-grows a plurality of functional layers 2 on a substrate 1 in sequence, and the method includes:

[0016] Etching a ridge waveguide on the plurality of functional layers 2, wherein the channel of the ridge waveguide is etched to the active layer 227.

[0017] By photolithography, the positions of the first heat insulation part 31 and the second heat insulation part 32 are drawn, the position of the first heat insulation part 31 is etched and / or wet-etched to a first depth, the position of the second heat insulation part 32 is etched and / or wet-etched to a second depth, a plurality of mutually spaced heat insulation grooves 3 are obtained, a first support part 41 is grown on the first heat insulation part 31, and a second support part 42 covering the upper sacrificial layer 226 is grown on the second heat insulation part 32; wherein, the first depth is the depth at which the channel of the ridge waveguide reaches the lower cladding layer 221, and the second depth is the depth at which the channel of the ridge waveguide reaches the middle sacrificial layer 224.

[0018] Performing lateral corrosion from the second heat insulation part 32 to obtain a hollow heat insulation area 5 penetrating through a plurality of heat insulation grooves 3.

[0019] Preferably, the positions of the first heat-insulating portion 31 and the second heat-insulating portion 32 are drawn by photolithography, the position of the first heat-insulating portion 31 is etched to a first depth and / or wet-etched, the position of the second heat-insulating portion 32 is etched to a second depth and / or wet-etched, so as to obtain a plurality of spaced-apart heat-insulating grooves 3, a first support portion 41 is grown on the first heat-insulating portion 31, and a second support portion 42 covering the upper sacrificial layer 226 is grown on the second heat-insulating portion 32, specifically including:

[0020] In the ridge waveguide channel, the position of the first heat-insulating portion 31 is drawn by photolithography, the position of the first heat-insulating portion 31 is etched until reaching the upper sacrificial layer 226, the upper sacrificial layer 226 of the InP material is etched with a hydrochloric acid-based solution until reaching the upper etch stop layer 225, and then further photolithography and / or wet etching are performed until reaching the lower cladding 211 to form the first heat-insulating portion 31, and the first support portion 41 is grown on the first heat-insulating portion 31;

[0021] After the growth of the first support portion 41 is completed, the position of the second heat-insulating portion 32 is drawn by photolithography in the ridge waveguide channel, and photolithography and / or wet etching are performed until reaching the middle sacrificial layer 224 to form the second heat-insulating portion 32, and the second support portion 42 is grown in the second heat-insulating portion 32; wherein, before the growth of the second support portion 42, the second heat-insulating portion 32 and the first heat-insulating portion 31 are separated by the first support portion 41.

[0022] Preferably, the lateral etching is performed from the second heat-insulating portion 32 to obtain a hollow heat-insulating region 5 penetrating through the plurality of heat-insulating grooves 3, specifically including:

[0023] Taking the second heat-insulating portion 32 as a longitudinal channel, pouring a sulfuric acid-based solution into the longitudinal channel, and performing etching for a first preset time to etch away the lower etch stop layer 223 to form a lateral channel 6;

[0024] Pouring a hydrochloric acid-based solution into the longitudinal channel and the lateral channel 6, and performing etching for a second preset time to etch away the remaining middle sacrificial layer 224 and the lower sacrificial layer 222 to form a complete hollow heat-insulating region 5.

[0025] Preferably, the ridge waveguide is etched on the plurality of functional layers 2, specifically including:

[0026] The corresponding ridge waveguide pattern is defined on the surface of the functional layer 2 sequentially grown on the substrate 1 by photolithography, and etching is performed on the semiconductor chip based on the defined ridge waveguide pattern, and the etching depth exceeds the contact layer 228;

[0027] An acidic etching solution is selected to etch the contact layer 228 so as to form channels on the left and right sides of the waveguide of the semiconductor chip.

[0028] Preferably, the fabrication of the laser chip is performed on the laser wafer 9, and the method further includes:

[0029] A plurality of laser chips are provided on the laser wafer 9, and an ultrasonic detector 10 is provided at the contact position between the laser wafer 9 and the laser chip. The ultrasonic detector 10 includes a probe 101 and a processor 102. The probe 101 of the ultrasonic detector 10 is in seamless contact with the substrate 1 of the laser chip to detect the completion degree of the cavity heat insulation region 5 in the laser chip; wherein, the ultrasonic detector 10 is provided at the position where the second heat insulation part 32 is located and / or at the interval position between the plurality of heat insulation grooves 3;

[0030] When the cavity heat insulation region 5 of the corresponding laser chip is completely formed according to the detection of the ultrasonic detector 10, the fabrication of the laser chip is completed and qualified.

[0031] Preferably, the detection of the completion degree of the cavity heat insulation region 5 in the laser chip specifically includes:

[0032] A transmitted wave is sent by the probe 101 towards the substrate 1. When the transmitted wave enters the etching solution from the substrate 1, a primary reflection occurs and the probe 101 receives a first echo. When the transmitted wave enters the corresponding upper functional layer 2 from the etching solution, a secondary reflection occurs and the probe 101 receives a second echo;

[0033] The completion degree of the cavity heat insulation region 5 is determined according to the time difference between the first echo and the second echo received by the probe 101.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows: By providing a cavity heat insulation region below the ridge waveguide, the present invention prevents heat from being transferred from the lower part to the substrate, and heat insulation grooves are provided in the channel on both sides of the ridge waveguide to prevent heat from being transferred to the edge of the chip, thereby preventing heat from being transferred from the edge of the chip to the substrate and leaking out from the substrate, avoiding heat dissipation inside the chip, improving the heat insulation effect of the chip, and thus improving the thermal tuning efficiency of the chip. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a top view structural schematic diagram of a novel structure of a thermal tuning laser chip provided by an embodiment of the present invention;

[0037] Figure 2 It is a cross-sectional view during the manufacturing process of the first novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0038] Figure 3 It is a cross-sectional view during the manufacturing process of the second novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0039] Figure 4 It is a cross-sectional view of the first novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0040] Figure 5 It is a cross-sectional view of the second novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0041] Figure 6 It is a cross-sectional view of the third novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0042] Figure 7 It is a schematic layout diagram of heat insulation grooves in a novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0043] Figure 8 It is a cross-sectional view of the fourth novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0044] Figure 9 It is a schematic layout diagram of heat insulation grooves in another novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0045] Figure 10 It is a cross-sectional view of the fifth novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0046] Figure 11 It is a cross-sectional view of the sixth novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0047] Figure 12 It is a cross-sectional view during the manufacturing process of the third novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0048] Figure 13 It is a cross-sectional view of each functional layer in a novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0049] Figure 14 It is a flowchart of a manufacturing method of a novel-structured thermal tuning laser chip provided by an embodiment of the present invention;

[0050] Figure 15It is a flowchart of another method for fabricating a thermally tunable laser chip with a novel structure provided by an embodiment of the present invention;

[0051] Figure 16 It is a schematic structural diagram of a laser wafer used in a method for fabricating a thermally tunable laser chip with a novel structure provided by an embodiment of the present invention;

[0052] Figure 17 It is a schematic structural diagram of an ultrasonic detector in a laser wafer used in a method for fabricating a thermally tunable laser chip with a novel structure provided by an embodiment of the present invention;

[0053] Figure 18 It is a partially enlarged schematic diagram of a wafer and a laser chip during the fabrication process of a thermally tunable laser chip with a novel structure provided by an embodiment of the present invention;

[0054] Figure 19 It is a partially enlarged schematic diagram of a wafer and a laser chip during the fabrication process of another thermally tunable laser chip with a novel structure provided by an embodiment of the present invention;

[0055] Figure 20 It is a schematic diagram of the position of an ultrasonic detector in a laser wafer used in a method for fabricating a thermally tunable laser chip with a novel structure provided by an embodiment of the present invention.

[0056] In all the drawings, the reference numerals are as follows, where:

[0057] 1. Substrate; 2. Functional layer; 211. First functional layer; 212. Second functional layer; 213. Third functional layer; 214. Fourth functional layer; 215. Fifth functional layer; 221. Lower cladding layer; 222. Lower sacrificial layer; 223. Lower etch stop layer; 224. Middle sacrificial layer; 225. Upper etch stop layer; 226. Upper sacrificial layer; 227. Active layer; 228. Contact layer; 3. Thermal insulation groove; 31. First thermal insulation part; 32. Second thermal insulation part; 4. Support structure; 41. First support part; 42. Second support part; 5. Void thermal insulation region; 6. Lateral channel; 7. Resistor; 8. Electrode; 9. Laser wafer; 10. Ultrasonic detector; 101. Probe; 102. Processor. Detailed implementation manners

[0058] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0059] In the description of the present invention, the orientation or positional relationship indicated by the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and does not require the present invention to be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0060] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0061] Embodiment 1:

[0062] Embodiment 1 of the present invention provides a thermally tunable laser chip with a novel structure, including a substrate 1 and a plurality of functional layers 2 sequentially grown on the substrate 1; as Figure 1 shown, specifically:

[0063] A plurality of thermal insulation grooves 3 are respectively etched in the channels on both sides of the ridge waveguide, as Figure 1 shown; wherein, the plurality of thermal insulation grooves 3 are spaced from each other, and the thermal insulation groove 3 includes a first thermal insulation part 31 leading to the first functional layer 211 and a second thermal insulation part 32 leading to the second functional layer 212, as Figure 2 and Figure 3 shown; wherein, the etching of a plurality of thermal insulation grooves 3 in the channels on both sides of the ridge waveguide means that a plurality of thermal insulation grooves 3 are etched in one channel of the ridge waveguide, and a plurality of thermal insulation grooves 3 are also etched on the other side of the ridge waveguide. There is a gap between the thermal insulation grooves 3 located on both sides of the ridge waveguide, and there is also a gap between the plurality of thermal insulation grooves 3 located on one side of the ridge waveguide.

[0064] A support structure 4 is grown on the inner wall of the thermal insulation groove 3. The support structure 4 includes a first support part 41 and a second support part 42. The first support part 41 completely covers the first thermal insulation part 31, and the second support part 42 covers the third functional layer 213 up to the second thermal insulation part 32, as Figure 2 and Figure 3 shown, and the first support part 41 and the second support part 42 are connected to each other longitudinally in the ridge waveguide of the chip, that is, as Figure 1 and Figure 8As shown, one side of the first support part 41 is connected to one side between the second support part 42 (in actual use, it can be that after forming the first heat insulation part 31, growing the first support part 41, then forming the second heat insulation part 32. At this time, the second heat insulation part 32 is separated from the first heat insulation part 31 by the first support part 41, and then growing the second support part 42, so that the first support part 41 and the second support part 42 are connected), so as to jointly play a supporting role; wherein, the third functional layer 213 is located above the second functional layer 212, and the second functional layer 212 is located above the first functional layer 211.

[0065] A hollow heat insulation area 5 is formed by hollowing out between the third functional layer 213 and the first functional layer 211, with multiple heat insulation grooves 3 passing through, as Figure 4 、 Figure 5 and Figure 6 shown; wherein, the hollow heat insulation area 5 is formed by pouring etching liquid into the second heat insulation part 32 and performing lateral etching by the etching liquid. The multiple heat insulation grooves 3 passing through not only refer to the multiple heat insulation grooves 3 passing through one side of the ridge waveguide, but also include the multiple heat insulation grooves 3 passing through both sides of the ridge waveguide. The lateral etching means etching along the plane where the functional layer 2 is located, rather than longitudinally forming channels.

[0066] Among them, Figure 2 and Figure 3 can be understood as a schematic diagram before the hollow heat insulation area 5 is formed, Figure 2 showing the structure of the first heat insulation part 31 and the first support part 41, Figure 3 showing the structure of the second heat insulation part 32 and the second support part 42. Among them, the conduction of the second heat insulation part 32 to the second functional layer 212 is described on the basis of not considering the hollow heat insulation area 5. It can be understood that before the hollow heat insulation area 5 is formed, the second heat insulation part 32 conducts to the second functional layer 212, and the structure at this time is as Figure 3 shown; Figure 4 、 Figure 5 and Figure 6 are schematic diagrams of the chip after the hollow heat insulation area 5 is formed; among them, Figure 4 is Figure 1 a longitudinal sectional schematic diagram at the 2b position in Figure 4 . In actual use, Figure 4 parts of the first heat insulation part 31 near both sides of the chip may also be partially etched, which are not shown in Figure 5 is Figure 1 a longitudinal sectional schematic diagram at the 1b position in Figure 5 shown. Figure 6 isFigure 1 Cross-sectional schematic view of the 3b position in the middle, showing the spaced portions between multiple first heat insulation portions 31 of the unilateral channel of the ridge waveguide.

[0067] Among them, since the first support portion 41 and the second support portion 42 are connected, the suspended portion of the second heat insulation portion 32 can be supported by the support structure 4. Moreover, since the heat insulation grooves 3 are spaced apart, in the spaced portions between multiple heat insulation grooves 3, only the third functional layer 213 and the first functional layer 211 are hollowed out, and at least one functional layer 2 below the channel of the ridge waveguide still remains intact. Therefore, it also forms a support for the suspended portion by connecting with the suspended portion of the second heat insulation portion 32, thereby ensuring effective support for the overall structure of the chip while achieving a larger heat insulation space and enhancing the stability of the chip structure.

[0068] In actual use, each functional layer 2 is tightly connected and fixed to the inner wall of the chip. The inner wall of the chip can be the inner walls around the chip or the upper inner wall of the chip, specifically the inner wall of the chip that is bonded or fixed to the remaining functional layer 2. Thus, when the area below the ridge waveguide is hollowed out, the ridge waveguide can be suspended and supported by the remaining functional layer 2.

[0069] Through research and testing, it is found that the heat generated by the chip during normal operation is mainly exchanged with the outside air through the substrate 1 material. In this embodiment, by setting a hollow heat insulation area 5 below the ridge waveguide, heat transfer from the bottom to the substrate 1 is blocked, and heat insulation grooves 3 are provided on both sides of the channel of the ridge waveguide to block heat transfer to the edge of the chip, thereby preventing heat from being transferred from the chip edge to the substrate 1 and leaking out from the substrate 1, avoiding heat dissipation inside the chip, improving the heat insulation effect of the chip, and thus improving the thermal tuning efficiency of the chip.

[0070] In actual use, multiple heat insulation grooves 3 on both sides of the ridge waveguide can be aligned and distributed, as Figure 7 shown. At this time, a partial cross-sectional view obtained by slicing the heat insulation grooves along the optical axis direction of the chip (i.e., slicing along 1a in Figure 1 ) is as Figure 8 shown. Figure 8 Only two heat insulation grooves and the structure between them are shown. In actual use, when there are multiple heat insulation grooves, it should present a regular reuse of the first heat insulation portion 31, the second heat insulation portion 32, and the hollow heat insulation area 5 in Figure 8 .

[0071] There is also a preferred implementation manner, as Figure 9As shown, multiple heat insulation grooves 3 on both sides of the ridge waveguide are staggeredly distributed, so that there are two parts: a suspended structure (the part of the heat insulation groove 3) and a non-suspended structure (the interval part between multiple heat insulation grooves 3), which are staggeredly distributed not only in the axial direction of the laser, but also in the vertical direction of the ridge waveguide, so as to balance the overall uniform force of the support structure 4 and form a structure with one side suspended and the other side still connected to the functional layer 2, such as Figure 10 and Figure 11 shown, to increase its stability, where Figure 10 is Figure 9 a schematic cross-sectional view at the 2b position in Figure 11 is Figure 9 a schematic cross-sectional view at the 1b position in. Wherein, the length d1 occupied by each heat insulation groove 3 in the axial extension direction of the laser and the preset distance L between every two heat insulation grooves 3 are obtained by those skilled in the art through empirical analysis. When multiple heat insulation grooves 3 are staggeredly arranged, there is also a preferred implementation manner, that is, the length d1 occupied by each heat insulation groove 3 in the axial extension direction of the laser is the same as the preset distance L between every two heat insulation grooves 3 on one side of the ridge waveguide.

[0072] In the preferred implementation manner, as Figure 12 shown, there are three functional layers 2 between the third functional layer 213 and the first functional layer 211, which are the second functional layer 212, the fourth functional layer 214, and the fifth functional layer 215 in sequence from the substrate 1 direction upwards; taking the second heat insulation part 32 as a longitudinal channel, pouring a first etching solution into the longitudinal channel to etch away the fourth functional layer 214 to form a transverse channel 6, and pouring a second etching solution into the longitudinal channel and the transverse channel 6 to etch away the second functional layer 212 and the fifth functional layer 215 to form a complete cavity heat insulation area 5. The etching away of the fourth functional layer 214, the second functional layer 212, and the fifth functional layer 215 all etch away the central parts of the corresponding functional layers 2, and partial structures of the functional layers 2 are still reserved on the inner walls around the chip.

[0073] In this embodiment, by forming a transverse channel 6 in the second heat insulation part 32, the second etching solution poured into the transverse channel 6 can have a large contact area with the functional layers 2 to be etched (the second functional layer 212 and the fifth functional layer 215), so as to accelerate etching, improve the etching effect, and ensure the uniformity of etching by etching from the middle position upwards and downwards, ensuring the rapid and stable formation of the cavity heat insulation area 5.

[0074] Wherein, the support structure 4 can be composed of one or more layers, or can also be a single dielectric layer. In this regard, the embodiment of the present invention also provides a preferred implementation manner, which specifically includes:

[0075] The support structure 4 includes an inner layer and an outer layer. The inner layer is a metal layer, and the outer layer is an oxide film. Among them, the inner layer is the layer closer to the heat insulation groove 3. Among them, the metal layer is obtained by sputtering. The metal layer may include metals Ti and Pt. The oxide film can be deposited by chemical vapor deposition (abbreviated as CVD).

[0076] In this preferred embodiment, by providing the support structure 4 on the inner wall of the heat insulation groove 3, it not only plays the role of enhancing heat insulation and preventing the corresponding functional layer 2 from being corroded in subsequent processes, improving the thermal tuning efficiency of the chip, but also through the support structure 4 and the multiple functional layers 2 connected to its outer wall, plays a corresponding supporting role for the ridge waveguide, thereby realizing double support for the ridge waveguide, enhancing the stability of the ridge waveguide, and preventing the chip structure from collapsing due to external forces and other factors. And in this embodiment, by integrating heat insulation and support, the chip space required for separately setting a heat insulation structure and a support frame is reduced. And by arranging the support structure 4 on the inner wall of the heat insulation groove 3, on the one hand, the manufacturing process difficulty is reduced, and on the other hand, the existing space is reasonably utilized, without the need to create another space, reducing the space occupied by the chip, providing a basis for the small volume of the chip.

[0077] In an alternative embodiment, as Figure 13 shown, the multiple functional layers 2 sequentially grown on the substrate 1 include at least one of a lower cladding layer 221, a lower sacrificial layer 222, a lower etch stop layer 223, a middle sacrificial layer 224, an upper etch stop layer 225, an upper sacrificial layer 226, an active layer 227, and a contact layer 228.

[0078] In this embodiment, the first functional layer 211 is the lower cladding layer 221, the second functional layer 212 is the lower sacrificial layer 222, the third functional layer 213 is the upper etch stop layer 225, the fourth functional layer 214 is the lower etch stop layer 223, and the fifth functional layer 215 is the middle sacrificial layer 224.

[0079] The specific structure of the above-mentioned functional layer 2 depends on the actual scenario, and can be one or more of a laser layer structure, a detector layer structure, a modulator layer structure, or a passive waveguide layer structure. In the actual implementation process, the above-mentioned multiple functional layers 2 are usually designed in combination to meet the different thermal tuning laser chip requirements. And as the most significant in terms of effect performance, usually the practical significance of the laser layer structure and the modulator layer structure is the greatest. Other functional layers 2 are designed according to the support requirements, heat insulation requirements, and manufacturing process of the ridge waveguide. The designed parameters include but are not limited to the material of the functional layer 2, the thickness of the functional layer 2, and the arrangement method of the functional layer 2.

[0080] In an embodiment of the present invention, a more practical complex structure diagram is also provided, such as Figure 1 shown, which further includes two parts, a resistor 7 and an electrode 8. Each resistor 7 is sputtered above the dielectric layer on the ridge waveguide of the laser, and each resistor 7 is connected to a group of electrodes 8.

[0081] The heat insulation grooves 3, the support structure 4, and the cavity heat insulation region 5 in this embodiment can be applied to the regions of the thermally tunable laser chip, including but not limited to the front grating region, the phase region, and the rear grating region. This embodiment can be applied to a specific region alone or used in combination in multiple regions.

[0082] In an embodiment of the present invention, the first, second, and other limiting descriptions do not refer to a specific order meaning. They are merely used to distinguish the corresponding limited objects from the same category and are added for the convenience of describing two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0083] Embodiment 2:

[0084] An embodiment of the present invention provides a method for manufacturing a thermally tunable laser chip with a new structure, which can be used to manufacture the thermally tunable laser chip with the new structure described in Embodiment 1. It should be noted that the focus of the embodiment of the present invention is on the method process output related to the substantial difference features. Other processes such as manufacturing the electrode 8, etc., do not belong to the improvement scope of the present invention and are also conventional prior art means. Therefore, they will not be elaborated in the following text of the embodiment of the present invention. In an embodiment of the present invention, as Figure 14 shown, multiple functional layers 2 are sequentially grown on the substrate 1 in advance. The method includes:

[0085] In step 201, a ridge waveguide is etched on the multiple functional layers 2, wherein the channel of the ridge waveguide is etched to the active layer 227.

[0086] In step 202, the positions of the first heat insulation part 31 and the second heat insulation part 32 are drawn by photolithography. The position of the first heat insulation part 31 is etched and / or wet-etched to a first depth, and the position of the second heat insulation part 32 is etched and / or wet-etched to a second depth, to obtain a plurality of spaced-apart heat insulation grooves 3; wherein the first depth is the depth at which the channel of the ridge waveguide reaches the lower cladding layer 221, and the second depth is the depth at which the channel of the ridge waveguide reaches the middle sacrificial layer 224.

[0087] In step 203, a first support part 41 is grown on the first heat insulation part 31, and a second support part 42 covering the upper sacrificial layer 226 is grown on the second heat insulation part 32.

[0088] In step 204, lateral etching is performed on the second heat insulation portion 32 to obtain a hollow heat insulation region 5 that penetrates through a plurality of heat insulation grooves 3.

[0089] In this embodiment, before manufacturing the hollow heat insulation region 5, a support structure 4 is preset to provide sufficient support for the ridge waveguide, so as to ensure that the ridge waveguide structure does not collapse during and after the subsequent manufacturing of the hollow heat insulation region 5.

[0090] In the embodiment of the present invention, an implementation scenario of a laser is given, as Figure 13 shown, the growth stratified substrate 1 specifically includes:

[0091] On the substrate 1, a lower cladding layer 221, a lower sacrificial layer 222, a lower etch stop layer 223, a middle sacrificial layer 224, an upper etch stop layer 225, an upper sacrificial layer 226, an active layer 227, and a contact layer 228 made of a multi-element material are sequentially grown. The present invention also provides specific material parameter usages of the functional layer 2, specifically including:

[0092] The lower cladding layer 221 is made of InGaAsP material, the lower sacrificial layer 222 is made of InP material, the lower etch stop layer 223 is made of InGaAsP material, the middle sacrificial layer 224 is made of InP material, the upper etch stop layer 225 is made of InGaAsP, the upper sacrificial layer 226 is made of InP material, the active layer 227 is made of InGaAsP material, and the contact layer 228 is made of a part of InP material and a part of InGaAsP material.

[0093] In an alternative embodiment, the thickness of the substrate 1 is greater than 150 μm, the thicknesses of the lower etch stop layer 223 and the upper etch stop layer 225 are about 0.02 μm, the total thicknesses of the lower sacrificial layer 222, the middle sacrificial layer 224, and the upper sacrificial layer 226 are about 4 μm, the thickness of the active layer 227 is about 0.4 μm, the thickness of the InP material in the contact layer 228 is about 1.6 μm, and the thickness of the InGaAsP material is about 0.2 μm.

[0094] Among them, the processing technology for each functional layer 2 is determined by the processing requirements of the corresponding functional layer 2 and the material of the functional layer 2. Next, taking the materials of each functional layer 2 given in this embodiment as examples, the processes of generating the corresponding ridge waveguide, heat insulation grooves 3, support structure 4, and hollow heat insulation region 5 of the present invention will be elaborated one by one.

[0095] In an alternative embodiment, the positions where the first thermal insulation portion 31 and the second thermal insulation portion 32 are drawn by lithography are etched and / or wet-etched to a first depth at the position of the first thermal insulation portion 31 and to a second depth at the position of the second thermal insulation portion 32 to obtain a plurality of spaced-apart thermal insulation grooves 3. A first support portion 41 is grown on the first thermal insulation portion 31, and a second support portion 42 covering the upper sacrificial layer 226 is grown on the second thermal insulation portion 32, as Figure 15 shown, specifically including:

[0096] In step 301, the position where the first thermal insulation portion 31 is located (which can be understood as the surface pattern of the first thermal insulation portion 31) is drawn by lithography in the ridge waveguide channel, and the position where the first thermal insulation portion 31 is located is etched (such as reactive ion etching (abbreviated as: RIE etching)) until reaching the upper sacrificial layer 226. The upper sacrificial layer 226 of the InP material is etched with a hydrochloric acid-based solution until reaching the upper etch stop layer 225, and then further lithography and / or wet etching are performed until reaching the lower cladding 211 to form the first thermal insulation portion 31. A first support portion 41 is grown on the first thermal insulation portion 31. After reaching the upper sacrificial layer 226, it can be considered that a first region is formed, and a dielectric layer can be grown on the inner wall of the first region. The position where the first thermal insulation portion 31 is located (which can be understood as the surface pattern of the first thermal insulation portion 31) is drawn by lithography on the surface of the dielectric layer, and then subsequent downward etching is performed. Among them, the grown dielectric layer can be retained as part of the subsequently grown support structure 4, or it can be removed (such as etched off with an HF solution) and then the support structure 4 is regrown.

[0097] In step 302, after the growth of the first support portion 41 is completed, the position where the second thermal insulation portion 32 is located (which can be understood as the surface pattern of the second thermal insulation portion 32) is drawn by lithography in the ridge waveguide channel, and lithography and / or wet etching are performed until reaching the middle sacrificial layer 224 to form the second thermal insulation portion 32. A second support portion 42 is grown in the second thermal insulation portion 32. Among them, before the growth of the second support portion 42, the second thermal insulation portion 32 and the first thermal insulation portion 31 are separated by the first support portion 41 and no other functional layer 2 is interposed, so that after the growth of the second support portion 42, the first support portion 41 and the second support portion 42 are connected. Among them, the manufacturing methods of the first thermal insulation portion 31 and the second thermal insulation portion 32 are implemented based on the same concept, and the difference is only that the final reached functional layer 2 is different.

[0098] In an alternative embodiment, the lateral etching from the second thermal insulation portion 32 to obtain a hollow thermal insulation region 5 penetrating through a plurality of thermal insulation grooves 3 specifically includes:

[0099] Using the second heat insulation portion 32 as a longitudinal channel, pour a sulfuric acid-based solution into the longitudinal channel, and perform etching for a first preset time to etch away the lower etching stop layer 223 to form a transverse channel 6; pour a hydrochloric acid-based solution into the longitudinal channel and the transverse channel 6, and perform etching for a second preset time to etch away the remaining middle sacrificial layer 224 and the lower sacrificial layer 222 to form a complete hollow heat insulation region 5.

[0100] The method for obtaining a ridge waveguide by etching specifically includes: defining a corresponding ridge waveguide pattern on the surface of the functional layer 2 grown on the substrate 1 in sequence by photolithography, and performing etching on the semiconductor chip based on the defined ridge waveguide pattern, with the etching depth exceeding the contact layer 228. An acidic etching solution is selected to etch the contact layer 228 to form channels on both left and right sides of the waveguide of the semiconductor chip.

[0101] The upper cross-section of the ridge waveguide and the heat insulation groove 3 fabricated by photolithography can be square, circular, or other shapes, which can be designed according to actual situations and will not be specifically limited herein.

[0102] An optional formulation of the sulfuric acid-based solution (H2SO4-based solution) is composed of H2O2 and H2SO4. An optional formulation of the hydrochloric acid-based solution is HCL and H3PO4, where the proportion of HCL to H3PO4 is 1:3.

[0103] This embodiment also provides a preferred implementation manner. Specifically: fabricate a laser chip on the laser wafer 9, and the method further includes:

[0104] A plurality of laser chips are arranged on the laser wafer 9. An ultrasonic detector 10 is arranged at the contact position between the laser wafer 9 and the laser chip. The ultrasonic detector 10 includes a probe 101 and a processor 102. The probe 101 of the ultrasonic detector 10 is in seamless contact with the substrate 1 of the laser chip to detect the completion degree of the hollow heat insulation region 5 in the laser chip; wherein, the ultrasonic detector 10 is arranged at the position where the second heat insulation portion 32 is located and / or at the interval position between a plurality of heat insulation grooves 3; when the hollow heat insulation region 5 of the corresponding laser chip is completely formed according to the detection by the ultrasonic detector 10, the fabrication of the laser chip is completed and qualified.

[0105] The laser wafer 9 refers to a silicon wafer used for fabricating silicon semiconductor integrated circuits. Since its shape is circular, it is called a wafer; various circuit element structures can be processed and fabricated on the silicon wafer to become an IC product with specific electrical functions (for example, a laser chip, a detector chip, a driver chip, etc.).

[0106] On the laser wafer 9, as Figure 16As shown, multiple laser chips are arranged in an array to achieve mass production of laser chips.

[0107] As Figure 17 shown, the ultrasonic detector 10 includes: a probe 101 and a corresponding processor 102. The probe 101 includes an ultrasonic transmitting unit and an ultrasonic receiving unit for emitting a transmitted wave and receiving an echo. The processor 102 is used to process and judge the completion degree of the cavity heat insulation area 5 according to the signal fed back by the probe 101.

[0108] Among them, each laser chip corresponds to one or more probes 101. The number of corresponding probes 101 is jointly analyzed and determined by those skilled in the art according to the internal structure and size of the laser chip. The probes 101 of multiple laser chips can belong to the same ultrasonic detector 10, that is, uniformly processed by the same processor 102, or the probes 101 of one laser chip correspond to one ultrasonic detector 10.

[0109] Since the acoustic impedance of the functional layer 2 and the etching solution is different, when ultrasonic waves enter the etching solution from the corresponding functional layer 2 or enter the corresponding functional layer 2 from the etching solution, the ultrasonic waves will exhibit the phenomena of projection and reflection. And because multiple functional layers 2 are all solids and their acoustic impedances differ little, the transmittance of ultrasonic waves between multiple functional layers 2 is much greater than the reflectance, and it can be regarded that ultrasonic waves can directly transmit between multiple functional layers 2. According to this principle, combined with the manufacturing structure characteristics of the laser chip in this embodiment, the method for detecting the completion degree of the cavity heat insulation area 5 in the laser chip specifically includes:

[0110] The probe 101 emits a transmitted wave towards the substrate 1. When the transmitted wave enters the etching solution from the substrate 1, a primary reflection occurs, and the probe 101 receives a first echo. When the transmitted wave enters the corresponding upper functional layer 2 from the etching solution, a secondary reflection occurs, and the probe 101 receives a second echo; according to the time difference between the first echo and the second echo received by the probe 101, the completion degree of the cavity heat insulation area 5 is determined.

[0111] As Figure 18 shown, when the cavity heat insulation area 5 is not etched completely, for example, after obtaining the lateral channel 6 by etching, when the ultrasonic wave passes through the lower sacrificial layer 222 and reaches the lateral channel 6, part of the ultrasonic wave is reflected by the etching solution to obtain a first echo, and the other part enters the etching solution and continues to propagate until it passes through the etching solution and reaches the middle sacrificial layer 224, and a second echo is obtained due to the reflection of the middle sacrificial layer 224. By processing the time difference between the first echo and the second echo, the height of the etched-through area is obtained, so as to judge whether the cavity heat insulation area 5 is completed.

[0112] As Figure 18As shown, when only the lateral channel 6 is etched and the cavity heat insulation region 5 is not formed, the time difference between the first echo and the second echo is relatively short. When the cavity heat insulation region 5 is about to be formed, as Figure 19 shown, the time difference between the first echo and the second echo is relatively long.

[0113] It should be noted that when ultrasonic waves propagate between the functional layers 2, and between the etching solution and the functional layer 2, there are corresponding reflected light parts and transmitted light parts. However, due to the small difference in acoustic impedance of the functional layers 2, the reflected light parts can be ignored in this solution, or the receiving and sensing range of the probe 101 can be set so that this part of the reflected light cannot be sensed and received by the probe 101, thus avoiding the influence of this part of the reflected light on the solution. And the transmitted light part that enters the functional layer 2 through the etching solution only causes a large attenuation of the second echo relative to the ultrasonic waves incident into the etching solution, and has no influence on measuring the time difference between the first echo and the second echo.

[0114] In this embodiment, while ensuring that the lower etching stop layer 223 at the position below the ridge waveguide is hollowed out, it is also necessary to ensure that a part of the structure of the lower etching stop layer 223 remains on the inner walls on both sides of the laser chip to provide a better supporting effect on the ridge waveguide. Therefore, ultrasonic detection is also required for the positions on both sides of the laser chip. Here is a specific implementation:

[0115] Lasers are arranged at the position of the laser wafer 9 directly below the ridge waveguide, and at the positions of the laser wafer 9 on both sides of the ridge waveguide and at corresponding lengths from the center position of the ridge waveguide, as Figure 20 shown. Among them, the first probe 101 is located directly below the ridge waveguide and is used to detect whether the cavity heat insulation region 5 below the ridge waveguide is hollowed out. In actual use, multiple first probes 101 can be set, respectively located at the position below the ridge waveguide between two heat insulation grooves 3, at the position below the ridge waveguide between two first heat insulation parts 31, and at the interval position between two heat insulation grooves 3 on the same side of the ridge waveguide. When all the first probes 101 detect that the cavity heat insulation region 5 is hollowed out, it is considered that the cavity heat insulation region 5 is completed. The second probe 101 and the third probe 101 are respectively located on both sides of the ridge waveguide and are used to detect whether there is still a part of the structure of the lower etching stop layer 223 remaining at the positions on both sides of the channel.

[0116] Etch the lower etching stop layer 223 with an H2SO4-based solution for a preset etching time, and perform ultrasonic detection on the laser chip before the etching is about to end.

[0117] Wherein, when the first probe 101 receives a first echo and a second echo, and the time difference between the first echo and the second echo is greater than or equal to a preset time difference, it is considered that the lower etch stop layer 223 below the ridge waveguide has been etched through. Meanwhile, the states of the second probe 101 and the third probe 101 are judged. If neither the second probe 101 nor the third probe 101 receives an echo, it is considered whether there is still a partial structure at the positions of the lower etch stop layer 223 on both sides of the channel. When the above two points are satisfied, the chip fabrication is completed.

[0118] If the second probe 101 or the third probe 101 receives an echo, it is considered that there is over-etching and the laser chip fabrication is unqualified.

[0119] The above implementation method uses the form of a straight probe 101 for detection to more intuitively show the relationship between each position to be detected and the transmitted wave and the echo. However, it does not represent a limitation on the type, quantity, and setting position of the probe 101. For example, it is also feasible to use a single array probe 101 to detect the completion degree of the cavity heat insulation area 5. The setting position of the corresponding probe 101 is analyzed by those skilled in the art according to the type of the selected probe 101.

[0120] The preset etching time is jointly analyzed by those skilled in the art considering factors such as the etching characteristics of the lower etch stop layer 223, the distribution of the first support anti-etching part 51 and the second support anti-etching part 52, and the width of the lower etch stop layer 223 on both sides of the heat insulation groove 3. Its setting basis is that after etching for the preset etching time, the lower etch stop layer 223 directly below the ridge waveguide located in the first support anti-etching part 51 and the second support anti-etching part 52 is etched through, and there is still a remaining structure in the lower etch stop layer 223 on both sides of the heat insulation groove 3, and the width of the remaining structure is greater than or equal to the preset length.

[0121] The preset length is determined by comprehensively considering the width of the spine, the thickness of each functional layer 2, the width of the heat insulation groove 3, and the distribution characteristics of the support structure 4. The preset time difference is analyzed by those skilled in the art according to experience.

[0122] In the embodiments of the present invention, the first, second, etc. are limiting descriptions, which do not refer to a specific order meaning. They are only used to distinguish the corresponding limited objects from the same category, and are added for the convenience of describing two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0123] In the embodiments of the present invention, the expression like "A and / or B" actually means that in the implementation manner, it can be implemented in the manner taking A as the object, or in the manner taking B as the object, or in the object manner of the combination of A and B. And A and B therein can also be replaced with specific subject name objects according to the requirements of the specific description scenario.

[0124] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A thermal tuning laser chip with a novel structure, characterized in that, It includes a substrate (1) and a plurality of functional layers (2) sequentially grown on the substrate (1); A plurality of heat insulation grooves (3) are respectively etched in the channels on both sides of the ridge waveguide; wherein, the plurality of heat insulation grooves (3) are spaced from each other, and the heat insulation groove (3) includes a first heat insulation part (31) leading to the first functional layer (211) and a second heat insulation part (32) leading to the second functional layer (212); A support structure (4) is grown on the inner wall of the heat insulation groove (3), and the support structure (4) includes a first support part (41) and a second support part (42). The first support part (41) completely covers the first heat insulation part (31), and the second support part (42) covers the third functional layer (213) of the second heat insulation part (32); wherein, the third functional layer (213) is located above the second functional layer (212), and the second functional layer (212) is located above the first functional layer (211); A hollow heat insulation area (5) penetrating through a plurality of heat insulation grooves (3) is hollowed out between the third functional layer (213) and the first functional layer (211); wherein, the hollow heat insulation area (5) is formed by pouring a corrosive liquid into the second heat insulation part (32) and performing lateral corrosion by the corrosive liquid.

2. The thermally tunable laser chip with the novel structure according to claim 1, wherein There are three functional layers (2) spaced between the third functional layer (213) and the first functional layer (211), which are the second functional layer (212), the fourth functional layer (214), and the fifth functional layer (215) in sequence from the direction of the substrate (1) upward; Taking the second heat insulation part (32) as a longitudinal channel, pouring a first corrosive liquid into the longitudinal channel to corrode away the fourth functional layer (214) to form a lateral channel (6), and pouring a second corrosive liquid into the longitudinal channel and the lateral channel (6) to corrode away the second functional layer (212) and the fifth functional layer (215) to form a complete hollow heat insulation area (5).

3. The thermally tunable laser chip with the novel structure according to claim 1, characterized in that, The support structure (4) includes an inner layer and an outer layer. The inner layer is a metal layer, and the outer layer is an oxide film; wherein, the inner layer is the layer close to the heat insulation groove (3).

4. The thermally tunable laser chip with the novel structure according to claim 1, characterized in that, The plurality of functional layers (2) sequentially grown on the substrate (1) include at least one of a lower cladding layer (221), a lower sacrificial layer (222), a lower etch stop layer (223), a middle sacrificial layer (224), an upper etch stop layer (225), an upper sacrificial layer (226), an active layer (227), and a contact layer (228).

5. A manufacturing method for a thermally tunable laser chip with a novel structure, characterized in that, A plurality of functional layers (2) are sequentially grown on the substrate (1) in advance, and the method includes: Etching a ridge waveguide on the plurality of functional layers (2), wherein the channel of the ridge waveguide is etched to the active layer (227); The positions of the first thermal insulation part (31) and the second thermal insulation part (32) are drawn by photolithography. The position of the first thermal insulation part (31) is etched and / or wet-etched to a first depth, and the position of the second thermal insulation part (32) is etched and / or wet-etched to a second depth, obtaining a plurality of thermally insulating grooves (3) spaced from each other. A first support part (41) is grown on the first thermal insulation part (31), and a second support part (42) covering the upper sacrificial layer (226) is grown on the second thermal insulation part (32); wherein, the first depth is the depth at which the channel of the ridge waveguide reaches the lower cladding (221), and the second depth is the depth at which the channel of the ridge waveguide reaches the middle sacrificial layer (224); Transverse etching is performed from the second thermal insulation part (32) to obtain a hollow thermal insulation region (5) penetrating through a plurality of thermally insulating grooves (3).

6. The manufacturing method of the thermally tunable laser chip with the novel structure according to claim 5, characterized in that, The steps of drawing the positions of the first thermal insulation part (31) and the second thermal insulation part (32) by photolithography, etching and / or wet-etching the position of the first thermal insulation part (31) to a first depth, etching and / or wet-etching the position of the second thermal insulation part (32) to a second depth, obtaining a plurality of thermally insulating grooves (3) spaced from each other, growing a first support part (41) on the first thermal insulation part (31), and growing a second support part (42) covering the upper sacrificial layer (226) on the second thermal insulation part (32) specifically include: The position of the first thermal insulation part (31) is drawn by photolithography in the channel of the ridge waveguide, and the position of the first thermal insulation part (31) is etched until reaching the upper sacrificial layer (226). The upper sacrificial layer (226) of the InP material is etched using a hydrochloric acid-based solution until reaching the upper etch stop layer (225), and then further photolithography and / or wet-etching is performed until conducting to the lower cladding (211) to form the first thermal insulation part (31), and a first support part (41) is grown on the first thermal insulation part (31); After the growth of the first support part (41) is completed, the position of the second thermal insulation part (32) is drawn by photolithography in the channel of the ridge waveguide, and photolithography and / or wet-etching is performed until conducting to the middle sacrificial layer (224) to form the second thermal insulation part (32), and a second support part (42) is grown in the second thermal insulation part (32); wherein, before the growth of the second support part (42), the second thermal insulation part (32) is separated from the first thermal insulation part (31) by the first support part (41).

7. The manufacturing method of the thermally tunable laser chip with the novel structure according to claim 5, characterized in that, The step of performing transverse etching from the second thermal insulation part (32) to obtain a hollow thermal insulation region (5) penetrating through a plurality of thermally insulating grooves (3) specifically includes: Using the second thermal insulation part (32) as a longitudinal channel, pouring a sulfuric acid-based solution into the longitudinal channel and performing etching for a first preset time to etch away the lower etch stop layer (223) to form a transverse channel (6); Pouring a hydrochloric acid-based solution into the longitudinal channel and the transverse channel (6) and performing etching for a second preset time to etch away the remaining middle sacrificial layer (224) and the lower sacrificial layer (222) to form a complete hollow thermal insulation region (5).

8. The manufacturing method of the thermally tunable laser chip with the novel structure according to claim 5, characterized in that, Etching ridge waveguides on the multiple functional layers (2) specifically includes: Defining corresponding ridge waveguide patterns on the surface of the functional layer (2) grown on the substrate (1) in sequence through photolithography, and etching on the semiconductor chip based on the defined ridge waveguide patterns, with the etching depth exceeding the contact layer (228); Selecting an acidic etching solution to etch the contact layer (228) to form channels on both the left and right sides of the waveguide of the semiconductor chip.

9. The manufacturing method of the thermally tunable laser chip with the novel structure according to claim 5, characterized in that, Fabricating laser chips on the laser wafer (9), and the method further includes: A plurality of laser chips are provided on the laser wafer (9), and an ultrasonic detector (10) is provided at the contact position between the laser wafer (9) and the laser chips. The ultrasonic detector (10) includes a probe (101) and a processor (102). The probe (101) of the ultrasonic detector (10) is in seamless contact with the substrate (1) of the laser chip to detect the completion degree of the cavity heat insulation area (5) in the laser chip; wherein, the ultrasonic detector (10) is provided at the position where the second heat insulation part (32) is located and / or at the interval position between the plurality of heat insulation grooves (3); When the cavity heat insulation area (5) of the corresponding laser chip is completely formed according to the detection of the ultrasonic detector (10), the fabrication of the laser chip is completed and qualified.

10. The method for fabricating a thermally tunable laser chip with a novel structure according to claim 9, characterized in that, The method for detecting the completion degree of the cavity heat insulation area (5) in the laser chip specifically includes: Sending an emission wave in the direction of the substrate (1) through the probe (101). When the emission wave enters the etching solution from the substrate (1), a primary reflection occurs and the probe (101) receives a first echo. When the emission wave enters the corresponding upper functional layer (2) from the etching solution, a secondary reflection occurs and the probe (101) receives a second echo; Determining the completion degree of the cavity heat insulation area (5) according to the time difference between the first echo and the second echo received by the probe (101).

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