Capacitance measurement device and method for capacitor array in chip

Abstract

The present invention relates to a capacitance measurement device and method for a capacitor array in a chip. By optimizing the design of a traditional capacitance measurement circuit and adopting a differential capacitance measurement technology based on the mutual capacitance of vertical and horizontal lines, the tolerance between each two mutual capacitances is processed and analyzed to improve the ability to capture tiny capacitance changes. By applying excitations of opposite phases to adjacent transmitting electrodes, the capacitance difference is extracted using the current cancellation principle, effectively eliminating the influence of circuit device process deviations and ambient temperature drift. A differential capacitance measurement module is used to convert nA-level composite current signals into voltages, and high-pass and low-pass filtering are combined to eliminate DC offsets and ensure signal stability under high gain. A frequency domain signal processing module is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, minimize the noise impact, and generate a high-entropy key. The measurement results are highly robust and accurate, and have strong anti-interference capabilities.

Description

Technical Field

[0001] The present invention belongs to the technical field of measuring physical unclonable functions in chips, and relates to a capacitance measurement device and method for a capacitance array in a chip. Background Art

[0002] Strong-SC-PUF-based secure measurement technology is a secure and reliable strong PUF (physically unclonable) circuit based on switched capacitors (SCs). It uses stimuli to select and configure two identical capacitors in N levels. It then uses LSSA (least squares spectrum analysis) to sample the circuit's total capacitance deviation and convert it into a digital response. This provides a large number of challenge-response pairs (CRPs) with excellent uniqueness and bias. Furthermore, it employs a built-in self-test (BIST) reliability enhancement strategy to automatically test and select PUF outputs with large capacitance deviations. The selected outputs achieve very high reliability and eliminate the need for expensive error correction mechanisms. However, the use of a BIST strategy increases circuit design complexity and overall testing time, and its robustness against non-invasive attacks such as electromagnetic interference needs improvement. Summary of the Invention

[0003] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a capacitance measurement device for a capacitor array in a chip and a capacitance measurement method for a capacitor array in a chip, which can maintain high robustness and accuracy of the measurement results and improve anti-interference ability.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] In one aspect, a capacitance measurement device for a capacitor array in a chip is provided, comprising a microcontroller, a capacitor array of a chip to be measured, a differential capacitance measurement module, and a frequency domain signal processing module; the capacitor array comprises a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrodes and the receiving electrodes corresponds to a capacitor;

[0006] The differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to each two adjacent transmitting electrodes of the capacitor array. The composite current signal generated on the receiving electrode common to each two adjacent transmitting electrodes on the capacitor array is obtained and converted into a measurement signal in the form of a voltage. The frequency domain signal processing module samples the measurement signal ADC and performs a fast Fourier transform. The tolerance of each two capacitors in the capacitor array is extracted from the measurement signal as the characteristic parameter of the capacitor array. The microcontroller is used to control the generation of the excitation signal of the differential capacitance measurement module and to generate the PUF identifier of the chip to which the capacitor array belongs based on the characteristic parameters.

[0007] In one embodiment, the differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field-effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter;

[0008] The dual-channel DAC circuit is connected to each transmitting electrode of the capacitor array through a first low-pass filter and a fully differential amplifier in sequence. The input end of the junction field effect transistor transimpedance amplifier is connected to each receiving electrode of the capacitor array in sequence. The output end of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module through a high-pass filter, an AC amplifier and a second low-pass filter in sequence. The dual-channel DAC circuit is used to generate synchronous excitation signals with matched amplitudes and opposite phases.

[0009] In one embodiment, the frequency domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a dual-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to the differential capacitance measurement module for sampling the measurement signal ADC. The discrete Fourier transform circuit and the dual-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller uses the amplitude and phase information to calculate the tolerance.

[0010] In one embodiment, the capacitance measuring device of the capacitor array in the above-mentioned chip further includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module, the input end of the transmitting electrode integrity detection module is respectively connected to each transmitting electrode of the capacitor array, the output end of the transmitting electrode integrity detection module is connected to a microcontroller, the input end of the receiving electrode integrity detection module is respectively connected to each receiving electrode of the capacitor array, the output end of the receiving electrode integrity detection module is connected to the microcontroller, the transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrode of the capacitor array, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrode of the capacitor array.

[0011] On the other hand, a method for measuring capacitance of a capacitor array in a chip is provided, comprising the steps of:

[0012] On the printed circuit board where the chip to be tested is located, a capacitor array is constructed by orthogonal wiring on the top and bottom layers;

[0013] A differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to each two adjacent transmitting electrodes of the capacitor array, obtains the composite current signal generated on the receiving electrode common to each two adjacent transmitting electrodes, and converts it into a measurement signal in the form of a voltage;

[0014] The frequency domain signal processing module samples the measurement signal ADC and performs a fast Fourier transform. The tolerance between every two capacitors in the capacitor array is extracted from the measurement signal as the characteristic parameter of the capacitor array. The characteristic parameter is used to generate the PUF identifier of the chip to which the capacitor array belongs.

[0015] One of the above technical solutions has the following advantages and beneficial effects:

[0016] The capacitance measurement device and method for the capacitor array in the above-mentioned chip optimizes the design of the traditional capacitance measurement circuit, adopts differential capacitance measurement technology based on vertical and horizontal line mutual capacitance, and processes and analyzes the tolerance between each two mutual capacitances to improve the ability to capture tiny capacitance changes. By applying excitations of opposite phases to adjacent transmitting electrodes, the capacitance difference is extracted using the current cancellation principle, effectively eliminating the influence of circuit device process deviations and ambient temperature drift. The differential capacitance measurement module is used to convert the nA-level composite current signal into voltage, and high-pass and low-pass filtering are combined to eliminate DC offset to ensure signal stability under high gain. The frequency domain signal processing module is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, minimize the noise impact, and generate a high-entropy key. The measurement results are highly robust and accurate, and have strong anti-interference capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 Schematic diagram of the module architecture of a capacitance measurement device for a capacitor array in a chip according to one embodiment;

[0019] Figure 2 A schematic diagram of a 16×16 capacitor network arrangement in one embodiment;

[0020] Figure 3 is a schematic diagram of a simplified 2×2 capacitor model in one embodiment;

[0021] Figure 4 Schematic diagram of a differential capacitance measurement system in one embodiment;

[0022] Figure 5 A block diagram of the XC7Z020 peripheral circuit in one embodiment;

[0023] Figure 6 A schematic diagram of excitation signal generation and preprocessing in one embodiment;

[0024] Figure 7 1 is a schematic diagram of a fully differential amplifier circuit in one embodiment;

[0025] Figure 8 In one embodiment, RX Schematic diagram of current-to-voltage processing;

[0026] Figure 9 A schematic diagram of a JFET-TIA circuit implementation in one embodiment;

[0027] Figure 10 A schematic diagram of voltage signal filtering and amplification in one embodiment;

[0028] Figure 11 A schematic diagram of a mV-level signal amplification circuit in one embodiment;

[0029] Figure 12 A simplified block diagram of a (SAR) ADC circuit in one embodiment is shown;

[0030] Figure 13 A schematic diagram of a full link of a measurement circuit in one embodiment;

[0031] Figure 14 In one embodiment, RX Simplified diagram of current-to-voltage processing;

[0032] Figure 15 Schematic diagram of the overall circuit architecture of a capacitance measurement device for a capacitor array in a chip according to one embodiment;

[0033] Figure 16 FIG. 4 is a flow chart of a capacitance measurement method of a capacitor array in a chip according to an embodiment. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0035] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0036] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0037] Although current PUF measurement technology continues to develop in terms of stability and accuracy, it still faces many challenges. The following analyzes the defects of the existing technology from a technical perspective and explains how the present invention will solve these problems in a causal reasoning manner. (1) Environmental sensitivity leads to insufficient stability. The reason is that it relies on physical parameters such as delay time, power consumption, and current waveform (such as SRAM PUF, oscillator PUF, thermal noise PUF, etc.) for measurement, which is greatly affected by temperature, voltage fluctuations and electromagnetic interference. The consequence is poor characteristic value stability, and a dynamic compensation algorithm (such as real-time temperature-voltage feedback) is required to maintain response consistency. Defect summary: poor environmental sensitivity, insufficient CRP stability, and the need for additional compensation mechanisms.

[0038] (2) Limited measurement accuracy. This is because traditional measurement circuit design methods are limited by chip performance and environmental noise, making it difficult to achieve fast, high-precision measurement of capacitance in the fF (femtofarad) range. Consequently, the parallel detection requirements for tiny capacitors cannot be met. Summary of Defects: Limited measurement accuracy limits the application of PUF in high-security chips. (3) Reliance on error correction mechanisms. This is because insufficient measurement accuracy necessitates the reliance on expensive error correction mechanisms (such as error correction code (ECC)). This increases system complexity and resource overhead, impacting performance. Summary of Defects: Error correction is costly and unsuitable for resource-constrained scenarios (such as IoT devices).

[0039] Based on the existing technology, the present invention combines intelligent detection and PUF optimization to propose a new high-precision measurement solution: a multi-layer electrode network (including transmitting electrodes TX and receiving electrodes RX) is constructed on the PCB where the chip is located. Tiny capacitance is formed between the electrodes, and the mutual capacitance of each electrode pair has subtle and non-replicable differences, which are unique and unpredictable. A differential capacitance measurement method is adopted, that is, adjacent TX electrodes are applied with excitation signals of opposite phases, generating reverse currents on the RX electrodes, effectively eliminating the influence of circuit device process deviations and ambient temperature drift. A digital dual-phase lock-in amplifier is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, implement digital signal processing, and minimize the impact of noise to generate a high-entropy key. Some professional terms are explained as follows:

[0040] PUF: Short for Physical Unclonable Functions, the most commonly used hardware security primitive (basic component). Similar to a human fingerprint, it extracts information such as material or chip processing deviations to form information unique to a single entity. It is used in cryptographic applications such as root key protection and authentication.

[0041] Nano Composite Film: A multi-layer composite packaging structure consisting of a high-dielectric material, a conductive shielding layer, and an intelligent sensing layer. It is mainly used to improve the physical security of the chip and prevent reverse engineering attacks.

[0042] High-K Dielectric Material: A material with a high dielectric constant that can be used to form a packaging structure that is resistant to FIB analysis and has high capacitance density, thereby improving chip protection capabilities.

[0043] Random dielectric composite film: refers to a composite film formed by randomly embedding one or more particles with different dielectric properties in a substrate. The microstructure of the heterogeneous particles, such as shape, size, volume fraction, orientation and distribution, will affect the dielectric properties of the composite film, presenting typical dielectric texture characteristics such as resistance and capacitance.

[0044] Challenge-Response Pair (CRP): The information input to the PUF (e.g., a capacitor array) is called a challenge, and the information output from the PUF is called a response. Together, they are called a challenge-response pair.

[0045] Built-in Self-Test (BIST): A technology that integrates functional circuitry into circuits during design to provide self-test capabilities, thereby reducing device testing's reliance on automatic test equipment. BIST is a Design for Testability (DFT) technique that can be applied to nearly any circuit, making it widely used in the semiconductor industry.

[0046] Trans-impedance amplifier (TIA): A circuit that converts a weak current signal into a voltage signal. It has a negative feedback resistor and can be simply regarded as an inverting amplifier.

[0047] Dual-phase lock-in amplifier: designed to solve the problem of phase difference affecting measurement accuracy of the lock-in amplifier, it facilitates accurate extraction of the phase of the input signal. Its basic structure consists of two parallel lock-in amplifiers. After filtering, it can obtain output signals and phase difference values that are not affected by phase difference.

[0048] In one embodiment, Figure 1 As shown, a capacitance measurement device for a capacitor array in a chip is provided, comprising a microcontroller 11, a capacitor array 12 of a chip to be tested, a differential capacitance measurement module 13, and a frequency domain signal processing module 14. The capacitor array 12 comprises a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrode and the receiving electrode corresponds to a capacitor. The differential capacitance measurement module 13 inputs synchronous amplitude-matched and phase-opposite excitation signals to each two adjacent transmitting electrodes of the capacitor array 12, obtains the composite current signal generated on the receiving electrode common to each two adjacent transmitting electrodes on the capacitor array 12, and converts it into a measurement signal in the form of a voltage. The frequency domain signal processing module 14 samples the measurement signal ADC and performs a fast Fourier transform, extracting the tolerance of each two capacitors of the capacitor array 12 from the measurement signal as a characteristic parameter of the capacitor array 12. The microcontroller 11 is used to control the generation of the excitation signal of the differential capacitance measurement module 13, and to generate a PUF identifier of the chip to which the capacitor array 12 belongs based on the characteristic parameters.

[0049] It can be understood that a 16×16 capacitor network (16 TX electrodes and 16 RX electrodes) is constructed on the printed circuit board through orthogonal wiring of the TOP (top layer of the printed circuit board, that is, the component surface) and BOTTOM (bottom layer of the printed circuit board, opposite to the TOP layer). The simplified diagram of the network is as follows: Figure 2 shown.

[0050] To facilitate the description of the test board measurement object, a simplified 2×2 capacitor network model is used as an example. Figure 3 The figure shows a simplified 2×2 capacitor network model consisting of two orthogonal TX electrodes and RX electrodes. The 2×2 capacitor network model has the following three parameters related to capacitance:

[0051] (1) Mutual capacitance C m According to the principle of parallel plate capacitance, there is a capacitance at the intersection of each orthogonal TX electrode and RX electrode, which is called mutual capacitance (denoted as C m). For easy distinction, the capacitance between the TX1 electrode and the RX1 electrode can be marked as C 1,1 , and so on, in the simplified 2×2 capacitor network model there is C 1,1 、C 2,1 、C 1,2 and C 2,2 Four mutual capacitances. TX 1R and RX 1R The subscript R indicates redundancy or multiplexing.

[0052] (2) Tolerance △C between mutual capacitances. Due to the unpredictability and uncontrollability of the manufacturing process, there will be differences between each two capacitors. By obtaining these capacitance differences, we can use them as characteristic parameters of the chip. However, due to the very small capacitance value and the influence of various noises, the measurement of a single capacitor is more difficult for subsequent processing. This embodiment adopts the differential capacitance measurement method, and defines the capacitance difference caused by the difference between each two mutual capacitances as the tolerance △C. For an n×n capacitor network, there will be n 2 △C information is extracted through the measurement system 2 The information of △C can be used as the characteristic parameter of the chip.

[0053] (3) Equivalent capacitance Cs. Each electrode has an equivalent capacitance (represented by Cs) to the ground shield.

[0054] In summary, the 16×16 capacitor network provides a total of 128 tolerance △C. The measurement target of the package inspection board is to measure △C, and the resolution design index is 1fF. The detection principle is as follows: Figure 4 As shown, since the measurement circuit is inherently insensitive to parasitic resistance and capacitance, this embodiment implements ΔC measurement through two excitation signals with matched amplitudes and a 180° phase difference. This can resolve capacitance changes in the order of fF, and then combines with the corresponding digital signal processing chain to achieve accurate PUF digitization.

[0055] The capacitance measurement device of the capacitor array in the above-mentioned chip optimizes the design of the traditional capacitance measurement circuit and adopts the differential capacitance measurement technology based on the mutual capacitance of vertical and horizontal lines to process and analyze the tolerance between each two mutual capacitances to improve the ability to capture tiny capacitance changes. By applying excitations of opposite phases to adjacent transmitting electrodes and extracting the capacitance difference using the current cancellation principle, the influence of circuit device process deviation and ambient temperature drift is effectively eliminated. The differential capacitance measurement module 13 is used to convert the nA-level composite current signal into voltage, and high-pass and low-pass filtering are combined to eliminate DC offset to ensure signal stability under high gain. The frequency domain signal processing module 14 is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, and minimize the noise impact to generate a high-entropy key. The measurement result is highly robust and accurate, and has strong anti-interference ability.

[0056] It should be noted that the microcontroller 11 needs to have certain algorithm processing capabilities in addition to the control capabilities. The existing embedded SOC device XC7Z020 can be selected as the required microcontroller 11. Figure 5 As shown, its peripheral circuits mainly include power supply circuit, clock circuit, reset circuit, loading unit, external storage unit, UART interface, status indication and temperature monitoring unit, etc. According to the above control and processing requirements, adaptive configuration can be performed to obtain the microcontroller 11 with the required functions.

[0057] In one embodiment, the differential capacitance measurement module 13 includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter. The dual-channel DAC circuit is connected to each transmitting electrode of the capacitor array 12 in sequence through the first low-pass filter and the fully differential amplifier. The input end of the junction field effect transistor transimpedance amplifier is connected to each receiving electrode of the capacitor array 12, and the output end of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module 14 in sequence through the high-pass filter, the AC amplifier, and the second low-pass filter. The dual-channel DAC circuit is used to generate synchronous excitation signals with matching amplitudes and opposite phases.

[0058] It can be understood that in the differential capacitance measurement module 13, a two-order low-pass filter is used to remove the high-frequency components in the output of the dual-channel DAC circuit, and then a fully differential amplifier is used to provide sufficient amplitude matching for the DAC output signal. The two signals output by the fully differential amplifier are respectively added to the fixed electrodes TX1 and TX2 on the capacitor array that constitute the differential detection capacitor, and then a composite current I is generated on the common electrode RX1 of TX1 and TX2. RX , using the JEFT-TIA circuit (i.e., junction field effect transistor transimpedance amplifier) to automatically achieve current to voltage measurement, the composite current I RX After being converted into a voltage output signal, it is filtered and amplified by a high-pass filter and an AC amplifier, and then pre-processed and transmitted to the frequency domain signal processing module 14. The frequency domain signal processing module 14 realizes the conversion of analog signals to digital signals. For the extracted digital signal, the discrete Fourier transform and the dual-phase lock-in amplifier can be used to extract the amplitude and phase information from the signal, so as to analyze the characteristic information △C of the 16×16 network according to the existing tolerance calculation algorithm.

[0059] Dual-channel excitation signal generation and preprocessing: Figure 6As shown in Figure 1, dual-channel synchronous excitation signals can be implemented using a dual-channel DAC circuit (such as a 24-bit DAC device). This circuit is a 32-bit, 384kHz audio stereo DAC with a PLL. This DAC device can control out-of-band noise to a low level of 20dB, thereby reducing EMI and aliasing in downstream amplifiers / ADCs. The DAC device generates two synchronous excitation signals with matched amplitudes and opposite phases (amplitude imbalance or phase error will cause offsets in the extracted PUF data). The high-frequency components in the DAC output are then removed through a two-order low-pass filter.

[0060] The signal output by the low-pass filter cannot provide sufficient amplitude matching, so it is necessary to amplify the excitation signal through a fully differential amplifier. The circuit diagram is as follows Figure 7 As shown. The required signal amplitude is obtained by setting the values of resistors RG and RF. Resistors RG and RF need to be high-precision and low-temperature drift resistors. Although a fully differential amplifier can provide sufficient amplitude matching, the imbalance at the differential output will affect the measurement. According to experience, the imbalance of the TX signal is at least greater than △C / C m 1 ≈1 / 1000=-60dB is one order of magnitude smaller. Here we can choose the fully differential amplifier THS4551 to achieve this. The output balance parameter of this fully differential amplifier is 85dB@VOUT=±1V, ensuring sufficient signal quality for subsequent measurements. m 1 is the capacitance of a single mutual capacitor, VP and VN are differential input signals, VOCM is the common-mode voltage input, and VOUT+ and VOUT- are differential output signals.

[0061] nA (nanoampere) current-to-voltage conversion: The two signals output by the fully differential amplifier are added to the fixed electrodes TX1 and TX2 corresponding to the differential detection capacitors, and then a composite current I is generated on the common electrode RX1 of TX1 and TX2. RX , composite current I RX The amplitude is in the order of nA to sub-nA. This embodiment uses a JEFT-TIA (junction field effect transistor transimpedance amplifier) circuit to achieve current-to-voltage measurement. The circuit diagram is shown in FIG. Figure 8 shown.

[0062] A composite current I is generated on the common electrode RX RX The amplitude is nA level, to achieve I RX Measurement requires a high-gain, low-noise amplifier. The amplifier must meet the following three requirements: First, low bias current. Excessive input bias current will divide the weak measured current I RXThis can cause measurement inaccuracies. Therefore, the op amp's bias current should be less than or equal to picoamperes (pA). Secondly, low current noise and voltage noise are essential. Since the input signal is current, the op amp also needs to have low current noise and voltage noise. Thirdly, a high gain-bandwidth product is essential. High capacitive loading on the RX node reduces the amplifier's bandwidth.

[0063] Here, a JFET-TIA circuit is used for specific circuit implementation. The entire functional unit consists of a high gain-bandwidth product operational amplifier (IC1), a low input bias JFET (T1) and other peripheral circuit components (resistors and capacitors). The circuit implementation block diagram is shown in the figure below. Figure 9 As shown in the figure: Resistors R2 and R3 are used to set the DC operating point of the circuit. Feedback capacitor C1 uses an NPO type zero-drift capacitor. Resistor R1 is used to adjust the amplification gain so that the TIA has a gain amplitude of 0.0106V / A when the excitation frequency is ≤48KHz.

[0064] Currents less than a few nA are amplified and converted into voltages through the JFET-TIA circuit, providing high gain with extremely low noise. Figure 9 The circuit diagram derives the relationship between the output voltage and the input current, and the conduction current of the junction field effect transistor when it works in the amplification area i D Calculation formula: i D =I DSS ×(V GS / V P ) 2 , calculate that the output voltage satisfies V under any circumstances OUT =1.522+ i D ×R1, where I DSS is the saturation drain current, V GS is the gate-source voltage, V P is the pinch-off voltage, and R1 is the resistance of resistor R1.

[0065] Voltage signal filtering and amplification: composite current I RX After being converted into a voltage output signal, it needs to pass through a first-order active high-pass filter to remove the DC component in the signal. Then, the signal is fed into a high-gain amplifier circuit (using an AC amplifier with a first-stage follower followed by a two-stage amplification) to further amplify the signal to the dynamic range of the ADC in the frequency domain signal processing module 14. At the same time, in order to prevent aliasing during the digitization process, the AC amplifier needs to be implemented as an active first-order low-pass filter, such as Figure 10 shown.

[0066] The interference of the first stage amplification in the AC amplifier plays a major role in the interference of the entire AC amplifier. This is because as long as the first stage introduces a little weak interference voltage, the subsequent stage amplification will output a larger interference voltage. Therefore, the first stage amplification process is particularly important. This embodiment selects the high-precision operational amplifier OPA189 as the AC amplifier. This high-precision operational amplifier is an ultra-low noise, fast stabilization and zero drift device that provides rail-to-rail output. These features and excellent AC performance, plus the single-channel version's offset voltage of only 0.4µV and temperature drift of 0.005µV / ℃, make the OPA189 an ideal choice for precision instruments, signal measurement and active filtering applications. The circuit structure of the mV-level signal AC amplifier is as follows: Figure 11 As shown, its specific circuit structure can be understood by referring to the existing circuit description, and will not be elaborated in this manual.

[0067] In one embodiment, frequency-domain signal processing module 14 includes a sequentially connected successive approximation register (ADC) chip, a discrete Fourier transform (DFT) circuit, and a dual-phase lock-in amplifier. The input of the SAR ADC chip is connected to differential capacitance measurement module 13 for ADC sampling of the measurement signal. The DFT circuit and the dual-phase lock-in amplifier extract amplitude and phase information from the sampled measurement signal via a fast Fourier transform (FFT). Microcontroller 11 uses this amplitude and phase information to calculate the tolerance.

[0068] It can be understood that due to the low output impedance characteristics of the low-pass filter, the signal after sampling and pre-processing can be connected to the successive approximation register ADC chip, and the analog signal is converted to a digital signal through ADC conversion processing. ADC sampling needs to be synchronized with the DAC output, and the signal is oversampled to reduce noise. Considering the trade-offs between front-end noise, bandwidth, setup time, signal-to-noise ratio, slew rate, spurious-free dynamic range (SFDR), input impedance, and sampling time, the successive approximation register ADC chip can use a low-noise and low-power high-speed 24-bit successive approximation register (SAR) ADC. Its simplified circuit block diagram is shown below. Figure 12 As shown in the figure, the 24-BIT SAMPLING ADC is the 24-bit sampling ADC core, responsible for converting the input analog signal into a 24-bit digital quantity; the DIGITAL FILTER is a digital filter used to filter the original digital signal output by the ADC; the CONTROL LOGIC is a control logic unit used to manage the ADC's working timing (such as sampling start and conversion cycle), configuration parameters (such as gain and sampling rate), and coordinate the interaction between the module's internal and external interfaces. IN+ / IN- are analog input interfaces, V DDIt is a digital power supply, REF is the reference voltage, CHAIN is the daisy chain / cascade enable interface, CNV is the conversion start interface, BUSY is the busy signal interface, SDO is the SPI data output interface, RDL / SDI is the SPI data input interface, SCK is the SPI clock interface, It is the reference signal interface of the control logic unit.

[0069] For the extracted digital signal, a discrete Fourier transform circuit and a dual-phase lock-in amplifier are used to extract the amplitude and phase information from the input signal, and the characteristic information of the 16×16 network is analyzed based on the existing tolerance calculation algorithm.

[0070] In some embodiments, according to the parallel high-speed and high-precision measurement design of the capacitor array, the full link block diagram is as follows: Figure 13 As shown. Figure 13 It can be seen that after FFT, the amplitude of the excitation signal frequency spectrum line satisfies: (N+K)×6-|S|dB=20log(V AD )-[20log(Vp~p)-T0+T1+A], the range of the analog-to-digital converter AD is V AD The excitation signal Vp~p is unified with the sine signal amplitude, and we can get:

[0071] T0=(N+K)×6-|S|dB-20log(V AD / Vp~p)+T1+A

[0072] Among them, A is the driving gain of the analog-to-digital converter (AD), the capacitor array attenuation value T0 represents the characteristics of the capacitor array (the actual capacitance value is proportional to T0), and the T0 accuracy (also the capacitance limit measurement accuracy) is mainly determined by the FFT analysis bandwidth and the current noise of the current-to-voltage conversion (JFET and op amp). N is the resolution of the analog-to-digital converter (AD), K is the spectrum data bit width after the FFT operation, T1 is the current-to-voltage gain, and S is the excitation signal frequency spectrum, representing the amplitude / phase distribution of the communication signal in the frequency domain. The circuit limit signal-to-noise ratio (SNR) is:

[0073] SNR = 20log(I-in / I-Noise)

[0074] Among them, I-in is the output signal current of the capacitor array; I-Noise is the equivalent current noise at the input of the current-to-voltage converter. Its value is the current noise within the bandwidth of a single FFT spectrum line, which is a combination of the JFET current noise, the current noise caused by the feedback loop resistance, and the current noise at the input of the op amp. From the above expression, it can be seen that the key to achieving high-precision measurement is to control the current noise in the current-to-voltage process and maximize the DA output voltage amplitude. The circuit principles of the three parts, namely the excitation circuit, the capacitor array, and the current-to-voltage converter, are as follows: Figure 14 shown.

[0075] Figure 14 Vin+ and Vin- are the output signals of the differential DAC, and C mn+ It is the sum of the coupling capacitance between the mth TX+ signal line and the nth RX signal line of the film, C mn- is the sum of the coupling capacitance between the mth TX-signal line and the nth RX signal line of the film, C o is the sum of the RX signal parasitic capacitance and the input capacitance of the JFET tube. R0 is the input resistance of the JFET. Since the JFET input resistance is hundreds of MΩ, it can be ignored. Assume:

[0076] C mn =(C mn+ +C mn- ) / 2,δ=(C mn+ -C mn- ) / C mn , δ is approximately a real number.

[0077] V in =(V in+ +V in- ) / 2,Δ=(V in+ -V in- ) / V in , Δ is a complex number.

[0078] When the current-to-voltage loop is working stably, the output signal current of the capacitor array is:

[0079] I-in=j2πfVin C mn (Δ+δ)

[0080] Where f is the excitation signal frequency; δ is determined by the capacitance deviation (determined by the dielectric texture information of the composite film); and Δ is a relatively fixed deviation.

[0081] It should be noted that the extraction of random dielectric texture characteristics of composite films is the core of chip security packaging design and the data foundation required for designing highly reliable PUFs under wide temperature and voltage conditions. Therefore, achieving high-precision measurement of the random dielectric texture characteristics of composite films is crucial. This specification adopts the above-mentioned differential capacitance-based random dielectric texture characteristic measurement scheme. However, the capacitance values corresponding to the random dielectric texture characteristics of composite films are in the femtofarad (10 to 15F), and the subtle changes in capacitance values of hundreds of femtofarads need to be monitored simultaneously within the chip package size. To address this problem, this specification breaks through the design technology of random dielectric texture characteristic measurement capacitor arrays and the parallel fast and high-precision measurement technology of femtofarad-level capacitor arrays to identify subtle changes in the random dielectric texture characteristics of composite films, providing basic data support for the generation of reliable PUF root keys based on random dielectric characteristics.

[0082] In one embodiment, the capacitance measurement device for the capacitor array in the chip further includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module. The input end of the transmitting electrode integrity detection module is respectively connected to each transmitting electrode of the capacitor array 12, the output end of the transmitting electrode integrity detection module is connected to the microcontroller 11, the input end of the receiving electrode integrity detection module is respectively connected to each receiving electrode of the capacitor array 12, and the output end of the receiving electrode integrity detection module is connected to the microcontroller 11. The transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrodes of the capacitor array 12, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrodes of the capacitor array 12.

[0083] It is understandable that Figure 15 As shown, both the transmitting electrode integrity detection module and the receiving electrode integrity detection module can use a multiplexing unit (such as the multiplexer ADG706) to achieve the connection and selection of each corresponding electrode.

[0084] It is understandable that when applying chip packaging technology to realize the cross-capacitance characteristic analysis of flexible film: considering the advanced packaging technology level, reliability and safety protection requirements, the trace width is selected to be 10um and the insulation layer thickness is about 3um. Therefore, each cross-coupling capacitor is about 100um and the occupied area is about 400um. 2 , calculated based on a single pair (TX+, TX-) and RX forming 128 cross-coupling capacitors, totaling about 0.0512mm 2 According to the packaging materials and processes, the sum of the capacitance values of the 64 cross-coupling capacitors formed by TX+ or TX- is approximately 1 to 2 pf, with a process deviation of about 10%. Under the conditions of Vin = 1 V, f = 24 kHz, I-in is approximately 15 nA. According to the current device level, I-Noise is generally not less than 5 pA. When the FFT analysis measurement time is 10 ms, the SNR is 50 dB, which is about 8 bits of effective value. Assuming that one of the 128 cross-coupling capacitors is damaged, exactly 8 bits are required, which cannot meet the high-reliability measurement requirements. Therefore, it is necessary to further improve the circuit detection sensitivity or enhance the film feature information.

[0085] Then, methods for improving detection sensitivity are proposed: (a) Increasing the DA output signal amplitude. Depending on the device capabilities, an output of 2Vp-p can be achieved. (b) The current packaging insulation material is PI, with a dielectric constant of approximately 2 to 3. If a new high-dielectric thin film material is used, the dielectric constant can be increased to between 20 and 30. Combining these two measures, with other measurement conditions remaining unchanged, the SNR can be increased by approximately 26dB, or approximately 4 bits of effective value.

[0086] Then, an analysis of security application requirements is given: security application requirements include two aspects: one is whether the composite film can extract sufficient PUF effective information, and the other is the ultimate anti-intrusion detection capability, that is, the minimum detectable hole size when the composite film is intruded.

[0087] PUF effective information: According to the above analysis, 0.0512mm 2 The film with an area of 1mm can output 8 bits of effective information. 2 There are nearly 20 measurement data. The 8-bit effective information of each measurement result includes a fixed deviation, which cannot be used for PUF data. Only the capacitance difference between TX+ and TX1 relative to RX can be used to generate PUF information. Based on a 10% process deviation estimate, the 10% fluctuation corresponds to the lowest 2 to 3 bits of information in the 8-bit effective information. Therefore, 1mm 2 About 40 to 60 bits of information can be output for PUF information generation, which can achieve 4 bits / mm 2 The PUF information output provides stable information data.

[0088] For extreme intrusion detection capabilities, the integrity of the composite film can be tested through two methods: (a) testing the connectivity characteristics of the TX and RX lines; and (b) testing the offset between the TX+, TX-, and RX capacitors. In the above design, a single measurement result is the difference between the sum of the two groups of 64 capacitors. To achieve the ability to detect 10μm-level perforations (damaging only one capacitor), a single measurement result must have an effective measurement accuracy of at least 8 bits. Increasing the DA amplitude and improving the material dielectric constant can increase the effective bit rate of a single point by 4 bits. However, the probability of false alarms is still high, requiring the use of signal processing techniques such as sparse signal detection and increasing the analysis time window to reduce false alarms.

[0089] Through the above high-precision measurement analysis, it can be seen that the core of security packaging includes: (1) the dielectric properties of thin film insulating materials, which increase the capacitance value without changing the spatial dimensions; (2) advanced signal processing technology to reduce the false alarm rate of intrusion detection; (3) devices required for high-precision measurement circuits. At present, module-level packaging can use general-purpose devices to achieve high-precision measurement, but chip-level security packaging requires advanced packaging technology to package the die (bare chip) of the analog and integrated circuits required for measurement into chips in the form of chiplets.

[0090] In summary, by adding a composite dielectric film with random microscopic features to the surface of the chip die, Figure 15The high-precision differential capacitance measurement circuit extracts the random physical properties of the film. The specific implementation principle is as follows: the microcontroller 11 (i.e., the SOC uses XC7Z020) drives the dual-channel DAC to generate two synchronous amplitude-matched and phase-opposite excitation signals, and removes the high-frequency components in the DAC output through a two-order low-pass filter. Then, a fully differential amplifier is used to provide sufficient amplitude matching for the DAC output signal. The two signals output by the fully differential amplifier are respectively added to the fixed electrodes TX1 and TX2 corresponding to the differential detection capacitor, and then a composite current I is generated on the common electrode of TX1 and TX2. RX , using JFET-TIA circuit to achieve current to voltage measurement. Current I RX After being converted into a voltage output signal, it is filtered and amplified, and then transmitted to the ADC through a preprocessing circuit. The ADC realizes the conversion of analog signals into digital signals. For the extracted digital signal, the discrete Fourier transform circuit and the dual-phase lock-in amplifier are used to extract the amplitude and phase information from the RX signal. The SOC analyzes the characteristic information of the 16×16 capacitor network based on the existing tolerance calculation algorithm.

[0091] The capacitance measurement device in the capacitor array in the aforementioned chip optimizes traditional capacitance measurement circuits and employs a differential capacitance measurement technique based on vertical and horizontal line mutual capacitance. This technique processes and analyzes the tolerance between each mutual capacitance, improving the ability to capture minute capacitance changes. By applying excitation signals of opposite phase to adjacent TX electrodes and using current cancellation to extract the capacitance difference ΔC, the device effectively eliminates the effects of process variations and ambient temperature drift. A digital dual-phase lock-in amplifier (DLLA) extracts the amplitude and phase of the excitation, converting the analog signal into a digital signal to minimize noise and generate a high-entropy key. A JFET-TIA (transimpedance amplifier) converts the nanoamp RX current into a voltage. High-pass and low-pass filters are combined to eliminate DC offset and ensure signal stability at high gain. A multiplexing unit supports expansion to 16×16 electrode networks, balancing speed and area. The DLLA accelerates computations using the FPU, reducing the computation time per capacitor node by approximately 25%.

[0092] In one embodiment, Figure 16 As shown, a method for measuring capacitance of a capacitor array in a chip is provided, which may include the following steps:

[0093] S10, constructing a capacitor array on the printed circuit board where the chip to be tested is located by orthogonal wiring on the top layer and the bottom layer;

[0094] S12, inputting synchronous excitation signals with matching amplitudes and opposite phases to each two adjacent transmitting electrodes of the capacitor array through the differential capacitance measurement module, acquiring a composite current signal generated on a receiving electrode common to each two adjacent transmitting electrodes, and converting the composite current signal into a voltage measurement signal;

[0095] S14, after sampling the measurement signal ADC through the frequency domain signal processing module, a fast Fourier transform is performed, and the tolerance between every two capacitors in the capacitor array is extracted from the measurement signal as a characteristic parameter of the capacitor array; the characteristic parameter is used to generate a PUF identifier for the chip to which the capacitor array belongs.

[0096] The capacitance measurement method of the capacitor array in the above chip optimizes the design of the traditional capacitance measurement circuit and adopts differential capacitance measurement technology based on vertical and horizontal line mutual capacitance to process and analyze the tolerance between each two mutual capacitances to improve the ability to capture tiny capacitance changes. By applying excitations with opposite phases to adjacent transmitting electrodes and extracting capacitance differences using the principle of current cancellation, the influence of circuit device process deviations and ambient temperature drift is effectively eliminated. The differential capacitance measurement module is used to convert the nA-level composite current signal into voltage, and high-pass and low-pass filtering are combined to eliminate DC offset and ensure signal stability under high gain. The frequency domain signal processing module is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, and minimize the noise impact to generate a high-entropy key. The measurement results are highly robust and accurate, and have strong anti-interference capabilities.

[0097] In one embodiment, the differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field-effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter;

[0098] The dual-channel DAC circuit is connected to each transmitting electrode of the capacitor array through a first low-pass filter and a fully differential amplifier in sequence. The input end of the junction field effect transistor transimpedance amplifier is connected to each receiving electrode of the capacitor array in sequence. The output end of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module through a high-pass filter, an AC amplifier and a second low-pass filter in sequence. The dual-channel DAC circuit is used to generate synchronous excitation signals with matched amplitudes and opposite phases.

[0099] In one embodiment, the frequency domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a dual-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to a differential capacitance measurement module for sampling the measurement signal ADC. The discrete Fourier transform circuit and the dual-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller uses the amplitude and phase information to calculate the tolerance.

[0100] Regarding the specific limitations of the capacitance measurement method of the capacitor array in the chip, please refer to the corresponding limitations of the various embodiments of the capacitance measurement device of the capacitor array in the chip above, which will not be repeated here.

[0101] It should be understood that although the above process Figure 16 The steps in the flowchart are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Figure 16 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0102] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus DRAM (RDRAM), and DDR DRAM.

[0103] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention.

Claims

1. A capacitance measurement device for a capacitor array in a chip, characterized in that: The system includes a microcontroller, a capacitor array of a chip to be tested, a differential capacitance measurement module, and a frequency domain signal processing module; the capacitor array includes a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrode and the receiving electrode corresponds to a capacitor; The differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to each two adjacent transmitting electrodes of the capacitor array. The composite current signal generated on the receiving electrode shared by each two adjacent transmitting electrodes on the capacitor array is obtained and converted into a voltage measurement signal. The frequency domain signal processing module samples the measurement signal ADC and performs a fast Fourier transform. The tolerance of each two capacitors in the capacitor array is extracted from the measurement signal as a characteristic parameter of the capacitor array. The microcontroller is used to control the generation of the excitation signal of the differential capacitance measurement module and to generate the PUF identifier of the chip to which the capacitor array belongs based on the characteristic parameters. The differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is connected to each transmitting electrode of the capacitor array through a first low-pass filter and a fully differential amplifier in sequence. The input end of the junction field effect transistor transimpedance amplifier is connected to each receiving electrode of the capacitor array in sequence. The output end of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module through a high-pass filter, an AC amplifier and a second low-pass filter in sequence. The dual-channel DAC circuit is used to generate synchronous excitation signals with matched amplitudes and opposite phases.

2. The capacitance measuring device of the capacitor array in a chip according to claim 1, characterized in that: The frequency domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit and a dual-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to the differential capacitance measurement module for sampling the measurement signal ADC. The discrete Fourier transform circuit and the dual-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller uses the amplitude and phase information to calculate the tolerance.

3. The capacitance measuring device of the capacitor array in a chip according to claim 2, characterized in that: It also includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module. The input end of the transmitting electrode integrity detection module is respectively connected to each transmitting electrode of the capacitor array, and the output end of the transmitting electrode integrity detection module is connected to the microcontroller. The input end of the receiving electrode integrity detection module is respectively connected to each receiving electrode of the capacitor array, and the output end of the receiving electrode integrity detection module is connected to the microcontroller. The transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrode of the capacitor array, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrode of the capacitor array.

4. A method for measuring capacitance of a capacitor array in a chip, characterized in that: Including steps: On the printed circuit board where the chip to be tested is located, a capacitor array is constructed by orthogonal wiring on the top and bottom layers; A differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to each two adjacent transmitting electrodes of the capacitor array, obtains the composite current signal generated on the receiving electrode common to each two adjacent transmitting electrodes, and converts it into a measurement signal in the form of a voltage; The frequency domain signal processing module samples the measurement signal ADC and performs a fast Fourier transform. The tolerance between every two capacitors in the capacitor array is extracted from the measurement signal as a characteristic parameter of the capacitor array. The characteristic parameter is used to generate a PUF identifier for the chip to which the capacitor array belongs. The differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is connected to each transmitting electrode of the capacitor array through a first low-pass filter and a fully differential amplifier in sequence. The input end of the junction field effect transistor transimpedance amplifier is connected to each receiving electrode of the capacitor array in sequence. The output end of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module through a high-pass filter, an AC amplifier and a second low-pass filter in sequence. The dual-channel DAC circuit is used to generate synchronous excitation signals with matched amplitudes and opposite phases.

5. The method for measuring capacitance of a capacitor array in a chip according to claim 4, wherein: The frequency domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit and a dual-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to the differential capacitance measurement module for sampling the measurement signal ADC. The discrete Fourier transform circuit and the dual-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the tolerance is calculated by the microcontroller using the amplitude and phase information.

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