Preparation method of high-heat-dissipation plate-level packaging structure and product thereof

Abstract

The invention discloses a preparation method of a high-heat-dissipation board-level packaging structure and a product of the high-heat-dissipation board-level packaging structure. The preparation method comprises the following steps: step 1, mounting a plurality of chips on a bearing sheet; 2, mounting a size heat conduction chip on the chip; 3, performing plastic package on the product obtained in the step 2 to form a plastic package body; 4, grinding and thinning the plastic sealing surface of the plastic sealing body until the heat conducting chip is exposed; step 5, removing the bearing sheet; 6, bonding the products obtained in the step 5 in pairs in a back-to-back manner; step 7, rewiring is carried out on the chip; and 8, the product obtained in the step 7 is split and then cut, and single products are obtained. According to the preparation method of the high-heat-dissipation board-level packaging structure, the heat dissipation performance of the packaging structure is optimized, meanwhile, the strength of the packaging structure is enhanced, warping of the packaging structure is improved, the heat dissipation cost is reduced, the manufacturing process is simple, and mass production is easy.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a preparation method and a product of a high heat dissipation board-level packaging structure. Background Art

[0002] With the increasing requirements of mobile consumer electronic products such as mobile phones, computers, and digital cameras for function integration, large storage space, high reliability, and miniaturized packaging, high-density microelectronic assembly technology has become the mainstream in the new generation of electronic products. In order to match the development speed, the used chips are developing in the directions of higher density, faster speed, smaller size, and lower cost. At the same time, with the increasing richness of the functions of current electronic products, the number of I / O of the fan-in package structure can no longer meet the product requirements. As a kind of wafer-level packaging, the fan-out (FO) package structure, which is mainly for advanced packaging processes with a large number of input / output ports (Input / Output, I / O) and high integration flexibility (multi-chip integration in vertical and horizontal directions), is mostly used for multi-chip, ultra-thin thickness packaging, and three-dimensional system-level packaging. The emergence of wafer-level fan-out package (WLFOP) has greatly increased the number of I / Os of the package body, meeting the development direction of chip multi-functionality. However, due to the increasing market demand, in order to break through the existing methods, it is necessary to combine the PCB board-level production concept with the semiconductor wafer-level packaging method to break the original wafer size limitation, and propose a packaging structure that can accommodate more I / O numbers, reduce the chip size and thickness, integrate more heterogeneous chips to meet the packaging miniaturization requirements, can effectively reduce production costs, improve production efficiency, and ultimately be applied to consumer, high-speed computing, and professional electronic products.

[0003] In order to further reduce costs, manufacturers have started to use larger-size panels as carrier plates and launched panel-level fan-out package (PLFOP). The emergence of panel-level fan-out package technology can effectively achieve larger-area overall packaging, further increase packaging efficiency, reduce packaging costs, and has a broader development prospect. Currently, about 600 ICs can be produced from a 300×300mm 2 silicon wafer. If the panel-level fan-out package technology is used, the number of ICs packaged on a 500×500mm 2 panel can be as high as 2,600, that is, the production volume of fan-out package on a 500×500mm 2 panel will be the production volume of fan-out package on a 300×300mm 2More than 4 times the output of wafer-level fan-out packaging. The board-level fan-out packaging technology has the advantages of lower cost, flexible design, good electrothermal performance, diverse business models, and broad application fields.

[0004] At present, with the increasing integration of modern electronic chips, the packaging feature size of chips is getting smaller and smaller, the power consumption is rising extremely, and the heat generation problem of chips has become an important challenge in the development of board-level packaging processes. The heat dissipation performance of new product packaging is crucial for ensuring the performance, reliability, safety, and user experience of electronic devices. With the continuous improvement of the performance and integration of electronic devices, the heat dissipation problem has become increasingly important. Therefore, heat dissipation has become an indispensable part of new product design and packaging design. Summary of the Invention

[0005] To solve the technical problems existing in the prior art, the purpose of the present invention is to provide a preparation method and product of a high-heat-dissipation board-level packaging structure.

[0006] To achieve the above purpose and reach the above technical effects, the technical solution adopted by the present invention is as follows:

[0007] A preparation method of a high-heat-dissipation board-level packaging structure includes the following steps:

[0008] Step 1: Mount a plurality of chips on a carrier wafer.

[0009] Step 2: Mount a size thermal conductive chip on the chips.

[0010] Step 3: Encapsulate the product obtained in Step 2 to form an encapsulant.

[0011] Step 4: Grind and thin the encapsulation surface of the encapsulant until the thermal conductive chip is exposed.

[0012] Step 5: Remove the carrier wafer.

[0013] Step 6: Bond the products obtained in Step 5 back to back in pairs.

[0014] Step 7: Perform redistribution on the chips.

[0015] Step 8: Split the product obtained in Step 7 and then cut it to obtain single products.

[0016] Further, in Step 1, first attach a sticky film on the carrier wafer, and then mount a plurality of chips on the carrier wafer through the sticky film.

[0017] Further, in Step 2, the size of the thermal conductive chip is smaller than the size of the chip, and the thermal conductive chip is a ceramic chip or a thermal conductive metal chip.

[0018] Further, in Step 3, the encapsulant is made of epoxy-based encapsulant, polyimide or ceramic-based encapsulant.

[0019] Further, the adhesive film is removed in Step 5.

[0020] Further, in Step 6, the products obtained in Step 5 are bonded back-to-back in pairs through a temporary bonding material.

[0021] Further, in Step 7, a passivation layer I, RDL re-wiring, a passivation layer II, and exposed terminals are formed on the chip.

[0022] Further, the exposed terminals are pads for soldering to the PCB board.

[0023] Further, in Step 8, the products obtained in Step 7 are split by means of debonding.

[0024] The present invention also discloses a high heat dissipation board-level packaging structure, which is prepared by using the preparation method of a high heat dissipation board-level packaging structure as described above. The high heat dissipation board-level packaging structure includes a chip and a heat-conducting chip with a size smaller than that of the chip mounted thereon. A passivation layer I, RDL re-wiring, a passivation layer II, and exposed terminals are provided on the chip, and the exposed terminals are pads for soldering to the PCB board.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] The present invention discloses a preparation method of a high heat dissipation board-level packaging structure and its product, which optimizes the heat dissipation performance of the packaging structure, enhances the strength of the packaging structure, improves the warping of the packaging structure, reduces the heat dissipation cost, and has a simple manufacturing process and is easy to mass-produce. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic structural diagram of Step 1 of the present invention;

[0028] Figure 2 It is a schematic structural diagram of Step 2 of the present invention;

[0029] Figure 3 It is a schematic structural diagram of Step 3 of the present invention;

[0030] Figure 4 It is a schematic structural diagram of Step 4 of the present invention;

[0031] Figure 5 It is a schematic structural diagram of Step 5 of the present invention;

[0032] Figure 6 It is a schematic structural diagram of Step 6 of the present invention;

[0033] Figure 7 It is a schematic structural diagram of Step Seven of the present invention;

[0034] Figure 8 It is a schematic structural diagram of Step Eight of the present invention;

[0035] Figure 9 It is a schematic structural diagram of Step Nine of the present invention. Detailed Embodiment

[0036] The present invention will be elaborated in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making the protection scope of the present invention more clearly defined.

[0037] A brief overview of one or more aspects is given below to provide a basic understanding of these aspects. This overview is not an exhaustive survey of all contemplated aspects, and is neither intended to identify key or decisive elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that follows.

[0038] As Figures 1-9 shown, the present invention discloses a preparation method of a high heat dissipation board-level packaging structure, including the following steps:

[0039] Step One: As Figure 1 shown, a sticky film 2 is pasted on the carrier sheet 1, and several chips 3 are respectively mounted on the carrier sheet 1 through the sticky film 2;

[0040] Step Two: As Figure 2 shown, a heat conduction chip 4 with a size smaller than that of the chip is mounted on each chip 3. The heat conduction chip 4 is a ceramic chip, a heat conduction metal chip, etc. This method can reduce the heat dissipation cost without increasing the chip size and thickness, and the manufacturing process is simple and easy to mass-produce. In addition, by adding the heat conduction chip 4, the warping in the manufacturing process can be effectively reduced, and the damage to the chip caused by stress / warping after the finished product is mounted on the board can be improved;

[0041] Step Three: As Figure 3 shown, the product obtained in Step Two is encapsulated to form an encapsulation body 5. The encapsulation body 5 is made of an epoxy resin-based encapsulation material, polyimide, a ceramic-based encapsulation material, etc.;

[0042] Step Four: As Figure 4 shown, the encapsulation surface of the encapsulation body 5 is ground and thinned until the heat conduction chip 4 is exposed;

[0043] Step Five: As Figure 5 shown, the carrier sheet 1 and the sticky film 2 are removed;

[0044] Step Six: As shown in Figure 6 , the products obtained in Step Five are bonded back-to-back in pairs through the temporary bonding material 6. This bonding method is beneficial to improving production efficiency, reducing warpage, and reducing production costs.

[0045] Step Seven: As shown in Figure 7 , a passivation layer I 7, RDL rewiring 8, passivation layer II 9, and exposed terminals 10 are formed above the chip 3. Among them, the exposed terminals 10 are pads for soldering to the PCB board.

[0046] Step Eight: The products obtained in Step Seven are split by means of debonding to obtain the products as shown in Figure 8 , and then cut to obtain the single products as shown in Figure 9 .

[0047] The present invention also discloses a high heat dissipation board-level packaging structure, which is prepared by using the preparation method of a high heat dissipation board-level packaging structure as described above. The high heat dissipation board-level packaging structure includes a chip 3 and a heat-conducting chip 4 with a size smaller than that of the chip and mounted thereon. A passivation layer I 7, RDL rewiring 8, passivation layer II 9, and exposed terminals 10 are provided on the chip 3. The exposed terminals 10 are pads for soldering to the PCB board.

[0048] Example 1

[0049] As shown in Figures 1-9 , a preparation method of a high heat dissipation board-level packaging structure includes the following steps:

[0050] Step One: As shown in Figure 1 , a layer of adhesive film 2 is pasted on the carrier wafer 1, and several chips 3 are respectively mounted on the carrier wafer 1 through the adhesive film 2. The type of the chip 3 can be flexibly selected according to actual needs.

[0051] Step Two: As shown in Figure 2 , a heat-conducting chip 4 with a size smaller than that of the chip is mounted on each chip 3. The heat-conducting chip 4 is a ceramic chip. This method can reduce the heat dissipation cost without increasing the chip size and thickness, and the manufacturing process is simple and easy to mass-produce. In addition, by adding the heat-conducting chip 4, the warpage in the manufacturing process can be effectively reduced, and the damage to the chip caused by the stress / warpage of the finished product after being mounted on the board can be improved.

[0052] Step Three: As shown in Figure 3 , the products obtained in Step Two are encapsulated to form an encapsulation body 5. The encapsulation body 5 is made of an epoxy resin-based encapsulation material.

[0053] Step Four: As shown in Figure 4 , the encapsulation surface of the encapsulation body 5 is ground and thinned until the heat-conducting chip 4 is exposed.

[0054] Step Five: As Figure 5 shown, remove the carrier sheet 1 and the adhesive film 2;

[0055] Step Six: As Figure 6 shown, bond the products obtained in Step Five back-to-back in pairs through the temporary bonding material 6, which is beneficial to improving production efficiency, reducing warpage, and reducing production costs;

[0056] Step Seven: As Figure 7 shown, form a layer of passivation layer I 7, a layer of RDL re - wiring 8, a layer of passivation layer II 9, and a layer of exposed terminals 10 above the chip 3. The exposed terminals 10 are pads for soldering to the PCB board;

[0057] Step Eight: Split the product obtained in Step Seven by means of debonding to obtain the product as Figure 8 shown, and then perform cutting to obtain the single product as Figure 9 shown.

[0058] A high - heat - dissipation board - level packaging structure is prepared by using the preparation method of a high - heat - dissipation board - level packaging structure as described above. The high - heat - dissipation board - level packaging structure includes a chip 3 and a heat - conducting chip 4 with a size smaller than that of the chip mounted thereon. A passivation layer I 7, an RDL re - wiring 8, a passivation layer II 9, and exposed terminals 10 are provided on the chip 3. The exposed terminals 10 are pads for soldering to the PCB board.

[0059] For the parts or structures not specifically described in the present invention, existing technologies or existing products can be adopted, and no further elaboration will be made here.

[0060] The above are only the embodiments of the present invention, and thus do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A preparation method of a high heat dissipation board-level packaging structure, characterized in that, It includes the following steps: Step 1: Mount a number of chips on a carrier wafer; Step 2: Mount a thermal conductive chip with a size smaller than that of the chip on the chip; Step 3: Encapsulate the product obtained in Step 2 to form an encapsulant; Step 4: Grind and thin the encapsulation surface of the encapsulant until the thermal conductive chip is exposed; Step 5: Remove the carrier wafer; Step 6: Bond the products obtained in Step 5 back-to-back in pairs; Step 7: Perform redistribution on the chips; Step 8: Split the product obtained in Step 7 and then cut it to obtain single products.

2. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that In Step 1, first attach a sticky film on the carrier wafer, and then mount a number of chips on the carrier wafer through the sticky film.

3. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that, In Step 2, the size of the thermal conductive chip is smaller than that of the chip, and the thermal conductive chip is a ceramic chip or a thermal conductive metal chip.

4. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that, In Step 3, the encapsulant is made of an epoxy resin-based encapsulant, polyimide or a ceramic-based encapsulant.

5. The preparation method of a high heat dissipation board-level packaging structure according to claim 2, characterized in that, The sticky film is removed in Step 5.

6. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that, In Step 6, bond the products obtained in Step 5 back-to-back in pairs through a temporary bonding material.

7. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that In Step 7, form a passivation layer I, RDL redistribution, a passivation layer II and exposed terminals on the chip.

8. The preparation method of a high heat dissipation board-level packaging structure according to claim 7, characterized in that, The exposed terminals are pads for soldering to a PCB board.

9. The preparation method of a high heat dissipation board-level packaging structure according to claim 1, characterized in that, In Step 8, split the product obtained in Step 7 by means of debonding.

10. A high heat dissipation board-level packaging structure, characterized in that, Prepared by using the preparation method of a high heat dissipation board-level packaging structure according to any one of claims 1-9, the high heat dissipation board-level packaging structure includes a chip and a thermal conductive chip with a size smaller than that of the chip mounted thereon, a passivation layer I, RDL redistribution, a passivation layer II and exposed terminals are provided on the chip, and the exposed terminals are pads for soldering to a PCB board.

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