Method for improving bonding force between bump and bottom and chip structure

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a method for improving binding force between a bump and a bottom and a chip structure. The method comprises the following steps of: depositing a seed layer on a substrate of a wafer, coating a photoresist film on the seed layer, removing the redundant photoresist film, projecting a target pattern onto the photoresist film, developing, removing the redundant photoresist film, forming an RDL wiring pattern layer on the redundant photoresist film, depositing a metal layer, removing the photoresist film in the RDL wiring pattern layer, and covering an insulating layer, manufacturing a wiring opening, manufacturing a bump in the wiring opening, and removing the redundant insulating layer and the seed layer; the seed layer is made of Ti, Cu and a thin film, the thin film is obtained by curing nano-composite liquid, and the nano-composite liquid is made of silicon dioxide, dopamine, 3-mercaptopropyltriethoxysilane, copper sulfate and PVP. The chip structure is prepared by the method. According to the invention, the structural bonding force between chip structures can be improved, and the problem of poor salient points is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and particularly, to a method for improving the bonding force between bumps and the bottom, and a chip structure. Background Art

[0002] With the development of chip packaging technology, higher requirements have been put forward for the number and layout of bumps in chip packaging. According to the position and function of bumps in chip packaging, they are divided into active bumps and support bumps.

[0003] Support bumps are generally distributed on the passivation or passivation layer on the chip surface, and do not need to be connected to the chip pin pads (Pads), providing a stress support for subsequent flip chip or FC-BGA operations. During the layout of support bumps, factors such as the pitch of solder joints on the substrate and the frame need to be considered, so the diameter of support bumps will be greatly restricted, resulting in poor bonding force between support bumps and the substrate passivation layer, and easy occurrence of bump dropping or abnormal bumps. Summary of the Invention

[0004] In order to overcome the defects in the prior art, the present invention provides a method for improving the bonding force between bumps and the bottom, and a chip structure.

[0005] The technical solution of the present invention is as follows: The present invention fabricates a chip structure, which is a chip-related structure and relates to a chip packaging structure. The chip structure includes a substrate, a seed layer is covered on the substrate, a metal layer is covered on the seed layer, a bump is covered on the metal layer, the seed layer does not completely or completely cover the substrate, and the bump does not completely or completely cover the metal layer.

[0006] The chip structure is prepared according to a method for improving the bonding force between bumps and the bottom, including the following steps: Deposit a seed layer on the substrate of the wafer, coat a photoresist film on the seed layer, remove the excess photoresist film, project the target pattern onto the photoresist film, develop, remove the excess photoresist film, form an RDL wiring pattern layer on the remaining photoresist film by the RDL method, deposit a metal layer on the RDL wiring pattern, remove the photoresist film in the RDL wiring pattern layer, cover an insulating layer, make a wiring opening in the insulating layer, make a bump in the wiring opening, and remove the excess insulating layer and seed layer.

[0007] Further, the material of the seed layer includes Ti, Cu, and a thin film, the thin film is obtained by curing a nano-composite liquid, and the raw materials of the nano-composite liquid include silicon dioxide, dopamine, 3-mercaptopropyltriethoxysilane, copper sulfate, and PVP.

[0008] Further, when depositing a seed layer on the substrate surface of the wafer, Ti and / or Cu is deposited on the substrate to obtain a base material. After the base material is soaked in an ethanethiol solution, a nanocomposite solution is coated thereon, and then cured to obtain a thin film.

[0009] Further, the preparation method of the nanocomposite solution includes the following steps: Dopamine is added to a silica solution, the pH is adjusted, stirred, and centrifuged to obtain silica-polydopamine particles; the silica-polydopamine particles are dispersed in a solvent, 3-mercaptopropyltriethoxysilane is added, stirred, and centrifuged to obtain modified particles; the modified particles and PVP are added to a copper sulfate solution to obtain a nanocomposite solution.

[0010] Further, the material of the substrate includes silicon nitride and silica.

[0011] Further, the thickness of the metal layer is 1-5 μm.

[0012] Further, the thickness of the insulating layer is 30-80 μm.

[0013] Further, the material of the bump includes at least one of Cu, Sn, and copper-tin alloy, and the material of the metal layer includes Cu.

[0014] Further, when fabricating a bump in a wiring opening, the bump is fabricated by electroplating and reflow processes, and the height of the bump after reflow is 30-80 μm.

[0015] Further, the thickness of the seed layer is 0.05-1 μm, and the thickness of the thin film is 10-20 nm.

[0016] According to the inventive concept of the present invention, the advantages and beneficial effects of the present invention are as follows: The present invention provides a method for improving the bonding force between a bump and the bottom, and a chip structure. Compared with the prior art, the beneficial effects of the present invention are as follows: (1) In the prior art, the bonding force between the support bump and the substrate passivation layer is very poor, and the bump is prone to falling off or abnormal bumps. Therefore, the present invention constructs a seed layer and a metal layer between the bump and the substrate. The seed layer enhances the bonding force between the substrate and the metal layer through chemical bonding, conductivity, and blocking effects. The metal layer enhances the bonding force between the seed layer and the bump by improving the conductivity path and interface compatibility. The multi-layer structure of the present application synergistically increases the bonding force between the structures and also improves the bonding force between the bump and the bottom material.

[0017] (2) Although the materials selected for the seed layer of the present invention (such as Ti, Cu, or Ti / Cu laminate) have good electrical conductivity, the bonding force between the Ti seed layer and the substrate is limited, and peeling or cracking is likely to occur in subsequent processes. The Cu seed layer may experience performance degradation due to diffusion or oxidation during long-term use, especially when combined with the subsequent electroplated layer under the influence of interfacial stress. Ultimately, the bonding situation between the structures will be affected.

[0018] Therefore, the present invention provides a new method for preparing the seed layer: The present invention prepares a nano-composite solution, which can be cured into a thin film. In combination with Ti and / or Cu, a seed layer is prepared. Specifically: 1) Ti and / or Cu are deposited on the substrate to obtain a base material. Soaking the base material in an ethanethiol solution enhances the surface activity of the base material and provides better interfacial conditions for the attachment of the nano-composite solution. The thiol groups in the nano-composite solution further form chemical bonds with the ethanethiol-treated base material, enhancing the interfacial bonding force. 2) The raw materials of the nano-composite solution include silica, dopamine, 3-mercaptopropyltriethoxysilane, and copper sulfate. Silica provides mechanical strength and chemical stability, dopamine enhances the adhesion and reactivity of the particles in the raw materials, and 3-mercaptopropyltriethoxysilane achieves strong bonding with the substrate and modified particles through thiol and siloxane groups. PVP improves the dispersibility of the particles in the raw materials, and copper ions can be evenly distributed in the thin film through coordination with thiol and PVP, enhancing electrical conductivity and interfacial compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for describing the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a schematic diagram of the structure after coating the glue for the present invention; Figure 2 It is a schematic diagram of the structure after developing for the present invention; Figure 3 It is a schematic diagram of the structure after electroplating Cu for the present invention; Figure 4 It is a schematic diagram of the structure after re-coating the glue layer for the present invention; Figure 5 It is a schematic diagram of the structure after opening the wiring for the present invention; Figure 6 It is a schematic diagram of the structure after preparing the bumps for the present invention; The labels in the figure are: 1. Substrate; 2. Seed layer; 3. Photoresist film; 4. RDL wiring pattern; 5. Metal layer; 6. Insulating layer; 7. Wiring opening; 8. Bump. Detailed Implementation Modes

[0021] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described below in conjunction with specific implementation modes. Unless otherwise specified, the methods are all conventional methods, and the raw materials can all be obtained from public commercial channels unless otherwise specified.

[0022] Any embodiment described as "exemplary" here does not have to be construed as superior to other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0023] Method 1 The present invention provides a method for improving the bonding strength between bumps and the bottom. Referring to Figures 1 - 6 , the specific steps are as follows: 1) A layer of metal is deposited on the surface of the substrate 1 of the wafer by physical vapor deposition (PVD) as the seed layer 2 for subsequent electroplating. The materials selected for the seed layer 2 include Ti, Cu, or two layers of Ti and Cu stacked. Among them, the thickness of the seed layer 2 is 0.05 - 1 μm. When the material selected for the seed layer 2 is Ti alone, the thickness of Ti is 0.1 μm; when the material selected for the seed layer 2 is Cu alone, the thickness of Cu is 0.2 μm; the substrate 1 is a material containing a passivation layer or a material with passivation effect, and the materials selected for the substrate 1 include silicon nitride and silicon dioxide.

[0024] 2) After the deposition of the metal seed layer 2 is completed, as Figure 1 shown, a layer of photoresist film 3 is coated on the surface of the metal seed layer 2 from low speed to high speed by spin coating. Among them, the thickness of the photoresist film 3 is about 2 μm. After coating, the chemical EBR method is used to spray a solvent on the edge of the wafer to remove the excess photoresist film 3 to prevent the accumulation of the photoresist film 3. Among them, the photoresist film 3 is formed by photoresist, and the sprayed solvent can be a conventional EBR solvent, including PGMEA.

[0025] 3) After the coating of the photoresist is completed, through the step-by-step exposure method, that is, using a step-by-step lithography machine, the target pattern is projected onto the photoresist film 3 to make the photoresist film 3 photosensitive and undergo chemical and physical changes; then the wet development method is used to dissolve the unnecessary photoresist film 3 with a chemical solution, and the remaining photoresist film 3 forms the RDL wiring pattern layer 4 as Figure 2 shown. The wiring width is not specifically limited and can be flexibly adjusted according to the specifications of the subsequent bump 8 pitch and bump 8 diameter. Among them, the chemical solution can be a conventional photoresist remover, including PGMEA.

[0026] 4) On the formed RDL wiring pattern 4, as Figure 3As shown, electrolytic deposition of thin Cu is carried out using a full - surface electroplating process to deposit a uniform and well - adhered metal layer 5, achieving the filling of the wiring pattern to serve as the conductive layer for subsequent electroplated bumps 8. Among them, the thickness of the metal layer is 1 - 5 μm, and preferably the thickness of the metal layer 5 is about 2 μm.

[0027] 5) Remove the photoresist film 3 of the RDL pattern formed on the wafer surface by a wet de - glue method, and re - cover a layer of insulating layer 6 by spin - coating. As Figure 4 shown. Prepared in this way, the insulating layer 6 can cover the metal layer 5 and the seed layer 2 on the wafer.

[0028] Among them, the material of the insulating layer 6 can be a photoresist film 3 with insulating properties. The thickness of the insulating layer is 30 - 80 μm, and preferably the thickness of the insulating layer 6 is about 65 μm. However, it can be flexibly adjusted according to the specifications of the subsequent bump 8 height and bump 8 diameter when necessary.

[0029] 6) Adopt the exposure and development methods in step 3) to make the wiring openings 7 required for subsequent support bumps (i.e., bumps 8) on the insulating layer 6. The production can be completed by an etching process, as Figure 5 shown. This can expose the RDL pattern layer, facilitating the subsequent growth of support bumps (i.e., bumps 8) on the metal layer 5.

[0030] 7) Make bumps 8 in the wiring openings 7 through electroplating and reflow processes. The material of the bumps 8 is Cu, Sn, or a copper - tin alloy. In this way, the conduction between the RDL layers is achieved, and the interconnection with each bottom line is realized; the height of the bump after reflow is 30 - 80 μm, and preferably the height of the bump 8 after reflow is about 65 μm. However, the heights of Cu and Sn can be flexibly adjusted according to process and design requirements when necessary.

[0031] 8) Remove the excess insulating layer 6 around the bumps 8 by a wet method using chemical potions; then use an etching potion to remove the excess seed layer 2; as Figure 6 shown. This can achieve the combination of the bumps 8 and the bottom material. Among them, the chemical potion can be a conventional de - glue agent, including PGMEA.

[0032] The processes, methods, potions, or chemical potions not detailed above are conventional means in the art. Those skilled in the art can clearly know them and are not key factors affecting the technical effects of this application, so they will not be elaborated.

[0033] Finally, prepare the structure as Figure 6 shown according to Method 1: A seed layer 2 is covered on the substrate 1, a metal layer 5 is covered on the seed layer 2, and bumps 8 are covered on the metal layer 5.

[0034] The seed layer 2 may not completely cover the substrate 1, and the seed layer 2 can be arranged in an array according to actual needs. The bump 8 may also not completely cover the metal layer 5.

[0035] It should be noted that in the prior art, the bonding force between the support bump and the substrate passivation layer is very poor, and the bump is likely to fall off or be abnormal.

[0036] In this application, a seed layer 2 and a metal layer 5 are constructed between the bump 8 and the substrate 1. The seed layer 2 enhances the bonding force between the substrate 1 and the metal layer 5 through chemical bonding, conductivity, and blocking effects, etc. The metal layer 5 enhances the bonding force between the seed layer 2 and the bump 8 by improving the conductivity path and interface compatibility. The multi-layer structure in this application synergistically increases the bonding force between the structures and also improves the bonding force between the bump 8 and the bottom material.

[0037] Method 2: In Method 1, although the material selection of the seed layer 2 (such as Ti, Cu, or Ti / Cu laminate) has good conductivity, the bonding force between the Ti seed layer and the substrate 1 is limited, and peeling or cracking is likely to occur in subsequent processes. The Cu seed layer may experience performance degradation due to diffusion or oxidation during long-term use, especially affected by interface stress when combined with the subsequent electroplated layer. Ultimately, it will affect the bonding situation between the structures.

[0038] The present invention further improves the preparation method of the material of the seed layer 2, and the specific steps are as follows: Use the PVD method to deposit a 50-nm Ti layer on the substrate 1 using a high-purity Ti target. Then deposit a 50-nm Cu layer using a high-purity Cu target. In this way, the base material is prepared. Among them, the material of the substrate 1 is silicon dioxide.

[0039] Prepare a 0.01M ethanethiol solution with ethanethiol and ethanol, immerse the base material in the 0.01M ethanethiol solution, just submerge it, treat it at room temperature for 5 minutes, rinse the base material with ethanol, and dry it with nitrogen.

[0040] Take 5 g of silicon dioxide, disperse it in 100 mL of deionized water, ultrasonically disperse it for 30 minutes, add 0.2 g of 0.2 wt% dopamine, adjust the pH to 8.5 (Tris buffer solution can be used), stir for 12 hours, centrifuge at 8000 rpm for 10 minutes, wash it 3 times with deionized water, and dry it for standby to obtain silicon dioxide polydopamine particles.

[0041] Disperse 2 g of silicon dioxide polydopamine particles in 100 mL of 1 wt% ethanol, ultrasonically disperse it for 30 minutes, add 1.9 g of 0.1M 3-mercaptopropyltriethoxysilane, stir for 6 hours, centrifuge at 8000 rpm for 10 minutes, wash it 3 times with ethanol, and dry it for standby to obtain modified particles.

[0042] Prepare a 0.1 - 0.5 M copper sulfate solution using copper sulfate and deionized water. Add 1 g of modified particles and 0.5 g of 0.5 wt% PVP to 100 mL of 0.5 M copper sulfate solution, and ultrasonically disperse to obtain a nano composite solution.

[0043] Spin - coat the nano composite solution on a substrate, and cure it after coating. A thin film is formed on the substrate, and the thickness of the thin film is about 10 - 20 nm, preferably about 15 nm. Among them, the curing can be thermal curing, UV curing, or a combination of the two.

[0044] The seed layer 2 is prepared in this way, and the structure of the seed layer 2 includes a substrate and a thin film.

[0045] Among them, the raw materials: Silica: silica nanoparticles with a particle size of 5 - 10 nm, which can be purchased from Sigma - Aldrich; Dopamine: dopamine hydrochloride, which can be purchased from Sigma - Aldrich; Copper sulfate: analytically pure; PVP: polyvinylpyrrolidone with a molecular weight of 10,000, which can be purchased from Sigma - Aldrich.

[0046] It should be noted that Deposit Ti first, which can act as an adhesion layer, and then deposit Cu, which can act as a conductive layer. Immerse the substrate in an ethanethiol solution. The thiol group in the ethanethiol molecule has strong coordination ability and can form stable chemical bonds on the substrate surface. For example, it can form Cu - S on the substrate surface, enhance the binding force between the substrate and the thin film through the Cu - S chemical bond, and at the same time reduce the surface oxidation of Cu.

[0047] Using silica as the core, the outer layer is wrapped with polydopamine. Thiol functional groups are introduced on the particle surface through 3 - mercaptopropyltriethoxysilane. In addition, the self - polymerization of dopamine to form polydopamine also endows the particles with adhesion characteristics similar to mussel adhesive proteins and has a certain self - healing ability, which can reduce the propagation of micro - cracks. When preparing the nano composite solution, copper ions are introduced by the copper sulfate solution.

[0048] Therefore, the nano composite solution is prepared layer by layer. Dopamine can provide adhesion, silica provides mechanical strength, the thiol group forms a coordination bond with copper ions to improve the dispersion uniformity of copper ions, and PVP can act as a dispersant and stabilizer to prevent the aggregation of copper ions.

[0049] After the substrate is treated with ethanethiol, in cooperation with the nano composite solution, it can enhance the interfacial binding force through dual thiol functionalization, form a physical barrier, reduce the diffusion and oxidation of copper ions, and also increase the compatibility of the thin film with the substrate and the metal layer 5 respectively.

[0050] In the following examples and comparative examples, the parameter range values in Method 1 will affect the final detection results. Therefore, for the convenience of detection and comparison, when the parameter range values are involved, the preferred point values in the parameter range values are uniformly used as specific parameters. For example: the thickness of the metal layer 5 is 2 um, the thickness of the insulating layer 6 is 65 um, the height of the bump 8 after reflow is 65 um, and the thickness of the thin film is 15 nm.

[0051] Example 1 Prepare the sample according to the steps of Method 1. The seed layer 2 is also prepared according to the method of Method 1.

[0052] Among them, the material of the substrate 1 is silicon dioxide.

[0053] Seed layer 2: Use PVD method to deposit a 60-nm Ti layer on the substrate 1 using a high-purity Ti target, and then deposit a 60-nm Cu layer using a high-purity Cu target to prepare the substrate in this way.

[0054] Example 2 Prepare the sample according to the steps of Method 1, but the seed layer 2 is prepared according to the method of Method 2.

[0055] Among them, the material of the substrate 1 is silicon dioxide.

[0056] Example 3 Different from Example 2, do not deposit Ti: Use PVD method to deposit a 50-nm Cu layer on the substrate 1 using a high-purity Cu target to prepare the substrate in this way.

[0057] The rest is the same as Example 2.

[0058] Comparative Example 1 Different from Example 1 and Example 2, do not prepare the seed layer 2. The rest is prepared according to the steps of Method 1.

[0059] Finally, the structure prepared according to Method 1 is: the substrate 1 is covered with the metal layer 5, and the metal layer 5 is covered with the bump 8.

[0060] Detect the samples prepared in Examples 1-3 and Comparative Example 1: Pull-out test: Use the fixture of the Dage 4000 pull-out tester to fix the top of the bump 8 of the sample, and apply a vertically upward pulling force until the sample structure shows separation or fracture.

[0061] Parameter: Pull-out speed: 50 um / min Record the maximum pull-out force (breaking force). The higher the pull-out force, the stronger the bonding force.

[0062] The results are shown in Table 1 below: Table 1

[0063] Analysis: Comparing Examples 1-3 with Comparative Example 1, Comparative Example 1 has no seed layer and the lowest average drawing force, and the bonding force between structures in the sample is poor. This shows that the presence of the seed layer 2 significantly improves the bonding force between structures.

[0064] In both Example 2 and Example 3, Method 2 was used to prepare the seed layer 2, and Cu was not deposited in Example 3; their drawing forces are significantly higher than those of Example 1 and Comparative Example 1, indicating that preparing the seed layer 2 by Method 2 helps to improve the bonding force between structures.

[0065] Comparing between Example 2 and Example 3, the average drawing force of Example 2 is higher, indicating that when Ti and Cu are deposited simultaneously, the bonding force between structures can be further improved.

[0066] In summary, the above specific examples and comparative examples are only for clearly illustrating the present invention and should not be construed as limiting the present invention. Those skilled in the art should understand that without departing from the spirit and scope of the present invention, various equivalent substitutions, modifications, changes or improvements can be made to the technical solutions and their implementation manners of the present invention, and these changes or improvements all fall within the scope of the present invention. The protection scope of the present invention is subject to the appended claims.

Claims

1. A method for improving the bonding strength between bumps and the bottom, characterized in that, It includes the following steps: Deposit a seed layer on the substrate of the wafer, coat a photoresist film on the seed layer, remove the excess photoresist film, project the target pattern onto the photoresist film, develop, remove the excess photoresist film, form an RDL wiring pattern layer on the remaining photoresist film by the RDL method, deposit a metal layer on the RDL wiring pattern, remove the photoresist film in the RDL wiring pattern layer, cover with an insulating layer, make a wiring opening in the insulating layer, make bumps in the wiring opening, and remove the excess insulating layer and seed layer; Among them, the material of the seed layer includes Ti, Cu, and a thin film, and the thin film is obtained by curing a nano-composite solution. The raw materials of the nano-composite solution include silicon dioxide, dopamine, 3-mercaptopropyltriethoxysilane, copper sulfate, and PVP.

2. A method for improving the bonding strength between the bump and the bottom according to claim 1, characterized in that, When depositing the seed layer on the surface of the substrate of the wafer, deposit Ti and / or deposit Cu on the substrate to obtain a substrate material. After soaking the substrate material in an ethanethiol solution, coat the nano-composite solution and cure to obtain a thin film.

3. A method for improving the bonding strength between a bump and a bottom according to claim 1, characterized in that, The preparation method of the nano-composite solution includes the following steps: Add dopamine to the silicon dioxide solution, adjust the pH, stir, and centrifuge to obtain silicon dioxide polydopamine particles; disperse the silicon dioxide polydopamine particles in a solvent, add 3-mercaptopropyltriethoxysilane, stir, and centrifuge to obtain modified particles; add the modified particles and PVP to the copper sulfate solution to obtain the nano-composite solution.

4. A method for improving the bonding strength between a bump and a bottom, according to claim 1, characterized in that The material of the substrate includes silicon nitride and silicon dioxide.

5. A method for improving the bonding strength between the bump and the bottom, as claimed in claim 1, wherein The thickness of the metal layer is 1-5 μm.

6. A method for improving the bonding strength between a bump and a bottom, as claimed in claim 1, wherein The thickness of the insulating layer is 30-80 μm.

7. A method for improving the bonding strength between a bump and a bottom, as claimed in claim 1, wherein The material of the bump includes at least one of Cu, Sn, and copper-tin alloy, and the material of the metal layer includes Cu.

8. A method for improving the bonding strength between a bump and a bottom according to claim 1, characterized in that, When making bumps in the wiring opening, make the bumps by electroplating and reflow processes, and the height of the bumps after reflow is 30-80 μm.

9. A method for improving the bonding strength between a bump and a bottom, as claimed in claim 1, wherein The thickness of the seed layer is 0.05-1 μm, and the thickness of the thin film is 10-20 nm.

10. A chip structure, which is prepared by the method for improving the bonding force between bumps and the bottom according to any one of claims 1-9, characterized in that, The chip structure includes a substrate, a seed layer is covered on the substrate, a metal layer is covered on the seed layer, a bump is covered on the metal layer, the seed layer does not completely or completely cover the substrate, and the bump does not completely or completely cover the metal layer.

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