Cascode amplifier, power supply and server

Abstract

The embodiment of the invention provides a cascode amplifier, a power supply and a server. The cascode amplifier comprises a substrate, a GaN transistor and an S transistor. The substrate comprises a plate, a control pin, a first pole pin and a second pole pin. The GaN transistor is arranged on the plate, the GaN transistor comprises a first electrode, a second electrode and a control electrode, the GaN transistor comprises a first surface, the first surface deviates from the plate, the first electrode, the second electrode and the control electrode of the GaN transistor are arranged on the first surface, and the first electrode of the GaN transistor is connected to the first electrode pin. The S transistor comprises a first electrode, a second electrode and a control electrode; the first electrode of the S transistor is connected to the second electrode of the GaN transistor, and the second electrode of the S transistor is connected to the control electrode and the second electrode pin of the GaN transistor. The control electrode of the S transistor comprises a plurality of first connection points, and the control electrode of the S transistor is connected to the control pin through the plurality of first connection points.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a cascode amplifier, a power supply, and a server. Background Art

[0002] The Cascode amplifier structure is composed of a cascaded GaN (gallium nitride) HEMT (High Electron Mobility Transistor) and an Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the prior art, the Si MOSFET in the cascode amplifier is prone to failure in a high-temperature environment, thereby causing the cascode amplifier to fail. Summary of the Invention

[0003] The embodiments of this application aim to provide a cascode amplifier, a power supply, and a server for improving the problem of cascode amplifier failure.

[0004] To achieve the above objective, the embodiments of this application provide the following technical solutions:

[0005] On the one hand, a cascode amplifier is provided. The cascode amplifier includes: a substrate, a GaN transistor, and an Si transistor. The substrate includes a board material, a control pin, a first pole pin, and a second pole pin, and the control pin, the first pole pin, and the second pole pin are disposed on the board material. The GaN transistor is disposed on the board material. The GaN transistor includes a first pole, a second pole, and a control pole. The GaN transistor includes a first surface that faces away from the board material, and the first pole, the second pole, and the control pole of the GaN transistor are disposed on the first surface. The first pole of the GaN transistor is connected to the first pole pin. The Si transistor includes a first pole, a second pole, and a control pole; the first pole of the Si transistor is connected to the second pole of the GaN transistor, the second pole of the Si transistor is connected to the control pole and the second pole pin of the GaN transistor. The control pole of the Si transistor includes a plurality of first connection points, and the control pole of the Si transistor is connected to the control pin through the plurality of first connection points.

[0006] In the above common-source common-gate amplifier, the control electrode of the Si transistor includes a plurality of first connection points, and the voltages of the plurality of first connection points are the same. The plurality of first connection points are distributed on the second outer surface, so that the gate voltage at each part of the second outer surface can be made more uniform. Furthermore, the voltages of the electrical signals received by the control electrodes of the plurality of Si transistor cells are more uniform, thereby reducing the voltage drop between the control electrodes of the plurality of Si transistor cells and the first connection points. In this way, the opening degree of the plurality of Si transistor cells can be increased, and further, the leakage current of the Si transistor cells can be reduced, and the heat generated by the Si transistor cells can be reduced, thereby avoiding excessive local temperature of the Si transistor, and further avoiding the failure of the Si transistor, and further improving the problem of the failure of the common-source common-gate amplifier.

[0007] In some embodiments, the Si transistor includes a first outer surface and a second outer surface arranged opposite to each other. The first outer surface faces the substrate. The first pole of the Si transistor is disposed on the first outer surface, and the second pole and the control electrode of the Si transistor are disposed on the second outer surface. Among them, the plurality of first connection points are disposed on the second outer surface and are arranged along the edge of the second pole of the Si transistor.

[0008] With such an arrangement, the distribution of the plurality of first connection points on the second outer surface can be made relatively uniform, thereby reducing the maximum distance between the Si transistor cell and the first connection point, reducing the voltage drop between the Si transistor cell far from the first connection point and the first connection point, increasing the opening degree of the Si transistor cell far from the first connection point, reducing the heat generated by it, and further avoiding excessive temperature of the Si transistor cell, thereby reducing the risk of failure of the Si transistor cell in the Si transistor, that is, reducing the risk of failure of the Si transistor.

[0009] In some embodiments, the plurality of first connection points are arranged at equal intervals along the edge of the second pole of the Si transistor.

[0010] With such an arrangement, the distribution of the plurality of first connection points on the second outer surface can be made more uniform, further improving the voltage uniformity of the control electrodes of the plurality of Si transistor cells, improving the uniformity of the opening degrees of the plurality of Si transistor cells, and further avoiding overheating of the Si transistor cells in the local area, thereby reducing the risk of Si transistor failure.

[0011] In some embodiments, the control electrode of the Si transistor further includes a plurality of first control electrode windows. The plurality of first control electrode windows are disposed on the second outer surface and are arranged along the edge of the second pole of the Si transistor. At least one first connection point is disposed on one first control electrode window.

[0012] Among them, the first control gate window can provide a platform for setting the first connection point, thereby facilitating the setting of the first connection point and the connection between the first connection point and the control pin.

[0013] In some embodiments, the control gate of the Si transistor further includes a first control gate window, which is disposed on the second outer surface and surrounds the second pole of the Si transistor, and a plurality of first connection points are disposed on the first control gate window.

[0014] Among them, by making the first control gate window surround the second pole of the Si transistor, the area of the first control gate window is relatively large, thereby facilitating the adjustment of the position and number of the first connection points.

[0015] In some embodiments, the Si transistor includes a first outer surface and a second outer surface disposed opposite to each other. The first outer surface faces the substrate. The first pole of the Si transistor is disposed on the first outer surface, and the second pole and the control gate of the Si transistor are disposed on the second outer surface. Among them, a plurality of first connection points are disposed on the second outer surface. The plurality of first connection points are divided into a first group of first connection points and a second group of first connection points. The first group of first connection points and the second group of first connection points are respectively disposed on two opposite sides of the second pole of the Si transistor.

[0016] Exemplarily, the first group of first connection points and the second group of first connection points are respectively disposed on two sides of the second pole of the Si transistor in the first direction, so as to reduce the width of the Si transistor in the second direction. Among them, the second direction may intersect with the first direction.

[0017] In some embodiments, the control gate of the Si transistor further includes two first control gate windows, which are disposed on the second outer surface and are respectively disposed on two opposite sides of the second pole of the Si transistor. The first group of first connection points and the second group of first connection points are respectively disposed on the two first control gate windows.

[0018] Among them, a group of first connection points is disposed on one first control gate window. At this time, the area of the first control gate window is relatively large, and thus the number and spacing of the first connection points disposed on the first control gate window can be designed according to requirements.

[0019] In some embodiments, the two first control gate windows are respectively disposed on two sides of the second pole of the Si transistor in the first direction; the first control gate window is strip-shaped and extends along the second direction, where the second direction intersects with the first direction.

[0020] Among them, since the first control gate window is designed to be strip-shaped, the area of the first control gate window is relatively large, thereby facilitating the adjustment of the number of the first connection points disposed on the first control gate window according to requirements and the distance between two adjacent first connection points.

[0021] In some embodiments, the common-source and common-gate amplifier also includes: a first connector, the first connector includes a first end and a second end that are connected; the first end includes multiple first connection ends, the multiple first connection ends are respectively connected to multiple first connection points, and the second end is connected to a control pin.

[0022] By making the first end of the first connecting member include a plurality of first connecting ends, and making the plurality of first connecting ends connected to a plurality of first connecting points respectively, the plurality of first connecting points can have electrical signals with the same voltage.

[0023] In some embodiments, the Si transistor is disposed on the first surface, the Si transistor includes a first outer surface and a second outer surface disposed opposite to each other, the first outer surface faces the first surface, the first electrode of the Si transistor is located on the first outer surface, the second electrode of the Si transistor and the control electrode of the Si transistor are located on the second outer surface. The control electrode of the GaN transistor includes a plurality of second connection points, the plurality of second connection points are disposed on the first surface and connected to the second electrode of the Si transistor.

[0024] The control electrode of the GaN transistor includes a plurality of second connection points, and the plurality of second connection points are all connected to the second electrode of the Si transistor, so the voltages of the plurality of second connection points are the same. The plurality of second connection points are distributed on the first surface, so that the gate voltages at various locations on the first surface can be more uniform, and thus the voltages of the electrical signals received by the control electrodes of the plurality of GaN transistor cells can be more uniform, so that the voltage drop between the control electrodes of the plurality of GaN transistor cells and the second connection points can be reduced, so that the opening degree of the plurality of GaN transistor cells can be increased, so that the leakage current of the GaN transistor cells can be reduced, and the heat generated by the GaN transistor cells can be reduced, so that the temperature at various locations on the first surface of the GaN transistor can be more uniform, so that the heat transferred from the GaN transistor to the Si transistor can be reduced, so that the local temperature of the Si transistor can be avoided from being too high, so that the Si transistor can be avoided from failing, and so that the problem of failure of the common-source common-gate amplifier can be improved.

[0025] In some embodiments, a plurality of second connection points are disposed along an edge of the Si transistor.

[0026] Among them, multiple second connection points are arranged along the edge of the Si transistor, which can make the distribution of the multiple second connection points on the first surface relatively uniform, thereby reducing the maximum distance between the GaN transistor cell and the second connection point, increasing the voltage drop between the GaN transistor cell far from the second connection point and the second connection point, increasing the opening degree of the GaN transistor cell far from the second connection point, thereby reducing the heat generated by the GaN transistor cell far from the second connection point, and further avoiding local overheating of the GaN transistor. Further, it is possible to reduce the excessive heat received by the local part of the Si transistor from the GaN transistor. In this way, the heat received by the Si transistor cells in the local part of the Si transistor can be reduced, and further the risk of the Si transistor cells having too high a temperature can be avoided, thereby reducing the risk of failure of the Si transistor cells in the Si transistor, that is, reducing the risk of failure of the Si transistor.

[0027] In some embodiments, the multiple second connection points are arranged at equal intervals along the edge of the Si transistor.

[0028] With such an arrangement, the distribution of the multiple second connection points on the first surface can be made more uniform, further improving the voltage uniformity of the control electrodes of the multiple GaN transistor cells and the uniformity of the opening degrees of the multiple GaN transistor cells, thereby avoiding overheating of the GaN transistor cells in the local part, reducing the heat received by the Si transistor, and thus reducing the risk of failure of the Si transistor.

[0029] In some embodiments, the control electrode of the GaN transistor further includes multiple second control electrode windows, the multiple second control electrode windows are arranged on the first surface and along the edge of the Si transistor, and at least one second connection point is arranged on one second control electrode window.

[0030] Among them, the second control electrode window can provide a platform for the setting of the second connection point, thereby facilitating the setting of the second connection point and the connection of the second connection point to the second pole of the Si transistor.

[0031] In some embodiments, the control electrode of the GaN transistor further includes a second control electrode window, the second control electrode window is arranged on the first surface and surrounds the Si transistor, and multiple second connection points are arranged on the second control electrode window.

[0032] Among them, by making the second control electrode window surround the Si transistor, the area of the second control electrode window can be increased, and further a larger platform can be provided for the setting of the second connection point, thereby facilitating the adjustment of the position and quantity of the second connection point.

[0033] In some embodiments, the multiple second connection points are divided into a first group of second connection points and a second group of second connection points, and the first group of second connection points and the second group of second connection points are respectively disposed on opposite sides of the Si transistor.

[0034] Among them, the multiple second connection points are divided into two groups, and the first group of second connection points and the second group of second connection points are respectively disposed on both sides of the Si transistor. Further, the second connection points can avoid the Si transistor, thereby preventing the second connection points from affecting the installation of the Si transistor and facilitating the connection of the second connection points to the second pole of the Si transistor.

[0035] In some embodiments, the control electrode of the GaN transistor further includes two second control electrode windows, which are respectively disposed on opposite sides of the Si transistor, and the first group of second connection points and the second group of second connection points are respectively disposed on the two second control electrode windows.

[0036] Among them, a group of second connection points is disposed on one second control electrode window. At this time, the area of the second control electrode window is relatively large, and thus the number of second connection points disposed on the first control electrode window can be designed according to requirements.

[0037] In some embodiments, the two second control electrode windows are respectively disposed on both sides of the Si transistor in the third direction. The second control electrode window is strip-shaped and extends along the fourth direction, where the fourth direction intersects the third direction.

[0038] Among them, by disposing the two second control electrode windows on both sides of the Si transistor in the third direction, the width of the Si transistor in the fourth direction can be reduced. In addition, since the second control electrode window is strip-shaped, the area of the second control electrode window is relatively large at this time. Therefore, the number of second connection points disposed on the second control window and the distance between two adjacent second connection points can be designed according to requirements.

[0039] In some embodiments, the cascode amplifier further includes: a second connecting member, the second connecting member includes a connected third end and a fourth end, the third end includes a plurality of second connection ends, the plurality of second connection ends are respectively connected to the plurality of second connection points, and the fourth end is connected to the second pole of the Si transistor.

[0040] Among them, by making the third end of the second connecting member include a plurality of second connection ends and making the plurality of second connection ends be respectively connected to the plurality of second connection points, the plurality of second connection points can have electrical signals with the same voltage.

[0041] On the other hand, a power supply is provided. The power supply includes: a cascode amplifier as described in any of the above embodiments and a driving chip, and the driving chip is connected to the control pin of the substrate of the cascode amplifier.

[0042] The above power supply has the same structure and beneficial technical effects as the cascode amplifier provided in some of the above embodiments, which will not be elaborated here.

[0043] In another aspect, a server is provided. The server includes: a power supply and a motherboard as in any of the above embodiments, wherein the motherboard is connected to the power supply.

[0044] The above server has the same structure and beneficial technical effects as the power supply provided in some of the above embodiments, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present application.

[0046] Figure 1 FIG. is a schematic structural diagram of a server according to some embodiments;

[0047] Figure 2 FIG. is a schematic structural diagram of a power supply according to some embodiments;

[0048] Figure 3 FIG. is a schematic structural diagram of a cascode amplifier according to some embodiments;

[0049] Figure 4 FIG. is another schematic structural diagram of a cascode amplifier according to some embodiments;

[0050] Figure 5 FIG. is a schematic circuit diagram of a cascode amplifier according to some embodiments;

[0051] Figure 6 FIG. is a schematic structural diagram of multiple Si transistor cells in an Si transistor;

[0052] Figure 7 FIG. is a schematic structural diagram of an Si transistor according to some embodiments;

[0053] Figure 8 FIG. is another schematic structural diagram of an Si transistor according to some embodiments;

[0054] Figure 9 FIG. is yet another schematic structural diagram of an Si transistor according to some embodiments;

[0055] Figure 10Another structural schematic diagram of an Si transistor according to some embodiments;

[0056] Figure 11 A planar schematic diagram of a cascode amplifier according to some embodiments;

[0057] Figure 12 Another planar schematic diagram of a cascode amplifier according to some embodiments;

[0058] Figure 13 Yet another planar schematic diagram of a cascode amplifier according to some embodiments;

[0059] Figure 14 A structural schematic diagram of a GaN transistor according to some embodiments;

[0060] Figure 15 Another structural schematic diagram of a GaN transistor according to some embodiments;

[0061] Figure 16 Yet another structural schematic diagram of a GaN transistor according to some embodiments. Detailed implementation manners

[0062] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0063] Unless otherwise required by the context, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive meanings, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example" or "some examples", etc., are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0064] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0065] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. As used herein, "vertical" includes the described situation and situations similar to the described situation, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "vertical" includes absolute vertical and approximate vertical, and the acceptable deviation range of approximate vertical may also be within 5° deviation, for example.

[0066] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0067] Figure 1 It is a schematic structural diagram of a server according to some embodiments.

[0068] Please refer to Figure 1 , in the server 2000, there are a power supply, a motherboard, and a plurality of power components. The power components can be arranged on the motherboard or connected to the motherboard. The power supply is electrically connected to the motherboard. Thus, the power supply can supply power to the plurality of power components through the motherboard. By way of example, the power components can include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a memory, a network card, a PCIE (Peripheral Component Interconnect Express) card, and a hard disk, etc., which are not listed one by one herein.

[0069] Among them, the power supply provided by the embodiments of the present application can be applied not only to the server 2000, but also to other electronic devices, such as switches, desktop computers, laptop computers, personal digital assistants (PDAs), wireless terminal devices, communication devices, embedded devices, mobile terminals, etc. Among them, the mobile terminal can be, for example, a mobile phone, a tablet, etc., and the power supply can be a charging power supply for the mobile phone or the tablet.

[0070] In this embodiment, the number of power supplies can be one or more.

[0071] The power supply can convert a direct current (DC) signal into a DC signal required by a power element. The power supply can include an AC / DC conversion module and a voltage regulation module. The AC / DC conversion module can convert an alternating current (AC) signal into a DC signal, and the voltage regulation module can adjust the voltage of the DC signal and output the adjusted DC signal to the power element.

[0072] Among them, common devices in the voltage regulation module include a cascode amplifier.

[0073] Figure 2 It is a schematic structural diagram of a power supply according to some embodiments.

[0074] Please refer to Figure 2 , the power supply can further include a driver chip 3000, and the driver chip 3000 is electrically connected to the cascode amplifier 1000 to provide an electrical signal for the cascode amplifier 1000.

[0075] Among them, the cascode amplifier 1000 can include a control pin 500, a first pole pin 300, and a second pole pin 400. The driver chip 3000 is connected to the control pin 500. Thus, the driver chip 3000 can provide a control signal for the cascode amplifier 1000.

[0076] In addition, the power supply can further include a circuit board, and the driver chip 3000 and the cascode amplifier 1000 are disposed on the circuit board. Among them, the circuit board can be electrically connected to the first pole pin 300 and the second pole pin 400 of the cascode amplifier 1000. Thus, the circuit board can provide signals for the first pole pin 300 and the second pole pin 400.

[0077] Among them, the driver chip 3000 and the control pin 500 can be electrically connected through a wire or through a trace on the circuit board.

[0078] Figure 3 It is a schematic structural diagram of the cascode amplifier 1000 according to some embodiments, Figure 4Another structural schematic diagram of the cascode amplifier 1000 according to some embodiments. Figure 5 A circuit schematic diagram of the cascode amplifier 1000 according to some embodiments.

[0079] Please refer to Figure 3 、 Figure 4 and Figure 5 , the cascode amplifier 1000 may include a substrate 700, a GaN transistor 100, and an Si transistor 200. Among them, the GaN transistor 100 and the Si transistor 200 may be cascaded.

[0080] Among them, the substrate 700 includes a plate 710, a control pin 500, a first pole pin 300, and a second pole pin 400. The control pin 500, the first pole pin 300, and the second pole pin 400 are disposed on the plate 710.

[0081] The GaN transistor 100 is disposed on the plate 710. The GaN transistor 100 may include a first pole D1, a second pole S1, and a control pole G1. The GaN transistor 100 may further include a first surface 110. The first surface 110 faces away from the plate 710. The first pole D1, the second pole S1, and the control pole G1 of the GaN transistor 100 are disposed on the first surface 110. The first pole D1 of the GaN transistor 100 is connected to the first pole pin 300.

[0082] The Si transistor 200 includes a first pole D2, a second pole S2, and a control pole G2. Among them, the first pole D2 of the Si transistor 200 is connected to the second pole S1 of the GaN transistor 100, and the second pole S2 of the Si transistor 200 is connected to the control pole G1 of the GaN transistor 100.

[0083] Please refer to Figure 3 , the control pole G2 of the Si transistor 200 includes a plurality of first connection points 230. The control pole G2 of the Si transistor 200 is connected to the control pin 500 through the plurality of first connection points 230.

[0084] The substrate 700 can support the GaN transistor 100 and the Si transistor 200.

[0085] Please refer to Figure 3, in some examples, the GaN transistor 100 and the Si transistor 200 can be stacked. Among them, the GaN transistor 100 can be directly disposed on the substrate 700, the first surface 110 of the GaN transistor 100 faces away from the plate 710, the Si transistor 200 can be disposed on the first surface 110 of the GaN transistor 100, the Si transistor 200 can include a first outer surface 210 and a second outer surface 220 disposed opposite to each other, the first outer surface 210 faces the substrate 700 and fits with the first surface 110. At this time, the second outer surface 220 is located on the side of the first outer surface 210 away from the first surface 110. The first pole D2 of the Si transistor 200 is located on the first outer surface 210, and the second pole S2 and the control pole G2 of the Si transistor 200 are located on the second outer surface 220.

[0086] Among them, the first pole D2 of the Si transistor 200 is disposed facing the first surface 110, so that it is convenient to connect the first pole D2 of the Si transistor 200 to the second pole S1 of the GaN transistor 100 on the first surface 110. Exemplarily, the first pole D2 of the Si transistor 200 is soldered to the second pole S1 of the GaN transistor 100.

[0087] The cascode amplifier 1000 may further include a first adhesive layer. Among them, the first adhesive layer may be located between the first surface 110 of the GaN transistor 100 and the first outer surface 210 of the Si transistor 200. The first surface 110 and the first outer surface 210 can be bonded by the first adhesive layer to achieve a fixed connection between the GaN transistor 100 and the Si transistor 200.

[0088] Exemplarily, the first pole D1 of the GaN transistor 100 can be wire-bonded to the first pole pin 300, the second pole S1 of the GaN transistor 100 can be soldered to the first pole D2 of the Si transistor 200, the control pole G1 of the GaN transistor 100 can be wire-bonded to the second pole S2 of the Si transistor 200, the control pole G2 of the Si transistor 200 can be wire-bonded to the control pin 500, and the second pole S2 of the Si transistor 200 can be wire-bonded to the second pole pin 400.

[0089] Among them, by stacking the GaN transistor 100 and the Si transistor 200, the area occupied by the GaN transistor 100 and the Si transistor 200 on the substrate 700 can be reduced, and further the area of the cascode amplifier 1000 can be reduced.

[0090] Please refer to Figure 4, in some other examples, both the GaN transistor 100 and the Si transistor 200 can be disposed on the substrate 700. Among them, the first surface 110 of the GaN transistor 100 faces away from the plate 710. The Si transistor 200 may include a first outer surface 210 and a second outer surface 220 disposed opposite to each other. The first outer surface 210 faces the plate 710 and is attached to the plate 710. The first pole D2 of the Si transistor 200 is located on the first outer surface 210, and the second pole S2 and the control pole G2 of the Si transistor 200 are located on the second outer surface 220.

[0091] Exemplarily, the first pole D2 of the Si transistor 200 is connected to the first transfer pin on the plate 710. The second pole S1 of the GaN transistor 100 can be wire-bonded to the second transfer pin on the plate 710. Among them, the first pin and the second pin can be electrically connected through the trace on the plate 710, so that the first pole D2 of the Si transistor 200 can be electrically connected to the second pole S1 of the GaN transistor 100.

[0092] The first pole D1 of the GaN transistor 100 can be wire-bonded to the first pole pin 300 on the plate 710. The control pole G1 of the GaN transistor 100 is wire-bonded to the second pole pin 400 on the plate 710. The second pole S2 of the Si transistor 200 can be wire-bonded to the second pole pin 400, so that the control pole G1 of the GaN transistor 100 can be connected to the second pole S2 of the Si transistor 200, and both are connected to the second pole pin 400. The control pole G2 of the Si transistor 200 can be wire-bonded to the control pin 500.

[0093] Among them, by disposing the GaN transistor 100 and the Si transistor 200 on the plate 710, the contact between the GaN transistor 100 and the Si transistor 200 can be avoided, so that the heat transferred from the GaN transistor 100 to the Si transistor 200 can be reduced, and the risk of failure of the Si transistor 200 can be lowered.

[0094] Exemplarily, the above GaN transistor 100 can be a GaN (gallium nitride) HEMT (High Electron Mobility Transistor), and the GaN HEMT is a high-voltage depletion-type transistor. The Si transistor 200 can be a Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the Si MOSFET is a low-voltage enhancement-type transistor.

[0095] Exemplarily, the first pole D1 of the GaN transistor 100 can be the drain, the second pole S1 of the GaN transistor 100 can be the source, and the control pole G1 of the GaN transistor 100 can be the gate electrode.

[0096] Exemplarily, the first pole D2 of the Si transistor 200 can be the drain, the second pole S2 of the Si transistor 200 can be the source, and the control pole G2 of the Si transistor 200 can be the gate electrode.

[0097] Wherein, the gate G2 of the Si transistor 200 can be connected to the control pin 500, and the driving chip 3000 (as Figure 2 shown) can apply a gate voltage to the gate G2 of the Si transistor 200 through the control pin 500 to control the on / off of the Si transistor 200.

[0098] The second pole S2 of the Si transistor 200 can be connected to the second pole pin 400. Therefore, the voltage of the second pole pin 400 is equal to the voltage of the second pole S2 of the Si transistor 200. Also, since the second pole S2 of the Si transistor 200 is further connected to the gate G1 of the GaN transistor 100, the voltage of the second pole pin 400, the voltage of the second pole S2 of the Si transistor 200, and the voltage of the gate G1 of the GaN transistor 100 are equal.

[0099] When no gate voltage is applied to the gate G2 of the Si transistor 200 and the drain-source voltage is greater than zero, it operates in the forward blocking mode; when the gate voltage of the gate G2 of the Si transistor 200 is greater than the threshold voltage of the Si transistor 200, the cascode amplifier 1000 conducts forward; once the Si transistor 200 conducts reversely, the cascode amplifier 1000 will operate in the reverse conduction mode. Also, since the voltage of the first pole D2 of the Si transistor 200 is equal to the voltage of the second pole S1 of the GaN transistor 100, and the voltage of the second pole S2 of the Si transistor 200 is equal to the voltage of the gate G1 of the GaN transistor 100, the drain-source voltage of the Si transistor 200 provides a negative bias voltage for the gate-source voltage of the GaN transistor 100. Furthermore, controlling the on / off of the Si transistor 200 can control the on / off of the GaN transistor 100. In summary, the cascode amplifier 1000 can be turned off when receiving a low level at the control pin 500 and turned on when receiving a high level through the cascaded GaN transistor 100 and Si transistor 200.

[0100] Figure 6 It is a schematic structural diagram of multiple Si transistor cells 250 in the Si transistor 200.

[0101] Please refer toFigure 6 , the Si transistor 200 may include a plurality of Si transistor cells 250. The plurality of Si transistor cells 250 are arranged in an array and are in parallel. Specifically, the Si transistor cell 250 may include a first pole, a second pole 252, and a control pole 253. Among them, the first pole of the Si transistor cell 250 is close to the first outer surface 210, and the second pole 252 and the control pole 253 of the Si transistor cell 250 are close to the second outer surface 220. The first poles of the plurality of Si transistor cells 250 are connected and are connected to the first pole D2 of the Si transistor 200. The second poles of the plurality of Si transistor cells 250 are connected and are connected to the second pole S2 of the Si transistor 200. The control poles of the plurality of Si transistor cells 250 are connected and are connected to the control pole G2 of the Si transistor 200.

[0102] The control pole G2 of the Si transistor 200 may receive an electrical signal through the first connection point 230, and this electrical signal may be transmitted to the control poles of the plurality of Si transistor cells 250 through the first connection point 230, so as to control the conduction of the plurality of Si transistor cells 250. Among them, there is a voltage drop between the control poles of the plurality of Si transistor cells 250. The voltage drop between the control pole of the Si transistor cell 250 farther from the first connection point 230 and the first connection point 230 is greater. The higher the voltage of the electrical signal received by the control pole of the Si transistor cell 250, the higher the opening degree of the Si transistor cell 250, and the lower the voltage of the electrical signal received by the control pole of the Si transistor cell 250, the lower the opening degree of the Si transistor cell 250. And the lower the opening degree of the Si transistor cell 250, the greater the leakage current of the Si transistor cell 250, the more heat generated by the Si transistor cell 250, and the higher the temperature, the Si transistor cell 250 is prone to failure, resulting in the failure of the Si transistor 200, and further resulting in the failure of the cascode amplifier 1000.

[0103] In the embodiment of the present application, the control pole G2 of the Si transistor 200 includes a plurality of first connection points 230, and the voltages of the plurality of first connection points 230 are the same. The control poles of the plurality of Si transistor cells 250 can be connected to the plurality of first connection points 230. Furthermore, the voltages of the electrical signals received by the control poles of the plurality of Si transistor cells 250 are more uniform, so as to reduce the voltage drop between the control poles of the plurality of Si transistor cells 250 and the first connection point 230. In this way, the opening degree of the plurality of Si transistor cells 250 can be increased, and further the leakage current of the Si transistor cell 250 can be reduced, and the heat generated by the Si transistor cell 250 can be reduced, so as to avoid the local temperature of the Si transistor 200 being too high, and further avoid the failure of the Si transistor 200, and further improve the problem of the failure of the cascode amplifier 1000.

[0104] Exemplarily, the number of the first connection points 230 may be two, three, four, five or more.

[0105] Figure 7 It is a schematic structural diagram of an Si transistor according to some embodiments.

[0106] Please refer to Figure 7 , in some embodiments, the Si transistor 200 includes a first outer surface 210 and a second outer surface 220 arranged opposite to each other. The first outer surface 210 faces the substrate 700. The first pole D2 of the Si transistor 200 is disposed on the first outer surface 210, and the second pole S2 and the control pole G2 of the Si transistor 200 are disposed on the second outer surface 220.

[0107] Among them, a plurality of first connection points 230 are disposed on the second outer surface 220, and the plurality of first connection points 230 are arranged along the edge of the second pole S2 of the Si transistor 200.

[0108] Please refer to Figure 7 , and in combination with Figure 3 , exemplarily, the second pole S2 of the Si transistor 200 may include a second source window 261 and a third connection point 262. Among them, the third connection point 262 may be disposed on the second source window 261, and the third connection point 262 may be connected to the control pole G1 of the GaN transistor 100. For example, the second source window 261 may be a pad.

[0109] Among them, the second source window 261 is disposed on the second outer surface 220 of the Si transistor 200, and the second source window 261 is connected to the second poles of a plurality of Si transistor cells 250. Among them, the shape of the second source window 261 may be quadrilateral or circular. In the embodiments of the present application, the shape of the second source window 261 is not limited.

[0110] Among them, the edge of the second pole S2 of the Si transistor 200 may be the edge of the second source window 261. At this time, the plurality of first connection points 230 are arranged along the edge of the second source window 261.

[0111] Among them, a plurality of first connection points 230 are arranged along the edge of the second pole S2 of the Si transistor 200, which can make the distribution of the plurality of first connection points 230 on the second outer surface 220 relatively uniform, thereby reducing the maximum distance between the Si transistor cell 250 and the first connection point 230, reducing the voltage drop between the Si transistor cell 250 far from the first connection point 230 and the first connection point 230, increasing the opening degree of the Si transistor cell 250 far from the first connection point 230, reducing the heat generated by it, and further avoiding the overheating of the Si transistor cell 250, thereby reducing the risk of failure of the Si transistor cell 250 in the Si transistor 200, that is, reducing the risk of failure of the Si transistor 200.

[0112] In some examples, the second pole S2 of the Si transistor 200 can be rectangular or square, and the number of the first connection points 230 can be 4, and the 4 first connection points 230 can be respectively arranged corresponding to the corners of the second pole S2 of the Si transistor 200. In addition, the second pole S2 of the Si transistor 200 can be circular or elliptical. In the embodiments of the present application, the shape of the second pole S2 of the Si transistor 200 is not limited.

[0113] In some embodiments, the plurality of first connection points 230 are arranged at equal intervals along the edge of the second pole S2 of the Si transistor 200. Among them, "equal intervals" means that the distance between any two adjacent first connection points 230 is equal.

[0114] With such an arrangement, the distribution of the plurality of first connection points 230 on the second outer surface 220 can be made more uniform, further improving the voltage uniformity of the control electrodes of the plurality of Si transistor cells 250 and the uniformity of the opening degrees of the plurality of Si transistor cells 250, and further avoiding the overheating of the Si transistor cells 250 in a local area, thereby reducing the risk of failure of the Si transistor 200.

[0115] Figure 8 FIG. is another schematic structural diagram of the Si transistor 200 according to some embodiments.

[0116] Please refer to Figure 8 , in some embodiments, the control electrode G2 of the Si transistor 200 may further include a plurality of first control electrode windows 240, the plurality of first control electrode windows 240 are arranged on the second outer surface 220 and along the edge of the second pole S2 of the Si transistor, and at least one first connection point 230 is arranged on one first control electrode window 240.

[0117] Exemplarily, the first control electrode window 240 can be a pad.

[0118] Exemplarily, the first control gate window 240 is connected to the control gates of multiple Si transistor cells 250. Among them, one or more first connection points 230 may be provided on one first control gate window 240. In Figure 8 one example, one first connection point 230 is provided on one first control gate window 240. In other examples, multiple first connection points 230 may be provided on one first control gate window 240. In some other examples, the number of first connection points 230 provided on at least part of the first control gate windows 240 is different. For example, the Si transistor 200 further includes multiple first control gate windows 240, one first connection point 230 is provided on part of the first control gate windows 240, and multiple first connection points 230 are provided on another part of the first control gate windows 240.

[0119] The first control gate window 240 can be connected to the control gates of multiple Si transistor cells 250. Therefore, the first connection point 230 provided on the first control gate window 240 can be electrically connected to the control gate of the Si transistor cell 250.

[0120] The first control gate window 240 can provide a platform for the setting of the first connection point 230, thereby facilitating the setting of the first connection point 230 and facilitating the connection between the first connection point 230 and the control pin 500.

[0121] Figure 9 FIG. is a further structural schematic diagram of the Si transistor 200 according to some embodiments.

[0122] Please refer to Figure 9 , in some other embodiments, the control gate G2 of the Si transistor 200 may further include a first control gate window 240, the first control gate window 240 is provided on the second outer surface 220 and surrounds the second pole S2 of the Si transistor 200, and multiple first connection points 230 are provided on the first control gate window 240.

[0123] Exemplarily, the first control gate window 240 may surround the second source window 261.

[0124] In some examples, the first control gate window 240 may be annular. In other examples, an opening may also be provided on the first control gate window 240. At this time, the extension trajectory of the first control gate window 240 is not a closed figure.

[0125] Among them, by making the first control gate window 240 surround the second pole S2 of the Si transistor 200, the area of the first control gate window 240 is larger, thereby facilitating the adjustment of the position and number of the first connection points 230.

[0126] Figure 10Another structural schematic diagram of the Si transistor 200 according to some embodiments.

[0127] Please refer to Figure 10 , in some embodiments, a plurality of first connection points 230 are disposed on the second outer surface 220. The plurality of first connection points 230 are divided into a first group of first connection points 230X and a second group of first connection points 230Y. The first group of first connection points 230X and the second group of first connection points 230Y are respectively disposed on opposite sides of the second pole S2 of the Si transistor 200.

[0128] In Figure 10 , taking the first group of first connection points 230X including 3 first connection points 230 as an example, the embodiments of the present application are illustrated. Of course, the number of first connection points 230 in the first group of first connection points 230X is not limited to 3, and may also be 1, 2, 4, 5, and more.

[0129] Exemplarily, the first group of first connection points 230X and the second group of first connection points 230Y are respectively disposed on both sides of the second source window 261.

[0130] Exemplarily, the first group of first connection points 230X and the second group of first connection points 230Y are respectively disposed on both sides of the second pole S2 of the Si transistor 200 in the first direction F1, so as to reduce the width of the Si transistor 200 in the second direction F2. Wherein, the second direction F2 may intersect with the first direction F1.

[0131] Exemplarily, the arrangement direction of the plurality of first connection points 230 in the first group of first connection points 230X is the same as the arrangement direction of the plurality of first connection points 230 in the second group of first connection points 230Y. Of course, their arrangement directions may also be different.

[0132] Please refer to Figure 10 , in some embodiments, the control pole G2 of the Si transistor 200 may further include two first control pole windows 240. The two first control pole windows 240 are disposed on the second outer surface 220 and are respectively disposed on opposite sides of the second pole S2 of the Si transistor 200. The first group of first connection points 230X and the second group of first connection points 230Y are respectively disposed on the two first control pole windows 240. Wherein, a group of first connection points is disposed on one first control pole window 240. At this time, the area of the first control pole window 240 is relatively large, and thus the number and spacing of the first connection points 230 disposed on the first control pole window 240 can be designed according to requirements.

[0133] Please refer to Figure 10 , in some embodiments, the two first control pole windows 240 are respectively disposed on both sides of the second pole S2 of the Si transistor 200 in the first direction F1.

[0134] The first control gate window 240 is bar-shaped and extends along a second direction F2, where the second direction F2 intersects the first direction F1.

[0135] In some examples, when each group of first connection points includes multiple first connection points 230, the multiple first connection points 230 in a group of first connection points may be arranged in sequence along the second direction F2.

[0136] Wherein, the first control gate window 240 is designed to be bar-shaped. Therefore, the area of the first control gate window 240 is relatively large, facilitating adjusting the number of first connection points 230 provided on the first control gate window 240 and the distance between two adjacent first connection points 230 according to requirements.

[0137] In addition, by setting the first control gate window 240 to be bar-shaped and extending along the second direction F2, the space occupied by the first control gate window 240 in the first direction F1 can be reduced, facilitating reducing the size of the Si transistor 200 in the first direction F1.

[0138] Exemplarily, the second direction F2 and the first direction F1 may be perpendicularly arranged. With such an arrangement, the span of the first control gate window 240 in the first direction F1 can be reduced, which is beneficial to reducing the width of the Si transistor 200 in the first direction F1, thus facilitating the miniaturization of the Si transistor 200. Herein, the span of the first control gate window 240 in the first direction F1 refers to the distance between the two ends of the first control gate window 240 in the second direction F2 along the first direction F1.

[0139] In some examples, the extending directions of two first control gate windows 240 may be the same. Of course, the extending directions of two first control gate windows 240 may also be different.

[0140] The multiple first connection points 230 in the first group of first connection points 230X may be arranged along the second direction F2. The multiple first connection points 230 in the second group of first connection points 230Y may be arranged along the second direction F2.

[0141] Figure 11 It is a planar schematic diagram of a cascode amplifier according to some embodiments.

[0142] Please refer to Figure 11 , in some examples, the control gate G2 of the Si transistor 200 may further include a first control gate window 240. The first control gate window 240 is disposed on the second outer surface 220, the first control gate window 240 is bar-shaped, and is located on the side of the source S2 of the Si transistor 200 close to the control pin 500. Multiple first connection points 230 are disposed on the first control gate window 240.

[0143] With such a setting, the distance between the first control electrode window 240 and the control pin 500 is relatively close. When the first control electrode window 240 and the control pin 500 are connected by the first connecting member 900, the length of the first connecting member 900 can be reduced, and the parasitic capacitance and parasitic resistance of the link can be reduced.

[0144] Figure 12 Another planar schematic diagram of the cascode amplifier 1000 according to some embodiments. Figure 13 Another planar schematic diagram of the cascode amplifier 1000 according to some embodiments.

[0145] Please Figure 12 and Figure 13 and, in combination with Figure 3 In some embodiments, the cascode amplifier 1000 further includes: a first connecting member 900. The first connecting member 900 includes a first end 910 and a second end 920 that are connected. The first end 910 includes a plurality of first connection ends 911, and the plurality of first connection ends 911 are respectively connected to a plurality of first connection points 230, and the second end 920 is connected to the control pin 500.

[0146] Among them, the position in the first control electrode window 240 for connecting to the first connection end 911 can be used as the first connection point 230.

[0147] The plurality of first connection ends 911 are all connected to the second end 920. The second end 920 can obtain an electrical signal from the first control electrode window 240 and transmit it to the plurality of first connection ends 911. Therefore, the voltages of the plurality of first connection ends 911 are the same, and the plurality of first connection ends 911 are respectively connected to the plurality of first connection points 230, so that the plurality of first connection points 230 can have electrical signals with the same voltage.

[0148] In some examples, the second end 920 may include a plurality of fourth connection ends 921. The plurality of fourth connection ends 921 are all connected to the control pin 500, and the plurality of fourth connection ends 921 are respectively connected to different positions of the control pin 500. Among them, the second end 920 and the first end 910 are electrically connected. Therefore, the fourth connection end 921 and the first connection end 911 are electrically connected. For example, the plurality of first connection ends 911 and the plurality of fourth connection ends 921 are connected in one-to-one correspondence.

[0149] In some examples, the first connector 900 may include a plurality of second connection lines 930. One end of each second connection line 930 is connected to a first connection point 230, and the other end of each second connection line 930 is connected to a control pin 500. Wherein, the end of the second connection line 930 connected to the first connection point 230 may serve as the first connection end 911, and the end of the second connection line 930 connected to the control pin 500 may serve as the fourth connection end 921.

[0150] Wherein, a first connection point 230 can be connected to a control pin 500 through a second connection line 930, so that the shortest length of the second connection line 930 can be designed according to the distance between the first connection point 230 and the control pin 500, thereby reducing the parasitic inductance and parasitic resistance of the link and reducing the loss of electrical signals.

[0151] In other examples, the first connector 900 may include a first adapter board, a plurality of first jumper wires, and a second jumper wire. Wherein, one end of each of the plurality of first jumper wires is connected to the first adapter board, and the other ends of the plurality of first jumper wires are respectively connected to a plurality of first connection points 230. Wherein, the end of the first jumper wire connected to the first connection point 230 may serve as the first connection end 911. And one end of the second jumper wire is connected to the first adapter board, and the other end is connected to the control pin 500. Wherein, the end of the second jumper wire connected to the control pin 500 may serve as the second end 920. Wherein, the first jumper wire and the second jumper wire can be electrically connected through the first adapter board.

[0152] Wherein, by providing the first adapter board, a plurality of first jumper wires can converge to the first adapter board, and the second jumper wire can also be connected to the first adapter board, so that the first adapter board can fix the first jumper wire and the second jumper wire to avoid messy wiring.

[0153] In addition, in the case where the second end 920 includes a plurality of fourth connection ends, the number of second jumper wires can be multiple. At this time, one end of the second jumper wire is connected to the first adapter board, and the other end is connected to the control pin 500. Wherein, the end of the second jumper wire connected to the control pin 500 may serve as the fourth connection end 921.

[0154] Figure 14 Schematic diagram of the structure of a GaN transistor according to some embodiments.

[0155] Please refer to Figure 14 and in combination with Figure 3 , in some embodiments, when the Si transistor 200 is disposed on the first surface 110, the control electrode G1 of the GaN transistor 100 includes a plurality of second connection points 120. The plurality of second connection points 120 are disposed on the first surface and are connected to the second pole S2 of the Si transistor 200.

[0156] Among them, the GaN transistor 100 may include a plurality of GaN transistor cells, which are arranged in an array and connected in parallel. Specifically, the GaN transistor cell may include a first pole, a second pole, and a control pole. Among them, the first poles of the plurality of GaN transistor cells are connected and connected to the first pole D1 of the GaN transistor 100. The second poles of the plurality of GaN transistor cells are connected and connected to the second pole S1 of the GaN transistor 100. The control poles of the plurality of GaN transistor cells are connected and connected to the control pole G1 of the GaN transistor.

[0157] The control pole G1 of the GaN transistor 100 can receive an electrical signal through the second connection point 120, and this electrical signal can be transmitted through the second connection point 120 to the control poles of the plurality of GaN transistor cells to control the conduction of the plurality of GaN transistor cells. Among them, there is a voltage drop between the control poles of the plurality of GaN transistor cells, and the voltage drop between the control pole of the GaN transistor cell farther away from the second connection point 120 and the second connection point 120 is greater. The higher the voltage of the electrical signal received by the control pole of the GaN transistor cell, the higher the opening degree of the GaN transistor cell, and the lower the voltage of the electrical signal received by the control pole of the GaN transistor cell, the lower the opening degree of the GaN transistor cell. And the lower the opening degree of the GaN transistor cell, the greater the leakage current of the GaN transistor cell, and the more heat generated by the GaN transistor cell, resulting in a higher temperature at the position of the GaN transistor 100 corresponding to the GaN transistor cell, that is, it will cause the local temperature of the GaN transistor 100 to rise.

[0158] When the Si transistor 200 is located on the side of the GaN transistor 100 away from the substrate 700, the heat of the GaN transistor 100 can be transferred to the Si transistor 200. If the local temperature of the GaN transistor 100 is too high, the higher the temperature transferred from the GaN transistor 100 to the Si transistor 200. Due to the poor heat resistance of the Si transistor 200, it will further cause the Si transistor 200 to fail, resulting in the failure of the cascode amplifier 1000.

[0159] In an embodiment of the present application, the control electrode G1 of the GaN transistor 100 includes a plurality of second connection points 120, and the plurality of second connection points 120 are all connected to the second pole S2 of the Si transistor 200. Therefore, the voltages of the plurality of second connection points 120 are the same. By making the control electrode G1 of the GaN transistor 100 include a plurality of second connection points 120, the gate voltage at each part of the first surface 110 can be made more uniform. Furthermore, the voltages of the electrical signals received by the control electrodes of the plurality of GaN transistor cells are more uniform, thereby reducing the voltage drop between the control electrodes of the plurality of GaN transistor cells and the second connection points 120. In this way, the opening degree of the plurality of GaN transistor cells can be increased, and further the leakage current of the GaN transistor cells can be reduced, and the heat generated by the GaN transistor cells can be reduced, so that the temperature at each part of the GaN transistor 100 can be made more uniform, thereby reducing the heat transferred from the GaN transistor 100 to the Si transistor 200, and thus avoiding the local temperature of the Si transistor 200 from being too high, and further avoiding the failure of the Si transistor 200, and further improving the problem of the failure of the cascode amplifier 1000.

[0160] Figure 15 FIG. is another schematic structural diagram of the GaN transistor 100 according to some embodiments. Among them, in Figure 15 FIG., the dashed box indicated by A1 is the area on the first surface 110 for mounting the Si transistor 200.

[0161] Please refer to Figure 15 FIG., and in combination with Figure 13 FIG., in some embodiments, the plurality of second connection points 120 are arranged along the edge of the Si transistor 200. In Figure 15 FIG., taking the number of the second connection points 120 as 10 as an example, the embodiments of the present application are illustrated. The number of the second connection points 120 is not limited. For example, the number of the second connection points 120 can be 2, 3, 4, 5 or more.

[0162] Among them, the second pole S1 of the GaN transistor 100 is located within the area covered by the Si transistor 200. In the embodiments of the present application, by arranging the plurality of second connection points 120 along the edge of the Si transistor 200, the second connection points 120 can avoid the second pole S1 of the GaN transistor 100 and the Si transistor 200, thereby avoiding the second connection points 120 from affecting the installation of the Si transistor 200.

[0163] In addition, multiple second connection points 120 are arranged along the edge of the Si transistor 200, which can make the distribution of the multiple second connection points 120 on the first surface 110 relatively uniform, thereby reducing the maximum distance between the GaN transistor cells and the second connection points 120, increasing the voltage drop between the GaN transistor cells farther from the second connection points 120 and the second connection points, increasing the opening degree of the GaN transistor cells farther from the second connection points 120, thereby reducing the heat generated by the GaN transistor cells farther from the second connection points 120, and further avoiding local overheating of the GaN transistor 100. Further, the local heat received by the Si transistor 200 from the GaN transistor 100 can be reduced, thereby reducing the heat received by the Si transistor cells 250 in the local area of the Si transistor 200, further avoiding overheating of the Si transistor cells 250, and thus reducing the risk of failure of the Si transistor cells 250 in the Si transistor 200, that is, reducing the risk of failure of the Si transistor 200.

[0164] In some embodiments, the multiple second connection points 120 are arranged at equal intervals along the edge of the Si transistor 200. Herein, "equal intervals" means that the distance between any two adjacent second connection points 120 can be equal.

[0165] With such an arrangement, the distribution of the multiple second connection points 120 on the first surface 110 can be made more uniform, further improving the voltage uniformity of the control electrodes of the multiple GaN transistor cells, improving the uniformity of the opening degrees of the multiple GaN transistor cells, and further avoiding overheating of the GaN transistor cells in the local area, reducing the heat received by the Si transistor 200, and thus reducing the risk of failure of the Si transistor 200.

[0166] Please refer to Figure 15 , in some embodiments, the control electrode G1 of the GaN transistor 100 may further include multiple second control electrode windows 130. The multiple second control electrode windows 130 are arranged on the first surface 110 and along the edge of the Si transistor 200, and at least one second connection point 120 is arranged on one second control electrode window 130.

[0167] Exemplarily, the second control electrode window 130 may be a pad.

[0168] Among them, one or more second connection points 120 may be arranged on one second control electrode window 130. In Figure 15 , one second connection point 120 is arranged on one second control electrode window 130. In some other examples, please refer to Figure 3, multiple second connection points 120 may be provided on a second control electrode window 130. Additionally, in some other examples, one second connection point 120 is provided on a part of the second control electrode window 130, while multiple second connection points 120 are provided on the remaining part of the second control electrode window 130.

[0169] The second control electrode window 130 may be connected to the control electrodes of multiple GaN transistor cells. Therefore, the second connection points 120 provided on the second control electrode window 130 may be electrically connected to the control electrodes of the GaN transistor cells.

[0170] The second control electrode window 130 may provide a platform for the arrangement of the second connection points 120, facilitating the connection of the second connection points 120 to the second pole S2 of the Si transistor 200.

[0171] In some examples, the orthographic projection of the Si transistor 200 on the second outer surface 220 is approximately rectangular, and the number of the second connection points 120 may be four. The four second connection points 120 may be respectively arranged at the four corners of the rectangular projection of the Si transistor 200 on the second outer surface 220. Of course, the four second connection points 120 may also be arranged at other positions of the rectangular orthographic projection of the Si transistor 200, which will not be enumerated one by one here.

[0172] Figure 16 It is another structural schematic diagram of the GaN transistor 100 according to some embodiments.

[0173] Please refer to Figure 16 , in some other embodiments, the control electrode G1 of the GaN transistor 100 may further include a second control electrode window 130, which is provided on the first surface 110 and surrounds the Si transistor 200, and multiple second connection points 120 are provided on the second control electrode window 130.

[0174] In some examples, the second control electrode window 130 is annular.

[0175] In some other examples, an opening may be provided on the second control electrode window 130. At this time, the extending trajectory of the second control electrode window 130 may not be a closed figure.

[0176] By arranging the second control electrode window 130 to surround the Si transistor 200, the area of the second control electrode window 130 can be increased, and thus a larger platform can be provided for the arrangement of the second connection points 120, facilitating the adjustment of the positions and the number of the second connection points 120.

[0177] Please refer to Figure 3 and Figure 14, in some embodiments, the multiple second connection points 120 are divided into a first group of second connection points 120X and a second group of second connection points 120Y, and the first group of second connection points 120X and the second group of second connection points 120Y are respectively arranged on opposite sides of the Si transistor 200.

[0178] In Figure 3 and Figure 14 , taking the first group of second connection points 120X including two second connection points 120 as an example, the embodiments of the present application are illustrated. Of course, the number of second connection points 120 in the first group of second connection points 120X is not limited to two, and may also be 1, 3, 4, 5 or more.

[0179] In Figure 3 and Figure 14 , taking the second group of second connection points 120Y including two second connection points 120 as an example, the embodiments of the present application are illustrated. Of course, the number of second connection points 120 in the first group of second connection points 120X is not limited to two, and may also be 1, 3, 4, 5 or more.

[0180] Among them, the multiple second connection points 120 are divided into two groups, and the first group of second connection points 120X and the second group of second connection points 120Y are respectively arranged on both sides of the Si transistor 200. Furthermore, the second connection points 120 can avoid the Si transistor 200, thereby preventing the second connection points 120 from affecting the installation of the Si transistor 200 and facilitating the connection of the second connection points 120 to the second pole S2 of the Si transistor 200.

[0181] Exemplarily, the arrangement direction of the multiple second connection points 120 in the first group of second connection points 120X is the same as the arrangement direction of the multiple second connection points 120 in the second group of second connection points 120Y. Of course, their arrangement directions may also be different.

[0182] Please refer to Figure 3 and Figure 14 , in some embodiments, the control electrode G1 of the GaN transistor 100 may further include two second control electrode windows 130, and the two second control electrode windows 130 are respectively arranged on opposite sides of the Si transistor 200, and the first group of second connection points 120X and the second group of second connection points 120Y are respectively arranged on the two second control electrode windows 130.

[0183] Among them, a group of second connection points is arranged on one second control electrode window 130. At this time, the area of the second control electrode window 130 is relatively large, and thus the number of second connection points 120 arranged on the second control electrode window 130 can be designed according to requirements.

[0184] Please refer to Figure 14, in some embodiments, two second control gate windows 130 are respectively disposed on both sides of the Si transistor 200 in the third direction F3. The second control gate windows 130 are strip-shaped and extend along the fourth direction F4, wherein the fourth direction F4 intersects with the third direction F3.

[0185] Wherein, by disposing two second control gate windows 130 on both sides of the Si transistor 200 in the third direction F3, the width of the Si transistor 200 in the fourth direction F4 can be reduced. The second control gate windows 130 are strip-shaped. At this time, the area of the second control gate windows 130 is relatively large. Therefore, the number of second connection points 120 disposed on the second control gate windows 130 and the distance between two adjacent second connection points 120 can be designed according to requirements.

[0186] Exemplarily, the fourth direction F4 and the third direction F3 can be perpendicularly disposed. With such a setting, the span of the second control gate windows 130 in the third direction F3 can be reduced, which is beneficial to reducing the width of the GaN transistor 100 in the third direction F3, and further beneficial to the miniaturization of the GaN transistor 100. The span of the second control gate windows 130 in the third direction F3 refers to the distance between the two ends of the second control gate windows 130 in the fourth direction F4 along the third direction F3.

[0187] Exemplarily, the extending directions of the two second control gate windows 130 can be the same. Of course, the extending directions of the two second control gate windows 130 can also be different.

[0188] A plurality of second connection points 120 in the first group of second connection points 120X can be disposed along the fourth direction F4. A plurality of second connection points 120 in the second group of second connection points 120Y can be arranged in sequence along the fourth direction F4.

[0189] By setting the second control gate windows 130 to be strip-shaped and extending along the fourth direction F4, the space occupied by the plurality of second connection points 120 in the third direction F3 can be reduced, so as to facilitate reducing the size of the GaN transistor 100 in the third direction F3.

[0190] Please refer to Figure 3 , Figure 12 and Figure 13 , in some embodiments, the common source common gate amplifier 1000 may further include a second connecting member 800. The second connecting member 800 includes a connected third end 810 and a fourth end 820. The third end 810 includes a plurality of second connection ends 811, and the plurality of second connection ends 811 are respectively connected to the plurality of second connection points 120, and the fourth end 820 is connected to the second pole S2 of the Si transistor 200.

[0191] Among them, the position where the second control electrode window 130 of the GaN transistor 100 is connected to the second connection terminal 811 can serve as the second connection point 120.

[0192] Multiple second connection terminals 811 are all connected to the fourth terminal 820. Therefore, the voltages of the multiple second connection terminals 811 are the same. The second connection terminals 811 are connected to multiple second connection points 120, so that the voltages of the multiple second connection points 120 are the same.

[0193] Exemplarily, the substrate 700 may further include a second pole transfer pin. The second pole transfer pin is disposed on the board 710. The second pole transfer pin is connected to the control electrode G1 of the GaN transistor 100. In addition, the second pole transfer pin may also be connected to the second pole pin 400 through a trace on the board 710. Thus, the control electrode G1 of the GaN transistor 100 can be connected to the second pole pin 400. In addition, the control electrode G1 of the GaN transistor 100 is also connected to the second pole S2 of the Si transistor 200. Thus, the second pole S2 of the Si transistor 200 can also be connected to the second pole pin 400. For example, the second pole pin 400 may be wire-bonded to the second control electrode window 130 of the GaN transistor 100.

[0194] In some examples, the fourth terminal 820 may include multiple third connection terminals. The multiple third connection terminals are all connected to the second pole S2 of the Si transistor 200, and the multiple third connection terminals are respectively connected to different positions of the second pole S2 of the Si transistor 200.

[0195] In some examples, the second connector 800 may include multiple first connection lines 830. One end of each first connection line 830 is connected to a second connection point 120, and the other end of each first connection line 830 is connected to the second pole S2 of the Si transistor 200. Among them, the end of the first connection line 830 connected to the second connection point 120 can serve as the second connection terminal 811, and the end of the first connection line 830 connected to the second pole S2 of the Si transistor 200 can serve as the third connection terminal.

[0196] One second connection point 120 can be connected to the second pole S2 of the Si transistor 200 through a first connection line 830. Thus, the shortest length of the first connection line 830 can be designed according to the distance between the second connection point 120 and the second pole S2 of the Si transistor 200, thereby reducing the parasitic inductance and parasitic resistance of the link and reducing the loss of the electrical signal.

[0197] In some other examples, the second connector 800 may include a second adapter board, a plurality of third patch cords, and a fourth patch cord. One ends of the plurality of third patch cords are all connected to the second adapter board, and the other ends of the plurality of third patch cords are respectively connected to a plurality of second connection points 120. One end of the third patch cord connected to the second connection point 120 may serve as the second connection end 811. One end of the fourth patch cord is connected to the second adapter board, and the other end is connected to the second pole S2 of the Si transistor 200. One end of the fourth patch cord connected to the second pole S2 of the Si transistor 200 may serve as the fourth end 820. The third patch cord and the fourth patch cord may be electrically connected through the second adapter board.

[0198] Wherein, by providing the second adapter board, the plurality of third patch cords can converge to the second adapter board, and the fourth patch cord can also be connected to the second adapter board, so that the second adapter board can fix the third patch cord and the geothermal patch cord, avoiding messy wiring.

[0199] In addition, when the fourth end 820 includes a plurality of third connection ends, the number of the fourth patch cords can be multiple. At this time, one end of each fourth patch cord is connected to the second adapter board, and the other end is connected to the second pole S2 of the Si transistor 200. One end of the fourth patch cord connected to the second pole S2 of the Si transistor 200 may serve as the third connection end.

[0200] Please refer to Figure 14 , in some embodiments, the first pole D1 of the GaN transistor 100 may be located on a side of the second control pole window 130 away from the second pole S1 of the GaN transistor 100.

[0201] Exemplarily, the first pole D1 of the GaN transistor 100 may be located on a side of one second control pole window 130 away from the second pole S1 of the GaN transistor 100.

[0202] Please refer to Figure 3 , in some embodiments, the first pole D1 of the GaN transistor 100 may include a plurality of fourth connection points, and the plurality of fourth connection points are connected to the first pole pin 300.

[0203] Wherein, the plurality of fourth connection points are connected to the first poles of a plurality of GaN transistor cells, so as to improve the voltage uniformity of the first poles of the plurality of GaN transistor cells.

[0204] In some examples, the first pole D1 of the GaN transistor 100 may include a second drain window 140, and the plurality of fourth connection points are arranged in the second drain window 140.

[0205] Exemplarily, the second drain window 140 may be strip-shaped.

[0206] Exemplarily, such as Figure 14 As shown, when the two second control electrode windows 130 extend along the fourth direction F4, the second drain window 140 can extend along the fourth direction F4. At this time, the arrangement of the first electrode D1, the second control electrode window 130, and the second electrode S1 on the first surface 110 of the GaN transistor 100 is relatively regular. In addition, the width of the GaN transistor 100 in the third direction F3 can be reduced, which is beneficial to the miniaturization of the GaN transistor 100.

[0207] In some examples, the cascode amplifier 1000 may further include a third connecting member 600. One end of the third connecting member 600 is connected to a fourth connection point on the second control electrode window 130, and the other end is connected to the first electrode pin 300, so that the first electrode D1 of the GaN transistor 100 is connected to the first electrode pin 300.

[0208] Wherein, the first electrode D1 of the GaN transistor 100 may include a plurality of fourth connection points. At this time, one end of the third connecting member 600 may include a plurality of fifth connection ends, and the plurality of fifth connection ends are respectively connected to the fourth connection points, so that the third connecting member 600 is connected to the first electrode D1 of the GaN transistor 100. The other end of the third connecting member 600 may include a plurality of sixth connection ends, and the plurality of sixth connection ends are all connected to the first electrode pin 300, so that the third connecting member 600 is connected to the first electrode pin 300. Thus, the first electrode D1 of the GaN transistor 100 can be connected to the first electrode pin 300 through the third connecting member 600.

[0209] Exemplarily, the third connecting member 600 may include a plurality of third connecting lines 610. One end of the third connecting member 610 is connected to the second drain window 140 of the first electrode D1 of the GaN transistor 100, and the other end is connected to the first electrode pin 300. Wherein, one end of the third connecting line 610 connected to the third connection point can be used as a fifth connection end, and one end of the third connecting line 610 connected to the first electrode pin 300 can be used as a sixth connection end. Wherein, the position in the second drain window 140 connected to the third connecting line 610 can be used as a fourth connection point.

[0210] Wherein, by making the third connecting member 600 include a plurality of third connecting lines 610, the shortest length of the third connecting line 610 can be designed according to the distance between the first electrode D1 of the GaN transistor 100 and the first electrode pin 300. Thus, the parasitic inductance and parasitic resistance of the third connecting line 610 can be reduced, and the signal loss can be lowered.

[0211] Please refer to Figure 3 、 Figure 12 and Figure 13, in some embodiments, the substrate 700 may further include a Kelvin source pin 720, which is disposed on the board 710 and located between the second pole pin 400 and the control pin 500. The Kelvin source pin 720 is used to input a high-voltage signal, thereby avoiding interference between the signals of the second pole pin 400 and the control pin 500.

[0212] The Kelvin source pin 720 may be connected to the driving chip 3000, and the driving chip 3000 inputs a high-voltage signal to the Kelvin source pin 720.

[0213] As described above, the foregoing are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A cascode amplifier, characterized in that, Comprising: A substrate, the substrate comprising a plate, control pins, a first pole pin, and a second pole pin, the control pins, the first pole pin, and the second pole pin being disposed on the plate; A GaN transistor disposed on the plate, the GaN transistor comprising a first pole, a second pole, and a control pole, the GaN transistor comprising a first surface facing away from the plate, the first pole, the second pole, and the control pole of the GaN transistor being disposed on the first surface, and the first pole of the GaN transistor being connected to the first pole pin; An Si transistor, the Si transistor comprising a first pole, a second pole, and a control pole; the first pole of the Si transistor being connected to the second pole of the GaN transistor, and the second pole of the Si transistor being connected to the control pole of the GaN transistor; The control pole of the Si transistor comprises a plurality of first connection points, and the control pole of the Si transistor is connected to the control pins through the plurality of first connection points.

2. The cascode amplifier according to claim 1, wherein The Si transistor comprises a first outer surface and a second outer surface disposed opposite to each other, the first outer surface facing the substrate, the first pole of the Si transistor being disposed on the first outer surface, and the second pole and the control pole of the Si transistor being disposed on the second outer surface, wherein the plurality of first connection points are disposed on the second outer surface and are arranged along the edge of the second pole of the Si transistor.

3. The cascode amplifier according to claim 2, wherein The plurality of first connection points are arranged at equal intervals along the edge of the second pole of the Si transistor.

4. The cascode amplifier according to claim 2 or 3, characterized in that, The control pole of the Si transistor further comprises a plurality of first control pole windows, the plurality of first control pole windows being disposed on the second outer surface and arranged along the edge of the second pole of the Si transistor, and at least one of the first connection points being disposed on one of the first control pole windows.

5. The cascode amplifier according to claim 2 or 3, characterized in that, The control pole of the Si transistor further comprises a first control pole window, the first control pole window being disposed on the second outer surface and surrounding the second pole of the Si transistor, and the plurality of first connection points being disposed on the first control pole window.

6. The cascode amplifier according to claim 1, wherein The Si transistor comprises a first outer surface and a second outer surface disposed opposite to each other, the first outer surface facing the substrate, the first pole of the Si transistor being disposed on the first outer surface, and the second pole and the control pole of the Si transistor being disposed on the second outer surface, wherein the plurality of first connection points are disposed on the second outer surface, and the plurality of first connection points are divided into a first group of first connection points and a second group of first connection points, and the first group of first connection points and the second group of first connection points are respectively disposed on opposite sides of the second pole of the Si transistor.

7. The cascode amplifier according to claim 6, wherein The control pole of the Si transistor further comprises two first control pole windows, the two first control pole windows being disposed on the second outer surface and respectively disposed on opposite sides of the second pole of the Si transistor, and the first group of first connection points and the second group of first connection points are respectively disposed on the two first control pole windows.

8. The cascode amplifier according to claim 7, wherein The two first control gate windows are respectively disposed on two sides of the second pole of the Si transistor in the first direction; The first control gate window is strip-shaped and extends along a second direction, wherein the second direction intersects with the first direction.

9. The cascode amplifier according to any one of claims 1-8, characterized in that, Further comprising: A first connecting member, the first connecting member includes a connected first end and a second end; The first end includes a plurality of first connection ends, and the plurality of first connection ends are respectively connected to the plurality of first connection points, and the second end is connected to the control pin.

10. The cascode amplifier according to any one of claims 1-9, wherein The Si transistor is disposed on the first surface, the Si transistor includes a first outer surface and a second outer surface disposed opposite to each other, the first outer surface faces the first surface, the first pole of the Si transistor is located on the first outer surface, and the second pole and the control pole of the Si transistor are located on the second outer surface; The control pole of the GaN transistor includes a plurality of second connection points, and the plurality of second connection points are disposed on the first surface and connected to the second pole of the Si transistor.

11. A power supply, characterized in that, Comprising: The cascode amplifier according to any one of claims 1-10; A driving chip, the driving chip is connected to the control pin of the substrate of the cascode amplifier.

12. A server, characterized in that, Comprising: The power supply according to claim 11; A main board, connected to the power supply.

Images