Pulse signal phase detection circuit
Through the design of the first register circuit and the second register circuit combined with the lookup table unit, the phase difference between the pulse signal and the working clock is quickly and accurately detected, solving the problem of inaccurate phase detection of pulse signal in the prior art, and achieving stable sampling results.
Patent Information
- Application Number
- CN202311840629.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-18
AI Technical Summary
The phase detection results of existing pulse signals are inaccurate and have low detection efficiency, resulting in unstable sampling results.
The pulse signal phase detection circuit including a first register circuit, a second register circuit and a detection unit is adopted. By detecting the rising edge of the pulse signal, the working clock is registered in multiple stages, and the phase difference between the pulse signal and the working clock is quickly and accurately calculated using the lookup table unit.
Fast and accurate pulse signal phase detection is achieved, the sampling results are stabilized, and sampling uncertainty is avoided.
Smart Images
Figure CN120342365A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of signal phase detection, and particularly to a pulse signal phase detection circuit. Background Art
[0002] When synchronizing signals, the circuit receiving the synchronization pulse signal needs to ensure that the phase of the pulse signal sampled each time is fixed. However, even with the same clock source, after frequency multiplication and division operations within different circuits, the phase relationship between the working clock of the circuit receiving the synchronization pulse signal and the synchronization pulse has a certain randomness. At the same time, hardware differences also bring uncertainties. The superposition of the two leads to the uncertainty of sampling the synchronization pulse signal by the circuit receiving the synchronization pulse signal, which will cause the rising edge of the synchronization pulse signal to be close to the rising edge of the working clock signal, and the sampling result to randomly jump between 0 / 1, thus resulting in unstable sampling results. If the phase relationship between the pulse signal and the working clock can be detected quickly and accurately, phase adjustment can be performed to avoid unstable sampling results. However, the existing pulse signal phase detection results are inaccurate and the detection efficiency is low. Summary of the Invention
[0003] In view of the above analysis, the embodiments of the present invention aim to provide a pulse signal phase detection circuit to solve the problems of inaccurate existing pulse signal phase detection results and low detection efficiency.
[0004] On the one hand, the embodiments of the present invention provide a pulse signal phase detection circuit, including a first register circuit, a second register circuit, and a detection unit;
[0005] The first register circuit is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives;
[0006] The second register circuit is used to perform multi-stage registration on the working clock of the current clock domain and send the working clock and each stage registration value of the working clock to the detection unit;
[0007] The detection unit is used to obtain the phase difference between the pulse signal and the working clock according to the working clock and the multi-stage registration values of the working clock when the decision signal is valid.
[0008] Based on a further improvement of the above technical solution, the first register circuit includes three cascaded flip-flops, an inversion circuit, and an AND gate;
[0009] The data input terminal of the first flip-flop of the first register circuit receives the pulse signal; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;
[0010] The output terminal of the last flip-flop of the first register circuit is connected to the input terminal of the inversion circuit;
[0011] The clock signal input terminal of each flip-flop of the first register circuit is connected to the sampling clock of the current clock domain;
[0012] The output terminal of the penultimate flip-flop of the first register circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs a decision signal.
[0013] Based on a further improvement of the above technical solution, the second register circuit includes a plurality of cascaded flip-flops;
[0014] The data input terminal of the first flip-flop of the second register circuit is connected to the working clock of the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;
[0015] The clock signal input terminal of each flip-flop of the second register circuit is connected to the sampling clock of the current clock domain;
[0016] The working clock and the output terminal of each flip-flop of the second register circuit are connected to the input terminal of the detection unit.
[0017] Based on a further improvement of the above technical solution, the number of flip-flops in the second register circuit is set according to the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.
[0018] Based on a further improvement of the above technical solution, the detection unit is a multi-bit input and multi-bit output look-up table unit, and the working clock and each level of stored value of the working clock are used as addresses to input the look-up table unit, and the data stored at the address is output by the look-up table unit as the phase difference.
[0019] Based on a further improvement of the above technical solution, the following method is used to determine the data stored at each address of the look-up table unit:
[0020] According to the multiple frequency relationship between the sampling clock and the working clock, determine the target address when the pulse signal has a 0 phase difference from the working clock;
[0021] Calculate the corresponding target addresses at other phase differences according to the target address at the 0 phase difference;
[0022] Write the corresponding phase difference to the target address of the look-up table unit.
[0023] Based on a further improvement of the above technical solution, the following method is used to determine the target address when the pulse signal has a 0 phase difference from the working clock:
[0024] When , the values in the target address are successively 1 zero, ones, 0 zeros;
[0025] When the values in the target address are successively 3 ones, 0 zeros, and 0 ones;
[0026] where N represents the multiple of the sampling clock frequency relative to the working clock frequency.
[0027] Based on the further improvement of the above technical solution, calculating the corresponding target addresses at other phase differences according to the target address at 0 phase difference includes:
[0028] When the phase is the target address at 0 phase difference is circularly shifted left by k bits to obtain the corresponding target address;
[0029] where N represents the multiple of the sampling clock frequency relative to the working clock frequency, and 0 ≤ k < N.
[0030] Based on the further improvement of the above technical solution, the input bit number of the lookup table unit is the multiple of the sampling clock frequency relative to the working clock frequency in the current clock domain.
[0031] Based on the further improvement of the above technical solution, the output bit number of the lookup table unit is the multiple of the sampling clock frequency relative to the working clock frequency in the current clock domain plus 1.
[0032] Compared with the prior art, the pulse signal phase detection circuit provided in this embodiment detects the rising edge of the pulse signal through the first register circuit, performs multi-stage registration on the working clock through the second register circuit, and when the rising edge of the pulse signal arrives, the detection unit determines the phase difference between the pulse signal and the working clock according to the working clock and the registered value, so as to quickly and accurately obtain the phase difference between the pulse signal and the current working clock. If the rising edge of the pulse signal and the rising edge of the working clock are close, the phase of the pulse signal can be adjusted to make the sampling result more stable.
[0033] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combination schemes. Other features and advantages of the present invention will be described in the subsequent specification, and some advantages can be made obvious from the specification, or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained through the content specifically pointed out in the specification and the drawings. Description of the Drawings
[0034] The drawings are only for the purpose of showing specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;
[0035] Figure 1 It is a block diagram of the pulse signal phase detection circuit according to an embodiment of the present invention;
[0036] Figure 2 It is a circuit diagram of the first register circuit according to an embodiment of the present invention;
[0037] Figure 3 It is a circuit diagram of the second register circuit according to an embodiment of the present invention;
[0038] Figure 4 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;
[0039] Figure 5 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;
[0040] Figure 6 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;
[0041] Figure 7 It is a schematic diagram of the timing relationship according to an embodiment of the present invention. Specific embodiments
[0042] The following will specifically describe the preferred embodiments of the present invention in conjunction with the accompanying drawings, wherein the accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principle of the present invention, and are not used to limit the scope of the present invention.
[0043] A specific embodiment of the present invention discloses a pulse signal phase detection circuit, as Figure 1 shown, including a first register circuit, a second register circuit and a detection unit;
[0044] The first register circuit is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives;
[0045] The second register circuit is used to perform multi-stage registration on the working clock in the current clock domain and send the working clock and each stage registration value of the working clock to the detection unit;
[0046] The detection unit is used to obtain the phase difference between the pulse signal and the working clock according to the working clock and the multi-stage registration values of the working clock when the decision signal is valid.
[0047] During implementation, the input pulse signal comes from the same source but different clock domains. The current clock domain is the clock domain of the pulse signal phase detection circuit. The working clock in the current clock domain is obtained by dividing the sampling clock.
[0048] Compared with the prior art, the pulse signal phase detection circuit provided in this embodiment detects the rising edge of the pulse signal through the first register circuit, performs multi-stage registration on the working clock through the second register circuit, and when the rising edge of the pulse signal arrives, the detection unit determines the phase difference between the pulse signal and the working clock according to the working clock and the registered value, so as to quickly and accurately obtain the phase difference between the pulse signal and the current working clock. If the rising edge of the pulse signal is close to the rising edge of the working clock, the phase of the pulse signal can be adjusted to make the sampling result more stable.
[0049] During implementation, in order to obtain a stable pulse signal and avoid metastability, the input pulse is tapped multiple times through the first register circuit to obtain a stable rising edge of the pulse signal.
[0050] During implementation, as Figure 2 described, the first register circuit includes three cascaded flip-flops, an inversion circuit, and an AND gate;
[0051] The data input terminal of the first flip-flop of the first register circuit receives the pulse signal; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;
[0052] The output terminal of the last flip-flop of the first register circuit is connected to the input terminal of the inversion circuit;
[0053] The clock signal input terminal of each flip-flop of the first register circuit is connected to the sampling clock of the current clock domain;
[0054] The output terminal of the penultimate flip-flop of the first register circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs a decision signal.
[0055] During implementation, in order to accurately detect the state of the working clock at the rising edge moment of the pulse signal, as Figure 3 shown, the second register circuit includes multiple cascaded flip-flops;
[0056] The data input terminal of the first flip-flop of the second register circuit is connected to the working clock of the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;
[0057] The clock signal input terminal of each flip-flop of the second register circuit is connected to the sampling clock of the current clock domain;
[0058] The working clock and the output terminal of each flip-flop of the second register circuit are connected to the input terminal of the detection unit.
[0059] During implementation, the phase difference relationship between the input pulse signal and the working clock is related to the frequency multiplication relationship between the sampling clock and the working clock. Therefore, the number of flip - flops in the second register circuit is set according to the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.
[0060] For example, if the frequency of the sampling clock is 4 times that of the working clock, 3 - stage flip - flops are used; if the frequency of the sampling clock is 5 times that of the working clock, 4 - stage flip - flops are used, that is, the number of flip - flops is one less than the frequency multiplication factor.
[0061] The working clock signal and the output signal of each register in the second register circuit are both input to the detection unit. When the judgment signal is valid, the detection unit obtains the phase difference between the pulse signal and the working clock according to the values of the working clock signal and the output signals of each register in the second register circuit.
[0062] During implementation, the clock signal of the detection unit is the sampling signal in the current clock domain.
[0063] During implementation, in order to quickly obtain the phase difference, the detection unit uses a multi - bit input and multi - bit output lookup table unit. The working clock and each stage of the stored value of the working clock are used as addresses to input to the lookup table unit, and the data stored at the address is output by the lookup table unit as the phase difference.
[0064] That is, the working clock and the output terminals of each flip - flop in the second register circuit are connected to the address input terminals of the lookup table unit, and the phase difference is stored at the address of the lookup table. For example, if 3 - stage storage is used, the sequence of stored values includes 4 elements, which are the working clock value at the current moment, the first - stage stored value of the working clock (the output value of the first flip - flop), the second - stage stored value of the working clock (the output value of the second flip - flop), and the third - stage stored value of the working clock (the output value of the third flip - flop) in sequence.
[0065] During implementation, the number of input bits of the lookup table unit is the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.
[0066] Therefore, by using the working clock and each stage of the stored value of the working clock as addresses, the phase difference stored in the lookup table can be quickly read.
[0067] During implementation, the following method is used to determine the data stored at each address of the lookup table unit:
[0068] According to the frequency multiplication relationship between the sampling clock and the working clock, determine the target address when the phase difference between the pulse signal and the working clock is 0;
[0069] Calculate the corresponding target addresses for other phase differences according to the target address when the phase difference is 0;
[0070] Write the corresponding phase difference to the target address of the lookup table unit.
[0071] Since the target addresses for other phase relationships between the pulse signal and the working clock can all be calculated based on the target address when the pulse signal and the working clock are in the same phase, during implementation, first calculate the target address when the pulse signal and the working clock are in the same phase (i.e., 0 phase), and calculate the corresponding target addresses for other phase differences based on the target address at the 0 phase difference.
[0072] Since the first register circuit includes 3 stages of flip - flops, the rising edge detected is after delaying the pulse signal by three sampling periods, that is, the decision signal is the signal triggered by the pulse signal delayed by 3 sampling periods.
[0073] Therefore, the following method is used to determine the target address when the phase difference between the pulse signal and the working clock is 0:
[0074] When , the median values of the target address are successively 1 zero, ones, zeros;
[0075] When , the median values of the target address are successively 3 ones, zeros, ones;
[0076] Wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency.
[0077] The multiple of the sampling clock frequency relative to the working clock frequency is usually 4 times or more.
[0078] The high level and low level of the working clock each maintain sampling clock cycles. If that is, N = 4 or N = 5, at the decision moment, the working clock is at a low level. Since Therefore, the first - stage register value and the second - stage register value of the working clock are both 1. Since Therefore, the remaining register values are all 0. That is, the corresponding target address values are successively 1 zero, ones, zeros. When N = 4, the target address is 0110. When N = 5, the target address is 01100.
[0079] When N = 4, the timing relationship between the pulse signal, the working clock, and the multi - stage register values of the working clock is as Figure 4 shown. clk600 represents the working clock signal, clk_d1 represents the first - stage register value of the working clock, clk_d2 represents the second - stage register value of the working clock, and clk_d3 represents the third - stage register value of the working clock.
[0080] If At the judgment moment, the working clock, as well as the first-level register value and the second-level register value of the working clock, are both 1, and the subsequent register values are 0, and there are zeros, and
[0081] For example, when N = 6, the timing relationship of the pulse signal, the working clock, and the multi-level register values of the working clock is as Figure 5 shown. clk400 represents the working clock signal, clk_d1 represents the first-level register value of the working clock, clk_d2 represents the second-level register value of the working clock, clk_d3 represents the third-level register value of the working clock, clk_d4 represents the third-level register value of the working clock, and clk_d5 represents the third-level register value of the working clock. The target address is 111000.
[0082] Then, calculate the corresponding target addresses at other phase differences according to the target address at 0 phase difference, specifically including:
[0083] When the phase difference is , circularly shift the target address at 0 phase difference to the left by k bits to obtain the corresponding target address;
[0084] wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency, and 0 ≤ k < N.
[0085] Since the pulse signal is a signal sampled by the sampling clock, the phase difference between the pulse signal and the working clock includes N cases, that is, the phase difference is 0,
[0086] When N = 4, the rising edge of the working clock is after the rising edge of the pulse signal by cycles, and the timing relationship of the pulse signal, the working clock, and the multi-level register values of the working clock is as Figure 6 shown. At this time, the corresponding register value sequence is 1100. The rising edge of the working clock is after the rising edge of the pulse signal by cycles, and the timing relationship of the pulse signal, the working clock, and the multi-level register values of the working clock is as Figure 7 shown. At this time, the corresponding register value sequence is 1001.
[0087] Therefore, when the phase is , circularly shift the target address at 0 phase difference to the left by k bits to obtain the target address corresponding to the phase difference of .
[0088] Write the k value corresponding to each phase difference to the corresponding target address. For example, when N = 4, the address corresponding to the 0 phase difference is 0110. Therefore, store 0 at the 0110 address of the look-up table. The address corresponding to the phase difference is 1100. Therefore, store 1 at the 1100 address of the look-up table.
[0089] The phase difference includes N cases. Therefore, there are only N addresses storing phase difference values, while the look-up table has 2 N addresses. Therefore, other addresses can store 2 N - 1 to represent non-phase difference.
[0090] The look-up table needs to output N + 1 values. Therefore, the output bit number of the look-up table unit is the multiple of the sampling clock frequency of the current clock domain relative to the working clock frequency plus 1.
[0091] Therefore, at the decision moment, using the working clock and the data at the output end of each flip-flop of the second register circuit as the address, the corresponding phase difference can be found in the look-up table to obtain the phase difference between the pulse signal and the working clock.
[0092] After obtaining the phase difference between the pulse signal and the working clock, if the pulse signal is close to the rising edge of the working clock, to avoid unstable sampling, the phase of the pulse signal can be adjusted so that the distance between the pulse signal and the rising edge of the working clock is maximized (differing by a period), thereby making the sampling more stable.
[0093] Those skilled in the art can understand that all or part of the processes of implementing the methods of the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a disk, an optical disc, a read-only memory or a random access memory, etc.
[0094] The above is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.
Claims
1. A pulse signal phase detection circuit, characterized in that, It includes a first register circuit, a second register circuit, and a detection unit; The first register circuit is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives; The second register circuit is used to perform multi-stage registration on the working clock in the current clock domain and send the working clock and the registered value of each stage of the working clock to the detection unit; The detection unit is used to obtain the phase difference between the pulse signal and the working clock according to the working clock and the multi-stage registered values of the working clock when the decision signal is valid.
2. The pulse signal phase detection circuit according to claim 1, wherein The first register circuit includes three cascaded flip-flops, an inversion circuit, and an AND gate; The data input terminal of the first flip-flop of the first register circuit receives the pulse signal; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop; The output terminal of the last flip-flop of the first register circuit is connected to the input terminal of the inversion circuit; The clock signal input terminal of each flip-flop of the first register circuit is connected to the sampling clock in the current clock domain; The output terminal of the second-to-last flip-flop of the first register circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs the decision signal.
3. The pulse signal phase detection circuit according to claim 1, characterized in that, The second register circuit includes multiple cascaded flip-flops; The data input terminal of the first flip-flop of the second register circuit is connected to the working clock in the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop; The clock signal input terminal of each flip-flop of the second register circuit is connected to the sampling clock in the current clock domain; The working clock and the output terminal of each flip-flop of the second register circuit are connected to the input terminal of the detection unit.
4. The pulse signal phase detection circuit according to claim 1, wherein The number of flip-flops in the second register circuit is set according to the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.
5. The pulse signal phase detection circuit according to claim 1, wherein The detection unit is a multi-bit input and multi-bit output lookup table unit. The working clock and the registered value of each stage of the working clock are used as addresses to input the lookup table unit, and the data stored at the address is output by the lookup table unit as the phase difference.
6. The pulse signal phase detection circuit according to claim 5, wherein The data stored at each address of the lookup table unit is determined in the following manner: According to the multiple relationship between the sampling clock and the working clock, determine the target address when the phase difference between the pulse signal and the working clock is 0; Calculate the corresponding target addresses for other phase differences according to the target address when the phase difference is 0; Write the corresponding phase difference to the target address of the lookup table unit.
7. The pulse signal phase detection circuit according to claim 6, wherein The target address when the phase difference between the pulse signal and the working clock is 0 is determined in the following manner: When the target address has, in sequence, one 0, one 1, and one 0; When the target address has values of three 1s in sequence, several 0s, several 1s; Wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency.
8. The pulse signal phase detection circuit according to claim 6, wherein, Calculating the corresponding target addresses for other phase differences according to the target address when the phase difference is 0 includes: When the phase is , the target address at 0 phase difference is circularly left-shifted by k bits to obtain the corresponding target address; Wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency, and 0 ≤ k < N.
9. The pulse signal phase detection circuit according to claim 5, characterized in that, The input bit number of the lookup table unit is the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.
10. The pulse signal phase detection circuit according to claim 5, wherein The output bit number of the lookup table unit is the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency plus 1.