Method for manufacturing semiconductor chip

Abstract

The invention provides a manufacturing method of a semiconductor chip. The manufacturing method of the semiconductor chip comprises the following steps: providing a first carrier plate; transferring a semiconductor die onto the first carrier, wherein the semiconductor die has a surface and another surface opposite to each other; forming a filling layer on the side surface of the semiconductor crystal grain; forming a reflective layer on the semiconductor die and the side surface, the reflective layer including a first portion disposed on the surface of the semiconductor die and a second portion disposed on the filling layer; and forming a transparent conductive layer on the other surface of the semiconductor die. According to the manufacturing method of the semiconductor chip, detection can be directly carried out after the semiconductor chip is transferred.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor chip, and more particularly to a method for manufacturing a semiconductor chip that can be directly detected after the transfer of the semiconductor chip. Background Art

[0002] Electronic devices or spliced electronic devices have been widely used in different fields such as communication, display, automotive, or aviation. With the booming development of electronic devices, electronic devices are developed towards being thinner and lighter, so the requirements for the reliability or quality of electronic devices are higher. Summary of the Invention

[0003] The present disclosure provides a method for manufacturing a semiconductor chip, which can be directly detected after the transfer of the semiconductor chip to improve the transfer yield of the semiconductor chip.

[0004] According to an embodiment of the present disclosure, the method for manufacturing a semiconductor chip includes the following steps: providing a first carrier; transferring semiconductor dies onto the first carrier, wherein the semiconductor dies have surfaces opposite to each other and another surface; forming a filling layer on the side surfaces of the semiconductor dies; forming a reflective layer on the semiconductor dies and the side surfaces, wherein the reflective layer includes a first part and a second part, the first part is disposed on the surface of the semiconductor die, and the second part is disposed on the filling layer; and forming a transparent conductive layer on the another surface of the semiconductor die. Brief Description of the Drawings

[0005] The drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into the specification and constitute a part of the specification. The drawings illustrate embodiments of the present disclosure and are used in conjunction with the description to explain the principles of the present disclosure.

[0006] Figures 1A to 1D A cross-sectional schematic diagram of the method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure;

[0007] Figures 2A to 2E A cross-sectional schematic diagram of the method for manufacturing a semiconductor chip according to the second embodiment of the present disclosure;

[0008] Figures 3A to 3C A cross-sectional schematic diagram of the method for manufacturing a semiconductor chip according to the third embodiment of the present disclosure;

[0009] Figure 4 A cross-sectional schematic diagram of the semiconductor chip according to the fourth embodiment of the present disclosure;

[0010] Figure 5 A cross-sectional schematic diagram of the semiconductor chip according to the fifth embodiment of the present disclosure;

[0011] Figures 6A to 6B A cross-sectional schematic diagram of the semiconductor chip according to the sixth embodiment of the present disclosure;

[0012] Figures 7A to 7B Schematic cross-sectional view of a semiconductor chip according to the seventh embodiment of the present disclosure.

[0013] Description of reference numerals in the figures

[0014] 100, 100a, 100b, 100c, 100d, 100e, 100f: Semiconductor chips;

[0015] 110, 110a, 110b, 110f: Semiconductor dies;

[0016] 111, 111a: First-type semiconductor layers;

[0017] 112: Active layer;

[0018] 113, 113a: Second-type semiconductor layers;

[0019] 114, 1511, 1521: Surfaces;

[0020] 115: Another surface;

[0021] 116, 123: Side surfaces;

[0022] 120, 120a, 120b: Filling layers;

[0023] 121: First surface;

[0024] 122: Second surface;

[0025] 130, 130e, 130f: Reflective layers;

[0026] 131: First part;

[0027] 132, 132e, 132f: Second parts;

[0028] 140, 140e, 140f, 170: Insulating layers;

[0029] 141, 142: Openings;

[0030] 150, 150e, 150f: Electrode layers;

[0031] 151, 151c, 151d: First electrodes;

[0032] 152, 152c, 152d: Second electrodes;

[0033] 160, 160b, 160f: Transparent conductive layers;

[0034] G: Gap;

[0035] PR1: Negative photoresist;

[0036] PR2: Positive photoresist;

[0037] RL: Sacrificial layer;

[0038] S1: First carrier board;

[0039] S2: Second carrier board;

[0040] S3: Third carrier board;

[0041] S21: Substrate;

[0042] S22: Circuit layer;

[0043] Z: Direction;

[0044] θ1: Included angle. Detailed implementation

[0045] This disclosure can be understood by referring to the following detailed description and in conjunction with the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the electronic device is shown in the multiple drawings of this disclosure, and the specific elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of this disclosure.

[0046] In the following specification and claims, words such as "comprising" and "including" are open-ended words, and thus should be interpreted as meaning "including but not limited to...".

[0047] It should be understood that when an element or film layer is said to be "on" or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or layer, or there are intervening elements or film layers between the two (non-direct case). Conversely, when an element is said to be "directly" "on" another element or film layer or "directly connected to" another element or film layer, there are no intervening elements or film layers between the two.

[0048] Although terms such as "first", "second", "third", etc. can be used to describe various components, the components are not limited to these terms. These terms are only used to distinguish a single component in the specification from other components. The same terms may not be used in the claims, and instead, the components may be replaced by first, second, third, etc. according to the order of the element declarations in the claims. Therefore, in the following specification, the first component may be the second component in the claims.

[0049] In the text, terms such as "about", "approximately", "substantially", and "substantively" generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially", or "substantively" can still be implied even without specific mention of "about", "approximately", "substantially", or "substantively".

[0050] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect" and "interconnect", unless otherwise specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed therebetween. And these terms related to joining and connecting may also include cases where both structures are movable, or both structures are fixed. In addition, the term "coupled" includes any means of direct and indirect electrical connection.

[0051] In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means can be used to measure the area, width, thickness, or height of each element, or the distance or spacing between elements. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structure image of the element to be measured, and the area, width, thickness, or height of each element, or the distance or spacing between elements can be measured.

[0052] In the present disclosure, the semiconductor chip can be applied to an electronic device. The electronic device may include a display device, a light-emitting device, a backlight device, a virtual reality device, an augmented reality (AR) device, an antenna device, a sensing device, a splicing device, or any combination thereof, but not limited thereto. The display device can be a non-self-emitting display or a self-emitting display according to requirements, and can be a color display or a monochrome display according to requirements. The antenna device can be an antenna device in a liquid crystal form or an antenna device in a non-liquid crystal form. The sensing device can be a sensing device for sensing capacitance, light, heat, or ultrasonic waves. The splicing device can be a display splicing device or an antenna splicing device, but not limited thereto. The electronic components in the electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode (LED) or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but not limited thereto. The transistor may include, for example, a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate thin film transistor, but not limited thereto. The electronic device may also include, according to requirements, fluorescence materials, phosphor materials, quantum dot (QD) materials, or other suitable materials, but not limited thereto. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, the wearable device (such as including an augmented reality or virtual reality device), the vehicle-mounted device (such as including a car windshield), or the splicing device. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The following will illustrate the content of the present disclosure with the semiconductor chip in the electronic device, but the present disclosure is not limited thereto.

[0053] It should be noted that in the following embodiments, without departing from the spirit of the present disclosure, the features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily mixed and matched.

[0054] Now, reference will be made in detail to the exemplary embodiments of the present disclosure. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0055] Figures 1A to 1D A cross-sectional schematic view of a method for manufacturing a semiconductor chip according to the first embodiment of the present disclosure. Among them, the method for manufacturing the semiconductor chip 100 of this embodiment may include the following steps:

[0056] First, please refer to Figure 1A , provide a first carrier S1; then, form a sacrificial layer RL on the first carrier S1; then, transfer the semiconductor die 110 to the first carrier S1.

[0057] Specifically, in this embodiment, the first carrier S1 may include a rigid substrate, a flexible substrate, or a combination of the foregoing. For example, the material of the first carrier S1 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), epoxy resin, other suitable carrier materials, or a combination of the foregoing, but is not limited thereto.

[0058] The sacrificial layer RL is disposed between the semiconductor die 110 and the first carrier S1, and the sacrificial layer RL can be removed together with the first carrier S1 in subsequent steps. In this embodiment, the material of the sacrificial layer RL may include an adhesive material that loses its adhesion characteristics when heated or irradiated with ultraviolet light, or a material that is easily removed, such as silicon nitride or silicon oxide, but is not limited thereto.

[0059] The semiconductor die 110 can be a vertical type chip. In the direction Z (e.g., the normal direction of the first carrier S1), the semiconductor die 110 sequentially includes a first-type semiconductor layer 111, an active layer 112, and a second-type semiconductor layer 113 from bottom to top. The first-type semiconductor layer 111 is closer to the first carrier S1 than the second-type semiconductor layer 113, and the active layer 112 is disposed between the first-type semiconductor layer 111 and the second-type semiconductor layer 113. The semiconductor die 110 has a surface 114, another surface 115, and a side surface 116. The surface 114 and the another surface 115 are opposite to each other. The surface 114 is closer to the first carrier S1 than the another surface 115, and the side surface 116 connects the surface 114 and the another surface 115. In this embodiment, the semiconductor die 110 can be a light-emitting element (such as an organic light-emitting diode, a submillimeter light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode, but not limited thereto), but not limited thereto. In this embodiment, the first-type semiconductor layer 111 can be a P-type semiconductor layer, and the second-type semiconductor layer 113 can be an N-type semiconductor layer, but not limited thereto. In some embodiments, the first-type semiconductor layer can also be an N-type semiconductor layer, and the second-type semiconductor layer can also be a P-type semiconductor layer. In this embodiment, the active layer 112 can be a light-emitting layer, but not limited thereto.

[0060] Then, please refer to Figure 1B , a negative photoresist PR1 is formed on the sacrificial layer RL; then, a filling layer 120 is formed on the side surface 116 of the semiconductor die 110 and the sacrificial layer RL exposed by the negative photoresist PR1; then, the negative photoresist PR1 is removed.

[0061] Specifically, before forming the filling layer 120, the negative photoresist PR1 can expose the semiconductor die 110 and a part of the sacrificial layer RL, and there is a gap G between the negative photoresist PR1 and the semiconductor die 110. The shape of the negative photoresist PR1 can be an inverted trapezoid. In this embodiment, the material of the negative photoresist PR1 can include acrylic, epoxy, siloxane, silica, but not limited thereto.

[0062] The filling layer 120 can surround and contact the side surface 116 of the semiconductor die 110. The filling layer 120 can include a first surface 121, a second surface 122, and a side surface 123. The first surface 121 is opposite to the second surface 122, and the first surface 121 is closer to the first carrier plate S1 than the second surface 122. The side surface 123 is located between the first surface 121 and the second surface 122, and the side surface 123 connects the first surface 121 and the second surface 122. In this embodiment, the included angle θ1 between the first surface 121 and the side surface 123 has an angle (taper angle). The angle of the included angle θ1 can be from 10 degrees to 80 degrees, or from 30 degrees to 70 degrees, for concentrating the light output of the semiconductor die 110, reducing the light output angle of the semiconductor die 110, or improving the light output efficiency of the semiconductor die 110, but not limited thereto. In this embodiment, the material of the filling layer 120 can include acrylic, epoxy alkane, siloxane, silica, other transparent filling materials, or a combination of the foregoing, but not limited thereto.

[0063] Then, please refer to Figure 1C , a reflective layer 130 is formed on the side surface 123 of the semiconductor die 110 and the filling layer 120; then, an insulating layer 140 is formed on the reflective layer 130; then, an electrode layer 150 is formed on the reflective layer 130.

[0064] Specifically, the reflective layer 130 includes a first portion 131 and a second portion 132. The first portion 131 is disposed on the other surface 115 of the semiconductor die 110. The first portion 131 can contact and be electrically connected to the second-type semiconductor layer 113 of the semiconductor die 110. The second portion 132 is disposed on the filling layer 120. The second portion 132 is disposed on the side surface 123 and the second surface 122 of the filling layer 120. The second portion 132 and the first portion 131 are separated from each other. In this embodiment, the material of the reflective layer 130 can include a material with high reflection characteristics for concentrating the light output of the semiconductor die 110, reducing the light output angle of the semiconductor die 110, or improving the light output efficiency of the semiconductor die 110.

[0065] The insulating layer 140 surrounds the reflective layer 130, and the insulating layer 140 can separate the first portion 131 and the second portion 132 of the reflective layer 130. The insulating layer 140 has an opening 141 and an opening 142. The opening 141 can expose a part of the first portion 131, and the opening 142 can expose a part of the second portion 132. In this embodiment, the material of the insulating layer 140 can include acrylic, epoxy alkane, siloxane, silica, silicon nitride, silicon oxynitride, other suitable insulating materials, or a combination of the foregoing, but not limited thereto.

[0066] The electrode layer 150 includes a first electrode 151 and a second electrode 152. The first electrode 151 and the second electrode 152 are separated from each other. The first electrode 151 is disposed on the insulating layer 140 and within the opening 141 of the insulating layer 140, and the first electrode 151 can be connected to the first portion 131. The second electrode 152 is disposed on the insulating layer 140 and within the opening 142 of the insulating layer 140, and the second electrode 152 can be connected to the second portion 132. In this embodiment, the material of the electrode layer 150 may include gold, tin, copper, other suitable electrode materials, or a combination of the foregoing, but is not limited thereto. In this embodiment, the first electrode 151 may be an N-type electrode, and the second electrode 152 may be a P-type electrode, but is not limited thereto. In some embodiments, the first electrode may also be a P-type electrode, and the second electrode may also be an N-type electrode. Herein, the N-type electrode means an electrode electrically connected to the N-type semiconductor layer, and the P-type electrode means an electrode electrically connected to the P-type semiconductor layer.

[0067] Then, please refer to Figure 1D , attach the second carrier substrate S2 to the electrode layer 150; then, turn it over, remove the first carrier substrate S1 to transfer the semiconductor die 110 from the first carrier substrate S1 to the second carrier substrate S2; then, form a transparent conductive layer 160 on the surface 114 of the semiconductor die 110.

[0068] Specifically, the second carrier substrate S2 includes a substrate S21 and a circuit layer S22. The circuit layer S22 is disposed between the substrate S21 and the electrode layer 150. The circuit layer S22 may include metal traces (not shown), and the circuit layer S22 can be used to drive the semiconductor die 110. In this embodiment, the substrate S21 may include a rigid substrate, a flexible substrate, or a combination of the foregoing. For example, the material of the substrate S21 may include glass, quartz, sapphire, ceramics, polycarbonate, polyimide, polyethylene terephthalate, other suitable substrate materials, or a combination of the foregoing, but is not limited thereto.

[0069] In this embodiment, for example, by applying a laser to the sacrificial layer RL, the sacrificial layer RL can be separated from the semiconductor die 110 to remove the sacrificial layer RL and the first carrier substrate S1.

[0070] The transparent conductive layer 160 is disposed on the surface 114 of the semiconductor die 110 and on the first surface 121 of the filling layer 120. The transparent conductive layer 160 can be connected to the second portion 132 of the reflective layer 130, and the transparent conductive layer 160 can contact and electrically connect to the first-type semiconductor layer 111 of the semiconductor die 110. Thereby, the first-type semiconductor layer 111 of the semiconductor die 110 can be electrically connected to the second electrode 152 through the transparent conductive layer 160 and the second portion 132. In this embodiment, the material of the transparent conductive layer 160 can include transparent conductive oxides (TCOs), graphene, or metals, but is not limited thereto. The material of the transparent conductive oxide can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), or a combination of the foregoing, but is not limited thereto. The metal can include a thin metal or a metal grid. For example, a very thin metal layer (such as a magnesium layer or a silver layer) can be formed, or a metal grid layer with light-transmitting openings can be formed by screen printing or other patterning processes.

[0071] In this embodiment, the step of forming the transparent conductive layer 160 can be after the step of forming the reflective layer 130, but is not limited thereto. In some embodiments, the step of forming the transparent conductive layer 160 can also be before the step of forming the reflective layer 130.

[0072] Thus far, the semiconductor chip 100 of this embodiment has been substantially manufactured.

[0073] In this embodiment, since the first-type semiconductor layer 111 and the second-type semiconductor layer 113 of the vertical semiconductor die 110 can be electrically connected to the second electrode 152 and the first electrode 151 respectively, and the second electrode 152 and the first electrode 151 can be disposed on the same side of the semiconductor chip 100, the semiconductor chip 100 can be directly detected or process monitored after being transferred to the second carrier S2, thereby improving the transfer yield.

[0074] In this embodiment, since the semiconductor chip 100 can be a vertical embedded flip-chip (VEFC), the semiconductor chip 100 can be directly detected or process monitored after being transferred to the second carrier S2, thereby improving the transfer yield.

[0075] Other embodiments will be listed below for illustration. It must be noted here that the following embodiments follow the component numbers and some content of the foregoing embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the following embodiments will not repeat it.

[0076] Figures 2A to 2E It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor chip according to a second embodiment of the present disclosure. Figures 2A to 2E The second embodiment shown and Figures 1A to 1D The first embodiment shown is similar. Therefore, the same or similar components can be made of the same materials or by the same methods. Therefore, the same and similar descriptions of the two embodiments will not be repeated below, and the differences between the two embodiments will be mainly described.

[0077] The method for manufacturing the semiconductor chip 100a of this embodiment may include the following steps:

[0078] First, please refer to Figure 2A , provide a first carrier S1; then, form a sacrificial layer RL on the first carrier S1; then, transfer the semiconductor die 110a to the first carrier S1. In this embodiment, in the Z direction (for example, the normal direction of the first carrier S1), the semiconductor die 110a sequentially includes a second-type semiconductor layer 113a, an active layer 112, and a first-type semiconductor layer 111a from bottom to top. The second-type semiconductor layer 113a is closer to the first carrier S1 than the first-type semiconductor layer 111a, and the active layer 112 is disposed between the first-type semiconductor layer 111a and the second-type semiconductor layer 113a.

[0079] Then, please refer to Figure 2B , form a positive photoresist PR2 on the sacrificial layer RL; then, form a filling layer 120a on the side surface 116 of the semiconductor die 110a and on the sacrificial layer RL exposed by the positive photoresist PR2; then, form a transparent conductive layer 160 on the surface 114 of the semiconductor die 110a and on the first surface 121 of the filling layer 120a. In this embodiment, the shape of the positive photoresist PR2 can be a positive trapezoid, and the material of the positive photoresist PR2 may include acrylic, epoxy, siloxane, silica, but is not limited thereto. In this embodiment, the second surface 122 of the filling layer 120a is closer to the first carrier S1 than the first surface 121.

[0080] Then, please refer to Figure 2C, bond the third carrier S3 onto the transparent conductive layer 160; then, turn it over, and remove the first carrier S1; then, remove the positive photoresist PR2.

[0081] Then, please refer to Figure 2D , form a reflective layer 130 on the other surface 115 of the semiconductor die 110a, on the side surface 123 of the filling layer 120a, and on the second surface 122 of the filling layer 120a; then, form an insulating layer 140 on the reflective layer 130; then, form the first electrode 151 and the second electrode 152 of the electrode layer 150 on the reflective layer 130.

[0082] Then, please refer to Figure 2E , bond the second carrier S2 to the electrode layer 150; then, turn it over and remove the third carrier S3 to transfer the semiconductor die 110a from the third carrier S3 to the second carrier S2.

[0083] So far, the semiconductor chip 100a of this embodiment has been substantially manufactured.

[0084] Figures 3A to 3C It is a cross-sectional schematic diagram of the manufacturing method of the semiconductor chip according to the third embodiment of the present disclosure. Figures 3A to 3C The third embodiment shown is similar to Figures 1A to 1D the first embodiment shown. Therefore, the same or similar components are made of the same materials or by the same methods. Thus, the same and similar descriptions of the two embodiments will not be repeated below, and the differences between the two embodiments will be mainly described.

[0085] The manufacturing method of the semiconductor chip 100b of this embodiment may include the following steps:

[0086] First, please refer to Figure 3A , in a similar Figure 1A step, after providing the first carrier S1 and forming the sacrificial layer RL on the first carrier S1, transfer the semiconductor die 110b to the first carrier S1 and partially embed the semiconductor die 110b in the sacrificial layer RL. Then, omit Figure 1B the step of using the negative photoresist in

[0087] and directly perform a patterning process after setting the filling layer 120b on the side surface 116 of the semiconductor die 110b. Figure 3B Then, please refer to

[0088] Then, please refer to Figure 3C , attach the second carrier S2 to the electrode layer 150; then, turn it over up and down, remove the first carrier S1, so as to transfer the semiconductor die 110b from the first carrier S1 to the second carrier S2; then, before the step of forming the transparent conductive layer 160b, form an insulating layer 170 on the side surface 116 of the semiconductor die 110b where the filling layer 120b is not formed; then, after the step of forming the insulating layer 170, form the transparent conductive layer 160b on the insulating layer 170, and connect the transparent conductive layer 160b to the second part 132 of the reflective layer 130. In this embodiment, the insulating layer 170 may be a single-layer structure or a multi-layer structure, and the material of the insulating layer 170 may include organic materials, inorganic materials, or a combination of the foregoing, but is not limited thereto.

[0089] Thus, the semiconductor chip 100b of this embodiment is substantially manufactured.

[0090] Figure 4 It is a cross-sectional schematic diagram of the semiconductor chip according to the fourth embodiment of the present disclosure. Please also refer to Figure 4 and Figure 1C , the semiconductor chip 100c of this embodiment is similar to the semiconductor chip Figure 1C , except that the difference between the two is that in the semiconductor chip 100c of this embodiment, in the direction Z (for example, the normal direction of the first carrier S1), the first electrode 151c may be higher than the second electrode 152c.

[0091] Specifically, please refer to Figure 4 , in the direction Z, the other surface 115 of the semiconductor die 110 is higher than the second surface 122 of the filling layer 120, and the first part 131 of the reflective layer 130 is higher than the second part 132.

[0092] The first electrode 151c has a surface 1511 facing away from the semiconductor die 110, and the second electrode 152c has a surface 1521 facing away from the semiconductor die 110. In the direction Z, the height difference H between the first electrode 151c and the second electrode 152c may be greater than 0 and less than or equal to 1 micrometer (μm) (i.e., 0 < H ≤ 1 μm), but is not limited thereto. Wherein, the height difference H is, for example, the minimum distance measured along the direction Z between the surface 1511 of the first electrode 151c and the surface 1521 of the second electrode 152c.

[0093] Figure 5 It is a cross-sectional schematic diagram of the semiconductor chip according to the fifth embodiment of the present disclosure. Please also refer to Figure 5 and Figure 4 , the semiconductor chip 100d of this embodiment is similar to Figure 4Similar to the semiconductor chip 100c, the difference between the two is that in the semiconductor chip 100d of this embodiment, the first electrode 151d and the second electrode 152d are formed by different steps, so that the first electrode 151d and the second electrode 152d can be substantially at the same height in the direction Z (for example, the normal direction of the first carrier plate S1).

[0094] Figures 6A to 6B It is a cross-sectional schematic diagram of the semiconductor chip of the sixth embodiment of the present disclosure. Figures 6A to 6B For continuity Figure 1B And replace Figures 1C to 1D The steps of. Figures 6A to 6B The sixth embodiment of Figures 1A to 1D The same or similar components in the embodiment of

[0095] The manufacturing method of the semiconductor chip 100e of this embodiment may include the following steps:

[0096] First, please refer to Figure 6A , after forming Figure 1B The structure of, form the first part 131 of the reflective layer 130e on the other surface 115 of the semiconductor die 110, and form the second part 132e of the reflective layer 130e on the side surface 123 of the filling layer 120; then, form the insulating layer 140e on the reflective layer 130e, wherein the insulating layer 140e has an opening 141 that exposes a part of the first part 131; then, form the first electrode 151 of the electrode layer 150e on the insulating layer 140e and within the opening 141 of the insulating layer 140e.

[0097] Then, please refer to Figure 6B , attach the second carrier plate S2 to the electrode layer 150e; then, turn it over up and down, remove the first carrier plate S1, so as to transfer the semiconductor die 110 from the first carrier plate S1 to the second carrier plate S2; then, form the transparent conductive layer 160 on the surface 114 of the semiconductor die 110.

[0098] So far, the semiconductor chip 100e of this embodiment has been substantially manufactured. Among them, the semiconductor chip 100e of this embodiment can be regarded as a vertical embedded chip (VEC), but is not limited thereto.

[0099] Figures 7A to 7B It is a cross-sectional schematic diagram of the semiconductor chip of the seventh embodiment of the present disclosure. Figures 7A to 7B The seventh embodiment shown in Figures 6A to 6BSimilar to the sixth embodiment shown, the same or similar components are made using the same materials or methods. Therefore, the descriptions of the same and similar parts in the two embodiments will not be repeated below, and the differences between the two embodiments will be mainly described.

[0100] The manufacturing method of the semiconductor chip 100f in this embodiment may include the following steps:

[0101] First, please refer to Figure 7A , the semiconductor die 110f of this embodiment can be partially embedded in the sacrificial layer RL; then, in a similar Figure 6A step, a first part 131 of the reflective layer 130f is formed on the other surface 115 of the semiconductor die 110f, and a second part 132f of the reflective layer 130f is formed on the side surface 123 of the filling layer 120; then, an insulating layer 140f is formed on the reflective layer 130f, where the insulating layer 140f has an opening 141 that exposes a part of the first part 131; then, a first electrode 151 of the electrode layer 150f is formed on the insulating layer 140f and within the opening 141 of the insulating layer 140f.

[0102] Then, please refer to Figure 7B , the second carrier plate S2 is bonded to the electrode layer 150f; then, it is turned over up and down, and the first carrier plate S1 is removed to transfer the semiconductor die 110f from the first carrier plate S1 to the second carrier plate S2; then, before the step of forming the transparent conductive layer 160f, an insulating layer 170 is formed on the side surface 116 of the semiconductor die 110f where the filling layer 120 is not formed; then, after the step of forming the insulating layer 170, a transparent conductive layer 160f is formed on the insulating layer 170, and the transparent conductive layer 160f is connected to the second part 132 of the reflective layer 130f. In this embodiment, the insulating layer 170 can be a single-layer structure or a multi-layer structure, and the material of the insulating layer 170 may include organic materials, inorganic materials, or a combination of the foregoing, but is not limited thereto.

[0103] So far, the semiconductor chip 100f of this embodiment has been roughly manufactured.

[0104] In summary, in the manufacturing method of the semiconductor chip in the embodiments of this disclosure, since the first-type semiconductor layer and the second-type semiconductor layer of the vertical semiconductor die can be electrically connected to the second electrode and the first electrode respectively, and the second electrode and the first electrode can be disposed on the same side of the semiconductor chip, the semiconductor chip in the electronic device can be directly detected or process monitored after being transferred to the first circuit layer, thereby improving the transfer yield.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limiting them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A manufacturing method of a semiconductor chip, characterized in that, Comprising: Providing a first carrier substrate; Transferring a semiconductor die onto the first carrier substrate, wherein the semiconductor die has a surface opposite to each other and another surface; Forming a filling layer on a side surface of the semiconductor die; Forming a reflective layer on the semiconductor die and the side surface, wherein the reflective layer comprises: A first portion disposed on the another surface of the semiconductor die; and A second portion disposed on the filling layer; and Forming a transparent conductive layer on the surface of the semiconductor die.

2. The manufacturing method according to claim 1, characterized in that, The transparent conductive layer connects to the second portion of the reflective layer.

3. The manufacturing method according to claim 1, wherein Further comprising: Transferring the semiconductor die from the first carrier substrate to a second carrier substrate.

4. The manufacturing method according to claim 1, wherein, Further comprising: Forming an electrode layer on the reflective layer, wherein the electrode layer comprises a first electrode connected to the first portion.

5. The manufacturing method according to claim 4, wherein The filling layer comprises a first surface, a second surface and a side surface, the side surface is located between the first surface and the second surface, and the second portion is disposed on the side surface and the second surface of the filling layer.

6. The manufacturing method according to claim 5, characterized in that, The electrode layer further comprises a second electrode connected to the second portion.

7. The manufacturing method according to claim 4, characterized in that, The filling layer comprises a first surface, a second surface and a side surface, the side surface is located between the first surface and the second surface, and the second portion is disposed on the side surface of the filling layer.

8. The manufacturing method according to claim 1, characterized in that, Further comprising: Forming a sacrificial layer on the first carrier substrate; And Partially embedding the semiconductor die into the sacrificial layer.

9. The manufacturing method according to claim 8, characterized in that Further comprising: Before the step of forming the transparent conductive layer, forming an insulating layer on the side surface of the semiconductor die where the filling layer is not formed.

10. The manufacturing method according to claim 9, characterized in that, Further comprising: After the step of forming the insulating layer, forming the transparent conductive layer on the insulating layer and connecting the transparent conductive layer to the second portion of the reflective layer.

11. The manufacturing method according to claim 1, characterized in that, The step of forming the transparent conductive layer is after the step of forming the reflective layer.

12. The manufacturing method according to claim 1, characterized in that, The step of forming the transparent conductive layer is before the step of forming the reflective layer.

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