Buffer insertion method and storage medium

Abstract

The invention relates to the technical field of semiconductor chips, in particular to a buffer insertion method and a storage medium. The method comprises the following steps: acquiring position information of a fan-out point and all corresponding fan-in points of the integrated circuit, and calculating a Manhattan distance between the fan-out point and each fan-in point based on the position information; calculating a corresponding first delay between the fan-out point and the fan-in point when the buffer is not placed and a corresponding second delay after the buffer is placed based on a nonlinear model; obtaining a corresponding buffer insertion candidate position based on the first delay, the second delay and the Manhattan distance between the corresponding fan-out point and the fan-in point; and carrying out calculation by taking the buffer insertion candidate position as a candidate point of a Van Ginneken algorithm to obtain a buffer placement scheme. The problems of inaccurate long conductive path delay estimation and inaccurate calculation of a buffer insertion scheme are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and particularly to a buffer insertion method and a storage medium.

Background Art

[0002] With the continuous improvement of the integrated circuit process technology, under advanced process technologies, the proportion of the interconnect delay has increased significantly. In order to ensure that the chip can achieve the purpose of timing convergence, optimizing the interconnect delay is the key point.

[0003] Currently, the commonly used effective means to optimize the interconnect delay is to insert buffers, which can not only shunt excessive loads on the network but also directly reduce the wire delay of the wires.

[0004] There are many buffer insertion methods. The most commonly used one is the Van Ginneken method. Specifically, the Steiner nodes under a given Steiner tree topology are used as the candidate positions for inserting buffers. However, when the side lengths of the given Steiner tree are too long, the Van Ginneken algorithm will give a buffer placement scheme with high delay; while the method proposed by C. Alpert et al. for calculating the splitting method of the edges of a given Steiner tree based on a linear logic gate delay model requires analyzing and calculating the lengths for splitting the edges for different edges of the Steiner tree and different types of buffers in the technology library respectively, and the method of adjusting the capacitance and resistance distribution of the Steiner tree based on the calculation results is too simple, and the linear delay model does not accurately estimate the delay under sub-micron processes and is not applicable to the actual capacitance and resistance distribution in advanced processes.

Summary of the Invention

[0005] In order to solve the problems of inaccurate estimation of long wire delays and inaccurate calculation of buffer insertion schemes in the prior art, the present invention provides a buffer insertion method and a storage medium.

[0006] The present invention provides the following technical solutions to solve the above technical problems: A buffer insertion method, the method comprising: obtaining the position information of the fan-out points and all corresponding fan-in points of the integrated circuit, calculating the Manhattan distance between the fan-out point and each of the fan-in points based on the position information; calculating a first delay corresponding to the case where no buffer is placed between the fan-out point and the fan-in point and a second delay corresponding to the case where a buffer is placed based on a non-linear model; obtaining corresponding buffer insertion candidate positions based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and the fan-in point;

[0007] Using the buffer insertion candidate positions as the candidate points of the Van Ginneken algorithm for calculation to obtain a buffer placement scheme.

[0008] Preferably, calculating the first delay corresponding to the case where no buffer is placed between the fan-out point and the fan-in point, and the second delay corresponding to the case after the buffer is placed based on a non-linear model includes: obtaining a conductive path corresponding to the fan-out point and the fan-in point whose Manhattan distance is greater than a preset length; obtaining capacitance and resistance information of the conductive path; based on the Manhattan distance and the capacitance and resistance information between the fan-out point and the fan-in point corresponding to the conductive path, calculating the first delay and the second delay of the conductive path by using a non-linear model.

[0009] Preferably, the second delay is the conductive path delay corresponding to uniformly placing i buffers on the corresponding conductive path, where i is a positive integer and i≥1.

[0010] Preferably, obtaining a candidate buffer insertion position corresponding to the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and the fan-in point includes: obtaining the optimal number of buffer insertions corresponding to the conductive path based on the first delay and the second delay of the conductive path; obtaining the optimal segmentation distance based on the Manhattan distance and the optimal number of buffer insertions between the fan-out point and the fan-in point corresponding to all the conductive paths; finding the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and performing a segmentation process on it to obtain a candidate buffer insertion position.

[0011] Preferably, obtaining the optimal number of buffer insertions corresponding to the conductive path based on the first delay and the second delay of the conductive path includes: comparing the magnitudes of the first delay and the second delay; if the second delay is less than the first delay, then making the first delay equal to the second delay, and making i = i + 1, recalculating the second delay based on i, and comparing the magnitudes of the two again until the second delay is greater than or equal to the first delay, then the current number of buffer insertions is the optimal number of buffer insertions corresponding to the current conductive path.

[0012] Preferably, obtaining the optimal segmentation distance based on the Manhattan distance and the optimal number of buffer insertions between the fan-out point and the fan-in point corresponding to all the conductive paths includes: obtaining the Manhattan distance and the optimal number of buffer insertions between the fan-out point and the fan-in point corresponding to all the conductive paths; calculating the initial segmentation distance corresponding to all the conductive paths based on the Manhattan distance and the optimal number of buffer insertions between the fan-out point and the fan-in point corresponding to all the conductive paths to obtain an initial segmentation set; selecting the smallest initial segmentation distance in the initial segmentation set as the optimal segmentation distance.

[0013] Preferably, finding the path to be split formed by the fan-out point and the fan-in point based on the optimal split distance and performing split processing on the path includes: screening the conductive paths formed by the fan-out point and each fan-in point based on the optimal split distance to obtain the path to be split; equally dividing the path to be split until its length is less than the optimal split distance.

[0014] Preferably, the screening process includes: comparing the distance of the conductive path formed by the fan-out point and the fan-in point with the optimal split distance; if the distance of the conductive path formed by the fan-out point and the fan-in point is greater than the optimal split distance, the corresponding conductive path is the path to be split; otherwise, it is a non-path to be split.

[0015] Preferably, calculating the buffer placement scheme with the candidate position for buffer insertion as the candidate point of the Van Ginneken algorithm includes: obtaining the candidate positions for buffer insertion of all the conductive paths to obtain a set of candidate positions; updating the capacitance and resistance information of the corresponding conductive paths based on the set of candidate positions; and solving the buffer placement scheme using the Van Ginneken algorithm based on the set of candidate positions and the capacitance and resistance information of the conductive paths.

[0016] To solve the above technical problems, the present invention provides another technical solution as follows: A storage medium stores a computer program thereon, and when the computer program is executed by a processor, it implements the buffer insertion method described in any one of the above.

[0017] Compared with the prior art, a buffer insertion method and a storage medium provided by the present invention have the following beneficial effects:

[0018] 1. A buffer insertion method provided by an embodiment of the present invention includes: obtaining the position information of the fan-out point of the integrated circuit and all corresponding fan-in points, calculating the Manhattan distance between the fan-out point and each fan-in point based on the position information; calculating the first delay corresponding to the fan-out point and the fan-in point without inserting a buffer and the second delay corresponding thereto after inserting a buffer based on a non-linear model, and the delay estimated using the non-linear model is more accurate than the traditional linear model; obtaining the corresponding candidate positions for buffer insertion based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and fan-in point to expand the range of buffer insertion positions and weaken the influence of long conductive paths on the buffer placement scheme; calculating the buffer placement scheme with the candidate position for buffer insertion as the candidate point of the Van Ginneken algorithm. By inserting a new node into the conductive path as the candidate point of the Van Ginneken algorithm, a buffer placement scheme with high delay is avoided when calculating the buffer placement scheme using the Van Ginneken algorithm.

[0019] 2. The embodiments of the present invention calculate the first delay corresponding to the case where no buffer is placed between the fan-out point and the fan-in point and the second delay corresponding to the case where a buffer is placed based on a non-linear model, including: obtaining the capacitance and resistance information of the conductive path; based on the Manhattan distance between the fan-out point and the fan-in point corresponding to the conductive path and the capacitance and resistance information, calculating the first delay and the second delay of the conductive path by using the non-linear model.

[0020] Understandably, by setting a preset length, the conductive paths with longer lengths and larger delays are screened out, and these conductive paths are specifically processed and calculated, while the conductive paths with smaller delays are not included in the subsequent calculations. Thus, while not affecting the subsequent calculation accuracy, the calculation amount of the overall solution is reduced, and the working efficiency is improved.

[0021] 3. The embodiments of the present invention obtain the corresponding buffer insertion candidate positions based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and fan-in point, including: obtaining the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path. It should be understood that the magnitude of the delay of the conductive path is proportional to the square of the length of the conductive path. Therefore, based on the change situation of the conductive path delay after inserting the buffer, the optimal buffer insertion quantity of the current conductive path can be judged; obtaining the optimal segmentation distance based on the Manhattan distance between the fan-out point and the fan-in point corresponding to all conductive paths and the optimal buffer insertion quantity; finding the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and performing a segmentation process on it to obtain the buffer insertion candidate positions.

[0022] Through the above method, a varying number of intermediate nodes can be added on the basis of the Steiner tree formed by the original circuit as candidate points for the Van Ginneken algorithm, so as to obtain a more reasonable buffer placement scheme to alleviate the greater delay caused by long wires, that is, long conductive paths, in advanced processes.

[0023] 4. The embodiments of the present invention obtain the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path, including: comparing the magnitudes of the first delay and the second delay; if the second delay is less than the first delay, then making the first delay equal to the second delay, and making i = i + 1, recalculating the second delay based on i, and comparing the magnitudes of the two again until the second delay is greater than or equal to the first delay, then the current buffer insertion quantity is the optimal buffer insertion quantity corresponding to the current conductive path. Through this method, the critical quantity of buffer insertion for the current conductive path can be quickly and accurately found.

[0024] 5. The embodiment of the present invention finds the to-be-split path formed by the fan-out point and the fan-in point based on the optimal split distance and performs split processing on it, including: screening the conductive paths formed by the fan-out point and each fan-in point based on the optimal split distance to obtain the to-be-split path; equally dividing the to-be-split path until its length is less than the optimal split distance. By the above method, the length of any edge of the Steiner tree corresponding to the current circuit is less than the optimal split distance. At the split position, that is, the candidate position for buffer insertion, a buffer is placed, splitting the long conductive path with large delay into short conductive paths with small delay, alleviating the large delay caused by the long conductive path in the advanced process node.

[0025] 6. The embodiment of the present invention takes the candidate position for buffer insertion as the candidate point of the Van Ginneken algorithm to calculate the buffer placement scheme, including: obtaining the candidate positions for buffer insertion of all conductive paths to obtain a candidate position set; updating the capacitance and resistance information of the corresponding conductive paths based on the candidate position set; using the Van Ginneken algorithm to solve the buffer placement scheme based on the candidate position set and the capacitance and resistance information of the conductive paths. Taking the buffer insertion position calculated by the above method as a new node, dividing the original long conductive path into short conductive paths, re-routing the circuit to update the capacitance and resistance information of the current Steiner tree to use the Van Ginneken algorithm to obtain the buffer placement scheme, and performing the Van Ginneken algorithm based on the updated Steiner tree. Compared with the original Van Ginneken algorithm, the range of buffer insertion positions is expanded, and the influence of the long edges in the Steiner tree on the placement scheme is weakened, so that a more reasonable buffer placement scheme can be obtained.

[0026] 7. The embodiment of the present invention also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the buffer insertion method as described in any one of the above. It has the same beneficial effects as the buffer insertion method described in any one of the above, and will not be elaborated here.

Description of the Drawings

[0027] Figure 1 is the flowchart of the steps of a buffer insertion method provided by the first embodiment of the present invention.

[0028] Figure 2 is the detailed flowchart of step S2 in a buffer insertion method provided by the first embodiment of the present invention.

[0029] Figure 3 is the detailed flowchart of step S3 in a buffer insertion method provided by the first embodiment of the present invention.

[0030] Figure 4It is a detailed step flowchart of step S31 in a buffer insertion method provided by the first embodiment of the present invention.

[0031] Figure 5 It is a detailed step flowchart of step S32 in a buffer insertion method provided by the first embodiment of the present invention.

[0032] Figure 6 It is a detailed step flowchart of step S33 in a buffer insertion method provided by the first embodiment of the present invention.

[0033] Figure 7 It is a detailed step flowchart of the screening process in a buffer insertion method provided by the first embodiment of the present invention.

[0034] Figure 8 It is a detailed step flowchart of step S4 in a buffer insertion method provided by the first embodiment of the present invention.

[0035] Figure 9 It is a schematic structural diagram of a storage medium provided by the second embodiment of the present invention.

[0036] Figure 10 It is a schematic structural diagram of the original Steiner tree provided by the first embodiment of the present invention.

[0037] Figure 11 It is a schematic structural diagram of the Steiner tree after inserting new nodes provided by the first embodiment of the present invention.

[0038] Figure 12 It is a buffer placement scheme generated based on the original Steiner tree provided by the first embodiment of the present invention.

[0039] Figure 13 It is a buffer placement scheme generated based on the Steiner tree after inserting new nodes provided by the first embodiment of the present invention.

[0040] Explanation of the attached drawing reference numerals:

[0041] 1. Storage medium.

Detailed implementation manners

[0042] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the attached drawings and implementation examples. It should be understood that the specific implementation examples described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0044] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, the "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0045] In various embodiments of the present invention, it should be understood that the magnitude of the sequence numbers of the above processes does not necessarily mean the inevitable sequence of execution. The execution sequence of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0046] The flowcharts and block diagrams in the drawings of the present invention illustrate the possible architectures, functions and operations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementation solutions, the functions marked in the blocks may also occur in a different order from that marked in the drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, which is determined based on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0047] Some of the prior art features mentioned in this solution are defined as follows:

[0048] The Manhattan distance is a geometric term used in a geometric metric space to indicate the total absolute axis distance between two points, that is, the total distance of the projection of the line segment formed by two points on the coordinate axes in a rectangular coordinate system. In a plane, the Manhattan distance between point i(X1,Y1) and point j(X2,Y2) is d(i,j) = |X1 - X2| + |Y1 - Y2|.

[0049] A Steiner tree is a theoretical model. In an undirected weighted graph, given several key points, it is required to find an edge set with the minimum sum of edge weights such that any two key points remain connected when only the edges in this edge set are retained. In other words, a Steiner tree is a subset of the minimum spanning tree that connects the given set of points.

[0050] In an integrated circuit, a fan-out point usually refers to the output terminal of a logic gate or module, which can drive the input terminals of other logic gates or modules; a fan-in point usually refers to the input terminal of a logic gate or module, which can receive signals from the output terminals of other logic gates or modules.

[0051] Please refer to Figure 1 , the first embodiment of the present invention provides a buffer insertion method, and the method includes:

[0052] Step S1: Obtain the position information of the fan-out points and all corresponding fan-in points of the integrated circuit, and calculate the Manhattan distance between the fan-out point and each fan-in point based on the position information;

[0053] Step S2: Calculate the first delay corresponding to the case without a buffer placed between the fan-out point and the fan-in point, and the second delay corresponding to the case with a buffer placed, based on a non-linear model;

[0054] Step S3: Calculate the corresponding candidate positions for buffer insertion based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and fan-in point;

[0055] Step S4: Use the candidate positions for buffer insertion as the candidate points of the Van Ginneken algorithm to calculate the buffer placement scheme.

[0056] It can be understood that the buffer insertion method provided in this embodiment uses a non-linear model that is more accurate than a linear model to calculate the delay of the conductive path, so as to improve the quality of delay estimation and give a more reasonable buffer placement scheme; at the same time, based on the high-precision delay estimation results, long conductive paths with large delays are segmented, and new nodes are inserted to act as candidate points for the Van Ginneken algorithm, avoiding the problem that the finally calculated buffer placement scheme still has a high delay caused by the influence of long conductive paths on the operation of the Van Ginneken algorithm.

[0057] Specifically, the position information of the fan-out points and all corresponding fan-in points of the current circuit obtained in step S1 of this embodiment is specifically to obtain the position coordinates of the current fan-out point and its corresponding J fan-in points.

[0058] Specifically, the Manhattan distance between the fan-out point and a specific fan-in point j

[0059] Among them, the coordinates of the fan-out point are (x out , y out ), and the coordinates of the fan-in point j are (x in , y in ), j where 1 ≤ j ≤ J.

[0060] Furthermore, in a specific embodiment, after obtaining the position information of the fan-out point and the fan-in point of the integrated circuit, it is also necessary to perform wire routing on the aforementioned points to obtain the corresponding conductive path, and based on the conductive path, obtain the corresponding capacitance and resistance values, so as to calculate the delay of the conductive path in the corresponding situation. It should be understood that the wire routing process referred to in this embodiment is the wire routing in the layout design.

[0061] In the actual calculation process of this embodiment, a corresponding Steiner tree will be generated based on the current wire routing situation. The nodes of the Steiner tree represent the fan-out point and / or the fan-in point of the circuit, and the edges represent the conductive paths corresponding to the fan-out point and the fan-in point. The circuit network is optimized and calculated in the form of a Steiner tree, which reduces the complexity of the operation and improves the calculation efficiency.

[0062] In other feasible embodiments, a binary tree, a red-black tree, etc. can also be used to represent the circuit.

[0063] Furthermore, please refer to Figure 2 , step S2 includes:

[0064] Step S21: Obtain the conductive path corresponding to the fan-out point and the fan-in point whose Manhattan distance is greater than the preset length;

[0065] Step S22: Obtain the capacitance and resistance information of the conductive path;

[0066] Step S23: Based on the Manhattan distance and the capacitance and resistance information between the fan-out point and the fan-in point corresponding to the conductive path, use a non-linear model to calculate the first delay and the second delay of the conductive path.

[0067] In a specific embodiment, the non-linear model used to calculate the delay of the conductive path is specifically the NLDM (Non-Linear Delay Model) model, so that the accurate delay of the conductive path can still be calculated under the sub-micron process.

[0068] In addition, in other embodiments, other types of non-linear models can also be used to calculate the delay of the conductive path, as long as the delay of the conductive path with relatively high accuracy can be estimated, and no more restrictions are imposed here.

[0069] It should be noted that the delay of the conductive path is proportional to the square of the length of the conductive path. Therefore, in this embodiment, by comparing the Manhattan distance between the fan-out point and the fan-in point with the preset length, the conductive paths with larger delays are screened out for further processing, while the conductive paths with smaller delays do not participate in the subsequent operations. By this method, the amount of operations in the subsequent calculation scheme can be reduced and the overall working efficiency can be improved.

[0070] Further, please refer to Figure 3 , step S3 includes:

[0071] Step S31: Obtain the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path;

[0072] Step S32: Obtain the optimal splitting distance based on the Manhattan distance and the optimal buffer insertion quantity corresponding to all conductive paths;

[0073] Step S33: Find the path to be split formed by the fan-out point and the fan-in point based on the optimal splitting distance and perform splitting processing on it to obtain candidate positions for buffer insertion.

[0074] In this embodiment, first, the optimal buffer insertion quantity corresponding to the conductive path is calculated, and then the conductive path is evenly split according to this quantity to obtain candidate positions for buffer insertion on the conductive path. It should be understood that the splitting point is the candidate position for buffer insertion.

[0075] In the calculation, the corresponding representation on the Steiner tree is to add a varying number of intermediate nodes on the basis of the original Steiner tree. For details, please refer to Figure 10 and Figure 11 . The intermediate nodes are used as candidate points for the Van Ginneken algorithm, so as to obtain a more reasonable buffer placement scheme to alleviate the greater delay caused by the too long conductive path in the advanced process. As can be seen from Figure 12 and Figure 13 , the Steiner tree generated by the traditional integrated circuit usually has long edges, resulting in a buffer placement scheme calculated based on this Steiner tree having a high-delay placement scheme, specifically manifested as a large spacing between buffers as shown in Figure 12 ; while as shown in Figure 13 , in the buffer placement scheme obtained by the operation of the Steiner tree with intermediate nodes inserted after being processed in this embodiment through the Van Ginneken algorithm, the placement spacing of the buffers is more reasonable and there will be no situation where the spacing is too long resulting in too large a delay.

[0076] Further, please refer to Figure 4 , step S31 includes:

[0077] Step S311: Compare the magnitudes of the first delay and the second delay;

[0078] Step S312: If the second delay is less than the first delay, then set the first delay equal to the second delay, set i = i + 1, recalculate the second delay based on i, and compare their magnitudes again until the second delay is greater than or equal to the first delay. Then, subtract one from the current buffer insertion count to obtain the optimal buffer insertion count corresponding to the current conductive path.

[0079] Specifically, the second delay is the conductive path delay corresponding to uniformly placing i buffers on the corresponding conductive path, where i is a positive integer and i ≥ 1.

[0080] It can be understood that the conductive path delay is proportional to the square of the conductive path length. That is, when inserting buffers on the conductive path, the delay will decrease as the number of inserted buffers increases, but when the number of placed buffers is excessive, the delay will instead increase. Therefore, each conductive path has its optimal buffer insertion count.

[0081] Specifically, for the conductive path between the fan - out point and a specific fan - in point j, define the first delay D1 corresponding to not placing any buffers on this conductive path, and the second delay D2 corresponding to placing i buffers on this conductive path.

[0082] In the specific calculation process, the initialized D1 = d j (0), D2 = d j (1), that is, the initial value of i is 1. It should be understood that d j (0) represents the delay corresponding to placing 0 buffers between the fan - out point and the specific fan - in point j, and d j (1) represents the delay corresponding to placing 1 buffer between the fan - out point and the specific fan - in point j, and so on.

[0083] If d j (1) < d j (0), then set D1 = D2, i = i + 1, and calculate the current second delay D2, that is, the value of d j (2).

[0084] Repeat the above process until D2 ≥ D1. At this time, the number of buffers placed on the conductive path is exactly one more than the optimal buffer insertion count for this conductive path.

[0085] Through the above method, the optimal buffer insertion count between the fan - out point and each fan - in point can be accurately and efficiently calculated, providing a true and accurate data basis for subsequent calculations to improve the rationality of the final buffer placement scheme.

[0086] Furthermore, please refer to Figure 5, step S32 includes:

[0087] Step S321: Obtain the Manhattan distance and the optimal buffer insertion number between the fan-out point and the fan-in point corresponding to all conductive paths;

[0088] Step S322: Calculate the initial segmentation distance corresponding to all conductive paths based on the Manhattan distance and the optimal buffer insertion number between the fan-out point and the fan-in point corresponding to all conductive paths, and obtain the initial segmentation set;

[0089] Step S323: Select the smallest initial segmentation distance in the initial segmentation set as the optimal segmentation distance.

[0090] Specifically, for the conductive path between the fan-out point and a specific fan-in point j, its segmentation distance where i is the optimal buffer insertion number of this conductive path calculated in the previous step.

[0091] The initial segmentation distance between the fan-out point and each fan-in point is calculated by the above method. It should be understood that this initial segmentation distance is the optimal segmentation distance of the current conductive path. Then, based on the calculated initial segmentation distances between the fan-out point and all fan-in points, the smallest one is used as the optimal segmentation distance l of the current circuit network, and the path to be segmented in the current circuit network is found accordingly.

[0092] Further, please refer to Figure 6 , finding the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and performing segmentation processing on it includes:

[0093] Step S331: Perform screening processing on the conductive paths formed by the fan-out point and each fan-in point based on the optimal segmentation distance to obtain the path to be segmented;

[0094] Step S332: Perform equal division processing on the path to be segmented until its length is less than the optimal segmentation distance.

[0095] It should be noted that performing equal division processing on the path to be segmented is essentially inserting new nodes on the edges of the Steiner tree corresponding to this path to be segmented, where represents the value rounded up, L j is the Manhattan distance of this segmented path, l is the optimal segmentation distance of the current circuit network, and the new nodes are the candidate positions for buffer insertion of the corresponding conductive path.

[0096] Specifically, please refer to Figure 7 , the screening processing includes:

[0097] Step S3311: Compare the distance of the conductive path formed by the fan-out point and the fan-in point with the optimal splitting distance.

[0098] Step S3312: If the distance of the conductive path formed by the fan-out point and the fan-in point is greater than the optimal splitting distance, the corresponding conductive path is the path to be split; otherwise, it is a non-path to be split.

[0099] It should be noted that after a series of the above calculations on the conductive paths of a certain length in the current circuit network, the optimal splitting distance is obtained. It should be understood that the optimal splitting distance is calculated based on the conductive paths screened in step S21, that is, the conductive paths of a certain length in the current circuit network. Therefore, the lengths of the conductive paths participating in the calculation are not less than the optimal splitting distance, while some of the lengths of the conductive paths not participating in the calculation may be less than the optimal splitting distance.

[0100] Therefore, before splitting the conductive paths in this example, all conductive paths are first compared and screened to exclude the shorter conductive paths that do not need to participate in the subsequent conductive path splitting process, thereby simplifying the splitting process and improving the overall work efficiency.

[0101] Further, please refer to Figure 8 , step S4 includes:

[0102] Step S41: Obtain the buffer insertion candidate positions of all conductive paths to obtain a candidate position set.

[0103] Step S42: Update the capacitance and resistance information of the corresponding conductive paths based on the candidate position set.

[0104] Step S43: Based on the candidate position set and the capacitance and resistance information of the conductive paths, use the Van Ginneken algorithm to solve the buffer placement scheme.

[0105] It should be noted that in the Van Ginneken algorithm, the inputs of the algorithm are usually the Steiner tree corresponding to the current circuit network, the required arrival time RAT(v) of each fan-in node, and the capacitance C(v) corresponding to each fan-in node; among them, the alternative nodes for placing buffers are arranged on the Steiner tree; the required arrival time represented by RAT(v) is obtained by subtracting the current delay from the RAT of the previous node, that is, the adjacent node of the fan-in end.

[0106] If i buffers are evenly placed on the conductive path from the fan-out to the fan-in node, the total delay can be expressed as

[0107] d(i) = celldelay + i * wiredelay(c buf)+(i - 1)*bufdelay(c buf ))

[0108] +wiredelay(c load )+bufdelay(c load )

[0109] wherein, is the conductive path delay corresponding to the load buffer at the average resistivity r; is the conductive path delay corresponding to the load fan - in terminal capacitance at the average resistivity r; bufdelay(c buf )) and bufdelay(c load )) are the delays in the process device library corresponding to the buffer at the library average transition time when connected to a subsequent buffer and a general load respectively; celldelay is the component delay corresponding to the fan - out node; when at least one buffer is connected, the capacitance c buf and the library average transition time are used to look up the device delay corresponding to the process device library, and when no buffer is connected, the capacitance c load and the process device library average transition time are used to look up the corresponding device delay.

[0110] Specifically, after obtaining the candidate location set, the candidate locations, fan - out points, and fan - in points are wired again to update the capacitance and resistance information of the corresponding conductive paths, that is, to update the Steiner tree. After re - allocation, the new resistance of the n - 1 new node capacitances are the capacitance information of the two - end nodes is the new resistance r, capacitance c, and the buffer insertion location set W are obtained, where c ori is the capacitance of the original starting or ending point, and c0, r0 are the original capacitance and resistance of the corresponding conductive path.

[0111] Based on the above data, using a recursive algorithm, more specifically, using the Find_Cands algorithm to find all (Q, C, M) corresponding to the fan - out point, that is, the solutions in the form of (agreed arrival time, capacitance, buffer placement scheme).

[0112] It should be noted that the buffer placement scheme M includes the buffer placement position and the buffer type placed at the corresponding position. For the solution set of the Find_Cands algorithm, in order to simplify the calculation, we assume that the current node v has two child nodes, and use Find_Cands(v.left) and Find_Cands(v.right) to represent the solutions corresponding to the left and right nodes of the node v. If the current node v has three child nodes, the first two child nodes are used by Find_Cands(v.left) and Find_Cands(v.right) and merged into a new Find_Cands(v.right), and the third child node is Find_Cands(v.left), and so on. No matter how many child nodes the current node v has, all its solutions can be represented by Find_Cands(v.left) and Find_Cands(v.right). In particular, if the current node v has only one node, its corresponding solution set is represented by Find_Cands(v.left), and the polarity of the solution set is represented by a positive and negative sign, for example, Find_Cands(v.left) + Indicates the solution set with polarity 0 corresponding to the left child of the current node

[0113] More specifically, the initial solution space Among them, S + is the solution space where the current node polarity is 0 and no buffer is placed; S - is the solution space where the polarity of the current node is 1 and no buffer is placed; is the solution space where the polarity of the current node is 0 and the buffer is placed; It is the solution space where the polarity of the current node is 1 and the buffer is placed.

[0114] Remember v s is a set of fan-in points, if v∈v s , update S according to the node v and its polarity p(v) + , S - , if p(v)=0

[0115] Then S + ={RAT(v),C(v),b}

[0116] When p(v) = 1, S is calculated similarly -

[0117] like At this time, node v has only one downstream node in the Steiner tree, and for any solution with polarity 0 in the subtree (Q, C, M)∈Find_Cands(v.left) +

[0118] Update the solution set to S+ = S + ∪ {Q, C, M}

[0119] Calculate S similarly -

[0120] If at the Steiner tree node v has two downstream nodes,

[0121] Let

[0122] Let

[0123] Set i = 1 and j = 1

[0124] When and

[0125] Let α l = (Q l , C l , M l ) be the i-th candidate solution in

[0126] Let α r = (Q r , C r , M r ) be the j-th candidate solution in

[0127] At this time, S + = S + ∪ (min(Q l , Q r ), C r + C l , M l ∪ M r )

[0128] If Q l < Q r , i = i + 1

[0129] If Q l ≥ Q r , j = j + 1

[0130] Calculate S similarly -

[0131] Next, update the solution of inserting a buffer at the current position. If the fan-in point v is a feasible buffer position, i.e., v ∈ W

[0132] For each buffer b ∈ B, where B is the set of buffers allowed to be placed at the current position.

[0133] If b is an inverter, bufDelay(b, α) is a function that calculates the device delay based on buffer type and post - capacitance interpolation.

[0134] Find α = (Q, C, M) ∈ S - such that is maximum.

[0135] If b is not an inverter, maintain the original polarity.

[0136] Find α = (Q, C, M) ∈ S + such that is maximum

[0137] If α exists, use the buffer capacitance C(b) and M(v) = b to update the {Q, C, M} tuple, that is, set Perform similar calculations Thus, a total of 2 pairs of solution spaces with or without buffer placement are obtained and merged.

[0138]

[0139] Let e = (u, v) be the parent conductive path of v, where u is the parent node of v. Denote D(u, v) as the conductive path delay from v to u. Before converting all solutions to the next candidate position using the conductive path delay and capacitance updates, that is,

[0140] For any α = (Q, C, M) ∈ S +

[0141] S + = S + ∪ {Q - D(u, v), C + C(e), M} - α

[0142] Perform similar calculations for S -

[0143] Delete the inferior solutions from S + and S - That is, solutions with a larger post - capacitance and without a larger required arrival time.

[0144] Finally, select a solution with the largest RAT in the solution space, and the corresponding buffer placement scheme M is the final placement scheme.

[0145] Furthermore, please refer to Figure 9 , the second embodiment of the present invention also provides a storage medium 1, on which computer program instructions are stored. When the computer program instructions are executed, the steps of any of the above buffer insertion methods are implemented.

[0146] In a specific implementation, the storage medium 1 may be an entity or device capable of carrying computer program code, such as a flash memory, a random access memory, a read-only memory, a USB flash drive, a hard disk, an optical disc, a magnetic disk, etc. Optionally, the computer-readable storage medium includes a non-volatile computer-readable medium. The storage medium 1 has a storage space for program code for executing any method steps in the above buffer insertion method. These program codes can be read out from one or more computer program products or written into another or more computer program products. The program codes can be appropriately compressed in the storage medium 1.

[0147] Compared with the prior art, a buffer insertion method and a storage medium provided by the present invention have the following beneficial effects:

[0148] 1. A buffer insertion method provided by an embodiment of the present invention includes: obtaining position information of a fan-out point of an integrated circuit and all corresponding fan-in points, and calculating the Manhattan distance between the fan-out point and each fan-in point based on the position information; calculating a first delay corresponding to when no buffer is placed between the fan-out point and the fan-in point and a second delay corresponding to when a buffer is placed based on a non-linear model. The delay estimated using the non-linear model is more accurate than that of a traditional linear model; obtaining corresponding buffer insertion candidate positions based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and fan-in point to expand the range of buffer insertion positions and weaken the influence of long conductive paths on the buffer placement scheme; calculating a buffer placement scheme with the buffer insertion candidate positions as candidate points of the Van Ginneken algorithm. By inserting new nodes as candidate points of the Van Ginneken algorithm in the conductive path, a buffer placement scheme with a high delay given by the Van Ginneken algorithm during the calculation of the buffer placement scheme is avoided.

[0149] 2. Calculating, by an embodiment of the present invention based on a non-linear model, a first delay corresponding to when no buffer is placed between a fan-out point and a fan-in point and a second delay corresponding to when a buffer is placed includes: obtaining capacitance and resistance information of a conductive path; calculating the first delay and the second delay of the conductive path using a non-linear model based on the Manhattan distance between the corresponding fan-out point and fan-in point of the conductive path and the capacitance and resistance information.

[0150] It can be understood that by setting a preset length, conductive paths with a longer length and a larger delay are screened out, and these conductive paths are specifically processed and calculated, while conductive paths with a smaller delay are not included in subsequent calculations, thereby reducing the calculation amount of the overall scheme and improving work efficiency without affecting the subsequent calculation accuracy.

[0151] The embodiments of the present invention obtain the corresponding buffer insertion candidate positions based on the Manhattan distance between the first delay, the second delay, and the corresponding fan-out point and fan-in point, including: obtaining the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path. It should be understood that the magnitude of the delay of the conductive path is proportional to the square of the length of the conductive path. Therefore, based on the change of the conductive path delay after inserting the buffer, the optimal buffer insertion quantity of the current conductive path can be judged; obtaining the optimal segmentation distance based on the Manhattan distance and the optimal buffer insertion quantity between the fan-out point and the fan-in point corresponding to all conductive paths; finding the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and performing segmentation processing on it to obtain the buffer insertion candidate positions.

[0152] Through the above method, a varying number of intermediate nodes can be added on the basis of the Steiner tree formed by the original circuit as candidate points for the Van Ginneken algorithm, so as to obtain a more reasonable buffer placement scheme to alleviate the greater delay caused by long wires, that is, long conductive paths, in advanced processes.

[0153] The embodiments of the present invention obtain the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path, including: comparing the magnitudes of the first delay and the second delay; if the second delay is less than the first delay, then making the first delay equal to the second delay, and making i = i + 1, recalculating the second delay based on i, and comparing the two magnitudes again until the second delay is greater than or equal to the first delay. Then the current buffer insertion quantity is the optimal buffer insertion quantity corresponding to the current conductive path. Through this method, the critical quantity of buffer insertion for the current conductive path can be quickly and accurately found.

[0154] The embodiments of the present invention find the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and perform segmentation processing on it, including: screening the conductive paths formed by the fan-out point and each fan-in point based on the optimal segmentation distance to obtain the path to be segmented; equally dividing the path to be segmented until its length is less than the optimal segmentation distance. Through the above method, the length of any edge of the Steiner tree corresponding to the current circuit is less than the optimal segmentation distance. Placing a buffer at the segmentation position, that is, the buffer insertion candidate position, can divide the long conductive path with large delay into short conductive paths with small delay, alleviating the large delay caused by long conductive paths in advanced process nodes.

[0155] 6. The buffer insertion candidate positions in the embodiments of the present invention are used as the candidate points of the Van Ginneken algorithm for calculation to obtain the buffer placement scheme, which includes: obtaining the buffer insertion candidate positions of all conductive paths to obtain a candidate position set; updating the capacitance and resistance information of the corresponding conductive paths based on the candidate position set; and using the Van Ginneken algorithm to solve the buffer placement scheme based on the candidate position set and the capacitance and resistance information of the conductive paths. Taking the buffer insertion positions calculated by the above method as new nodes, dividing the original long conductive paths into short conductive paths, and updating the capacitance and resistance information of the current Steiner tree through circuit rerouting to obtain the buffer placement scheme using the Van Ginneken algorithm. Performing the Van Ginneken algorithm based on the updated Steiner tree expands the range of buffer insertion positions compared with the original Van Ginneken algorithm, weakens the influence of long edges in the Steiner tree on the placement scheme, and thus a more reasonable buffer placement scheme can be obtained.

[0156] 7. The embodiments of the present invention also provide a storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the buffer insertion method as described in any one of the above. It has the same beneficial effects as the buffer insertion method described in any one of the above, and will not be elaborated here.

[0157] The above has introduced in detail a buffer insertion method and a storage medium disclosed in the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent replacements, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A buffer insertion method, characterized in that, The method includes: Obtaining the position information of the fan-out point and all corresponding fan-in points of the integrated circuit, and calculating the Manhattan distance between the fan-out point and each fan-in point based on the position information; Calculating the first delay corresponding to the case without placing a buffer and the second delay corresponding to the case after placing a buffer between the fan-out point and the fan-in point based on a non-linear model; Obtaining the corresponding buffer insertion candidate positions based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and the fan-in point; Calculating a buffer placement scheme with the buffer insertion candidate positions as the candidate points of the Van Ginneken algorithm.

2. The buffer insertion method according to claim 1, characterized in that Calculating the first delay corresponding to the case without placing a buffer and the second delay corresponding to the case after placing a buffer between the fan-out point and the fan-in point based on a non-linear model includes: Obtaining the conductive path corresponding to the fan-out point and the fan-in point whose Manhattan distance is greater than a preset length; Obtaining the capacitance and resistance information of the conductive path; Calculating the first delay and the second delay of the conductive path by using a non-linear model based on the Manhattan distance and the capacitance and resistance information between the corresponding fan-out point and fan-in point of the conductive path.

3. The buffer insertion method according to claim 1, wherein: The second delay is the conductive path delay corresponding to uniformly placing i buffers on the corresponding conductive path, where i is a positive integer and i≥1.

4. The buffer insertion method according to claim 3, characterized in that, Obtaining the corresponding buffer insertion candidate positions based on the first delay, the second delay, and the Manhattan distance between the corresponding fan-out point and the fan-in point includes: Obtaining the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path; Obtaining the optimal segmentation distance based on the Manhattan distance and the optimal buffer insertion quantity between the corresponding fan-out point and fan-in point of all the conductive paths; Finding out the path to be segmented formed by the fan-out point and the fan-in point based on the optimal segmentation distance and performing a segmentation process on it to obtain the buffer insertion candidate positions.

5. The buffer insertion method according to claim 4, wherein Obtaining the corresponding optimal buffer insertion quantity based on the first delay and the second delay of the conductive path includes: Comparing the magnitudes of the first delay and the second delay; If the second delay is less than the first delay, making the first delay equal to the second delay, setting i = i + 1, recalculating the second delay based on i, and comparing the magnitudes of the two again until the second delay is greater than or equal to the first delay, then subtracting one from the current buffer insertion quantity to obtain the optimal buffer insertion quantity corresponding to the current conductive path.

6. The buffer insertion method according to claim 4, wherein Obtaining the optimal segmentation distance based on the Manhattan distance and the optimal buffer insertion quantity between the corresponding fan-out point and fan-in point of all the conductive paths includes: Obtaining the Manhattan distance and the optimal buffer insertion quantity between the corresponding fan-out point and fan-in point of all the conductive paths; Calculating the initial segmentation distances corresponding to all the conductive paths based on the Manhattan distance and the optimal buffer insertion quantity between the corresponding fan-out point and fan-in point of all the conductive paths to obtain an initial segmentation set; Selecting the smallest initial segmentation distance in the initial segmentation set as the optimal segmentation distance.

7. The buffer insertion method according to claim 4, wherein Finding the path to be split formed by the fan-out point and the fan-in point based on the optimal split distance and performing split processing on it includes: Performing screening processing on the conductive paths formed by the fan-out point and each of the fan-in points based on the optimal split distance to obtain the paths to be split; Performing equal division processing on the paths to be split until their lengths are less than the optimal split distance.

8. The buffer insertion method according to claim 7, wherein The screening processing includes: Comparing the size of the distance of the conductive path formed by the fan-out point and the fan-in point with the optimal split distance; If the distance of the conductive path formed by the fan-out point and the fan-in point is greater than the optimal split distance, the corresponding conductive path is the path to be split; otherwise, it is a non-path to be split.

9. The buffer insertion method according to claim 1, wherein Calculating the buffer placement scheme with the candidate position for buffer insertion as the candidate point of the Van Ginneken algorithm includes: Obtaining the candidate positions for buffer insertion of all the conductive paths to obtain a set of candidate positions; Updating the capacitance and resistance information of the corresponding conductive paths based on the set of candidate positions; Based on the set of candidate positions and the capacitance and resistance information of the conductive paths, using the Van Ginneken algorithm to solve the buffer placement scheme.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the buffer insertion method according to any one of claims 1-9.

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