Motor phase current sampling system and motor driver

Abstract

The invention discloses a motor phase current sampling system and a motor driver, and relates to the technical field of motor control. The motor phase current sampling system comprises a control module and a sampling module, wherein the control module is used for outputting a sampling clock; and after receiving the sampling clock, the sampling module samples the phase current of the motor to be sampled so as to output the sampling current and a feedback clock synchronized with the sampling current to the control module. Wherein for any target sampling moment, the control module calibrates the target sampling moment according to a preset calibration time difference to obtain a target moment, and outputs the sampling clock at the target moment, so that when the sampling module receives the sampling clock, the sampling module outputs the sampling clock at the target moment; the time for sampling the phase current of the to-be-sampled motor is the target sampling time; and the time difference for calibration is determined by the control module according to the moment of outputting the sampling clock and the moment of receiving the feedback clock.

Description

Technical Field

[0001] The present invention relates to the technical field of motor control, and particularly to a sampling system for motor phase current and a motor driver. Background Art

[0002] Phase current sampling is an important functional module in motor FOC control (Field-Oriented Control). Whether the feedback of the motor phase current is accurate affects the control accuracy of the current loop in the servo driver. Existing phase current sampling technologies ignore the delay error of signal transmission on the sampling path, resulting in a certain error between the current value at the sampling moment and the current value at the feedback moment. In a servo driver, the magnitude of the phase current affects the control of the motor torque, and its current accuracy is an important factor affecting the torque control accuracy.

[0003] In order to reduce the error between the current value at the feedback moment and the current value at the sampling moment, in existing solutions, the method of linear fitting of phase current is commonly used. By fitting the slope of the phase current in a small interval through two sampling points with a small time interval, and making a linear function relationship, the magnitude of the phase current at the next sampling point is estimated. This method focuses on the estimation of the phase current and does not actually correct the delay error of signal transmission. Summary of the Invention

[0004] The main technical problem solved by the present invention is: solving the problem that there is a delay in the signal transmission path of the sampling of the motor phase current.

[0005] According to a first aspect, in one embodiment, a sampling system for motor phase current is provided, including: A control module, configured to output a sampling clock; A sampling module, after receiving the sampling clock, samples the phase current of the motor to be sampled, and outputs the sampled current and a feedback clock synchronized with the sampled current to the control module; Wherein, for any target sampling moment: The control module calibrates the target sampling moment according to a preset calibration time difference to obtain a target moment, and outputs the sampling clock at the target moment, so that when the sampling module receives the sampling clock, the moment of sampling the phase current of the motor to be sampled is the target sampling moment; The calibration time difference is determined by the control module according to the moment of outputting the sampling clock and the moment of receiving the feedback clock.

[0006] In one embodiment, the sampling system further includes a sampling clock transmission module and a feedback clock transmission module; The input end of the sampling clock transmission module is connected to the control module, and the output end of the sampling clock transmission module is connected to the sampling module; The input end of the feedback clock transmission module is connected to the sampling module, and the output end of the feedback clock transmission module is connected to the control module; The calibration time difference includes a first transmission delay duration for the sampling clock transmission module to output the sampling clock to the sampling module, and a second transmission delay duration for the feedback clock transmission module to output the feedback clock to the control module.

[0007] In one embodiment, the first transmission delay duration is equal to the second transmission delay duration, and the calibration time difference is the first transmission delay duration or the second transmission delay duration.

[0008] In one embodiment, the sampling system further includes a data receiving module. The input end of the data receiving module is connected to the sampling module, and the output end of the data receiving module is connected to the control module. The data receiving module is configured to input the sampled current into the control module.

[0009] In one embodiment, the data receiving module includes a first filtering module, a first inverting module, and a first inductance module connected in sequence; the first filtering module is configured to filter out high-frequency interference of the sampled current, the first inductance module is configured to absorb high-frequency interference of the sampled current, and the first inverting module is configured to shape the sampled current.

[0010] In one embodiment, the sampling clock transmission module includes a second filtering module, a second inverting module, and a second inductance module connected in sequence; the second filtering module is configured to filter out high-frequency interference of the sampling clock, the second inductance module is configured to absorb high-frequency interference of the sampling clock, and the second inverting module is configured to shape the sampling clock.

[0011] In one embodiment, the feedback clock transmission module includes a third filtering module, a third inverting module, and a third inductance module connected in sequence; the third filtering module is configured to filter out high-frequency interference of the feedback clock, the third inductance module is configured to absorb high-frequency interference of the feedback clock, and the third inverting module is configured to shape the feedback clock.

[0012] In one embodiment, the first inductance module, the second inductance module, and the third inductance module all include magnetic beads, and the number of magnetic beads in the first inductance module, the second inductance module, and the third inductance module is the same.

[0013] In one embodiment, the first inverter module, the second inverter module, and the third inverter module each include an inverter, and the number of inverters in the first inverter module, the second inverter module, and the third inverter module is the same.

[0014] According to a second aspect, in one embodiment, a motor driver is provided, and the motor driver includes the sampling system of the motor phase current in any of the above embodiments.

[0015] According to the sampling system of the motor phase current and the motor driver in the above embodiments, the control module calibrates any target sampling moment according to a preset calibration time to obtain a target moment. After determining the target moment, the control module outputs a sampling clock at the target moment, so that when the sampling module receives the sampling clock, the moment of sampling the phase current of the motor to be sampled is the target sampling moment. Among them, the calibration time difference is determined by the control module according to the moment of outputting the sampling clock and the moment of receiving the feedback clock. In this application, the calibration time difference is determined according to the moment of outputting the sampling clock and the moment of receiving the feedback clock, the target sampling moment is calibrated according to the calibration time difference to obtain the target moment, and the sampling clock is output at the target moment, so that the phase current corresponding to the target sampling moment can be obtained, and the control accuracy of the servo current loop is improved. Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of a sampling system of a motor phase current in one embodiment; Figure 2 It is a circuit diagram of a sampling system of a motor phase current in one embodiment; Figure 3 It is a correction flowchart of a sampling system of a motor phase current in one embodiment; Figure 4 It is a schematic structural diagram of a data receiving module in one embodiment; Figure 5 It is a schematic structural diagram of a sampling clock transmission module in one embodiment; Figure 6 It is a schematic structural diagram of a feedback clock transmission module in one embodiment; Figure 7 It is a current-time schematic diagram before correction in one embodiment; Figure 8 It is a current-time schematic diagram after correction in one embodiment; Figure 9 It is a schematic structural diagram of a motor driver in one embodiment. Detailed Description of the Invention

[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific embodiments. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid overwhelming the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and general technical knowledge in the field.

[0018] In addition, the features, operations, or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be reordered or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment and do not mean that they are necessary sequences, unless it is stated that a certain sequence must be followed.

[0019] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. And the "connection" and "coupling" mentioned in the present application, unless otherwise specified, both include direct and indirect connection (coupling).

[0020] Please refer to Figure 1 , in one embodiment, the present application provides a sampling system 100 for the phase current of a motor, including a control module 110, a sampling module 120, a sampling clock transmission module 130, a feedback clock transmission module 140, and a data receiving module 150.

[0021] In one embodiment, the clock output terminal of the control module 110 is connected to the input terminal of the sampling clock transmission module 130, and the output terminal of the sampling clock transmission module 130 is connected to the clock receiving terminal of the sampling module 120. The data output terminal of the sampling module 120 is connected to the input terminal of the data receiving module 150, and the output terminal of the data receiving module 150 is connected to the data receiving terminal of the control module 110. The clock output terminal of the sampling module 120 is connected to the input terminal of the feedback clock transmission module 140, and the output terminal of the feedback clock transmission module 140 is connected to the clock receiving terminal of the control module 110.

[0022] In one embodiment, the control module 110 can adopt a programmable microcontroller, as long as it can calculate the time difference for calibration.

[0023] Please refer toFigure 2 In this application, the control module 110 uses an FPGA. The PIN1 pin of the FPGA is used to output a sampling clock. After receiving the sampling clock, the sampling module 120 samples the phase current of the motor to be sampled, and then outputs the sampled current and the feedback clock synchronized with the sampled current to the control module 110. The PIN3 pin of the FPGA receives the sampled current data. The PIN2 pin of the FPGA is used to receive the feedback clock. The FPGA determines the calibration time difference based on the time when the sampling clock is output through the PIN1 pin and the time when the feedback clock is received through the PIN2 pin.

[0024] The sampling module 120 in this application uses an isolated sampling ADC. The CLKIN pin of the isolated sampling ADC receives the sampling clock or outputs the feedback clock. The DOUT pin of the isolated sampling ADC outputs the digital quantity signal of the voltage. The AINP pin and AINN pin of the isolated sampling ADC are respectively connected to the positive pole and negative pole of the sampling resistor Rs. The sampling resistor Rs is the sampling resistor on the U phase or V phase or W phase of the motor to be sampled, and it can convert the sampled current into the voltage analog quantity required by the isolated sampling ADC. The sampling resistor Rs uses a resistor with a small resistance value and a large power. When the sampled current flows through it, a voltage difference will be formed across the sampling resistor Rs, and the isolated sampling ADC will transmit the voltage difference to the control module 110 in the form of a digital quantity. Then, the sampled current can be calculated by dividing the voltage difference by the resistance value of the sampling resistor.

[0025] Please refer to Figure 3 In one embodiment, after determining the calibration time difference, for any target sampling moment, the control module 110 calibrates the target sampling moment according to the calibration time difference to obtain the target moment, and outputs the sampling clock at the target moment, so that when the sampling module 120 receives the sampling clock, the moment of sampling the phase current of the motor to be sampled is the target sampling moment. That is, when it is necessary to sample the phase current of the motor to be sampled at any target sampling moment, the control module 110 outputs the sampling clock in advance by the calibration time difference based on the target sampling moment. Because the sampling clock is output in advance by the calibration time difference, when the sampling module 120 receives the target sampling moment, it can just sample the phase current of the motor to be sampled, thus avoiding the delay error on the transmission path.

[0026] It should be noted that in the control system for controlling the motor mounted in the motor driver, the control system usually includes a position loop, a speed loop, and a current loop. The task of the current loop is to control the phase currents of each phase of the motor so that they operate quickly and accurately according to the target value, because the phase currents ultimately determine the torque output by the motor. In this application, by correcting the sampling time of the sampled current, the sampled current actually obtained at the target sampling time is determined, and the sampled current actually obtained at the target sampling time is compared with the target current, thereby adjusting the control signal and adjusting the output of the inverter to ensure that the motor generates torque as expected and achieve precise control.

[0027] In one embodiment, a sampling clock transmission module 130 and a feedback clock transmission module 140 are connected between the control module 110 and the sampling module 120, so the calibration time difference is generated by the sampling clock transmission module 130 and the feedback clock transmission module 140. Specifically, the calibration time difference includes the first transmission delay duration for the sampling clock transmission module 130 to output the sampling clock to the sampling module 120, and the second transmission delay duration for the feedback clock transmission module 140 to output the feedback clock to the control module 110.

[0028] In one embodiment, to ensure the accuracy of the calibration time difference, regardless of the hardware structures of the sampling clock transmission module 130 and the feedback clock transmission module 140, the first transmission delay duration of the sampling clock transmission module 130 and the second transmission delay duration of the feedback clock transmission module 140 must be equal, so the calibration duration is the first transmission delay duration or the second transmission delay duration.

[0029] In this application, to ensure the same first transmission delay duration and second transmission duration, the sampling clock transmission module 130 and the feedback clock transmission module 140 adopt similar hardware circuits. At the same time, to ensure the synchronization of the feedback clock and the sampled current, the data receiving module 150 and the feedback clock transmission module 140 also adopt similar hardware circuits, which will be specifically described below.

[0030] Please refer to Figure 4 , in one embodiment, the data receiving module 150 includes a first filtering module 151, a first inverting module 153, and a first inductance module 152 connected in sequence. The first filtering module 151 is used to filter out the high-frequency interference of the sampled current, the first inductance module 152 is used to absorb the high-frequency interference of the sampled current, and the first inverting module 153 is used to shape the sampled current.

[0031] Please refer to Figure 2, In one embodiment, the first filtering module 151 includes a resistor R13, a capacitor C9, a resistor R11, and a capacitor C7. The resistor R13 and the capacitor C9, as well as the resistor R11 and the capacitor C7, form a first-order low-pass filter, which can effectively filter out the high-frequency spike burrs of the sampled current. The first inductance module 152 includes a bead L3, which can also absorb the high-frequency spike burr interference of the sampled current. The first inverting module 153 includes an inverter U3F and an inverter U3E. The inverter U3F and the inverter U3E are used to shape the waveform of the sampled current to make it more approximate to a square wave. Using two inverters can keep the waveform phase consistent and no inversion will occur. On the data line where the sampling module 120 outputs the sampled current, the signal edge may not be steep and the waveform may be blurred due to line loss, interference, or insufficient driving ability. The inverter U3F and the inverter U3E "reshape" these digital signals with burrs or fuzzy rising / falling edges into standard square wave signals.

[0032] In one embodiment, the data receiving module 150 further includes a resistor R14, a resistor R12, and a capacitor C8. The first end of the resistor R14 is connected to the DOUT pin of the isolated sampling ADC, the second end of the resistor R14 is connected to the input end of the inverter U3F, the output end of the inverter U3F is connected to the first end of the resistor R13, the second end of the resistor R13 is connected to the first end of the capacitor C9, and the second end of the capacitor C9 is grounded. The second end of the resistor R13 is also connected to the first end of the bead L3, the second end of the bead L3 is connected to the first end of the resistor R12, and the second end of the resistor R12 is grounded. The first end of the resistor R12 is also connected to the first end of the capacitor C8, and the second end of the capacitor C8 is grounded. The first end of the capacitor C8 is also connected to the input end of the inverter U3E, the output end of the inverter U3E is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the first end of the capacitor C7, the second end of the capacitor C7 is grounded, and the first end of the capacitor C7 is also connected to the PIN3 pin of the FPGA.

[0033] It should be noted that the resistor R12 is a pull-down resistor. The inverter U3F outputs the lowest voltage to the ground and discharges the capacitor C8 in time. The capacitor C8 has a filtering and voltage stabilizing effect to improve the waveform quality of the sampled current. The resistor R14 is a current-limiting resistor to protect the inverter U3F.

[0034] Please refer to Figure 5 , In one embodiment, the sampling clock transmission module 130 includes a second filtering module 131, a second inverting module 133, and a second inductance module 132 connected in sequence. The second filtering module 131 is used to filter out the high-frequency interference of the sampling clock, the second inductance module 132 is used to absorb the high-frequency interference of the sampling clock, and the second inverting module 133 is used to shape the sampling clock.

[0035] Please refer to Figure 2, In one embodiment, the second filtering module 131 includes a resistor R1, a capacitor C1, a resistor R3, a capacitor C2, a resistor R4, and a capacitor C3. The resistor R1 and the capacitor C1, the resistor R3 and the capacitor C2, and the resistor R4 and the capacitor C3 form a first-order low-pass filter, which can effectively filter out the high-frequency spike burrs of the sampling clock. The second inductor module 132 includes a bead L1, which can also absorb the high-frequency spike burr interference of the sampling clock. The second inverting module 133 includes an inverter U3A and an inverter U3B. The inverter U3A and the inverter U3B are used to shape the waveform of the sampling clock to make it closer to a square wave. Using two inverters can keep the waveform phase consistent and no inversion will occur.

[0036] , In one embodiment, the sampling clock transmission module 130 further includes a resistor R2, a resistor R5, and a resistor R6. The first end of the resistor R1 is connected to the PIN1 pin of the FPGA. The second end of the resistor R1 is connected to the input end of the inverter U3A. The second end of the resistor R1 is also connected to the first end of the resistor R2. The second end of the resistor R2 is grounded. The second end of the resistor R1 is also connected to the first end of the capacitor C1. The second end of the capacitor C1 is grounded. The output end of the inverter U3A is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the first end of the bead L1. The second end of the resistor R3 is also connected to the first end of the capacitor C2. The second end of the capacitor C2 is grounded. The second end of the bead L1 is connected to the first end of the resistor R4. The second end of the resistor R4 is connected to the first end of the capacitor C3. The second end of the capacitor C3 is grounded. The second end of the resistor R4 is connected to the input end of the inverter U3B. The output end of the inverter U3B is connected to the first end of the resistor R5. The second end of the resistor R5 is grounded. The first end of the resistor R5 is also connected to the low end of the resistor R6. The second end of the resistor R6 is connected to the CLKIN pin of the isolated sampling ADC.

[0037] It should be noted that the resistors R2 and R5 are pull-up resistors, which are connected to the power supply VCC of 3.3V, so as to enhance the driving ability of the circuit. The resistor R6 can limit the circuit current to provide current limiting protection for the isolated sampling ADC.

[0038] Please refer to Figure 6 , In one embodiment, the feedback clock transmission module 140 includes a third filtering module 141, a third inverting module 143, and a third inductor module 142 connected in sequence. The third filtering module 141 is used to filter out the high-frequency interference of the feedback clock. The third inductor module 142 is used to absorb the high-frequency interference of the feedback clock. The third inverting module 143 is used to shape the feedback clock.

[0039] Please refer to Figure 2, In one embodiment, the third filtering module 141 includes a resistor R9, a capacitor C6, a resistor R7, and a capacitor C4. The resistor R9 and the capacitor C6, as well as the resistor R7 and the capacitor C4, form a first-order low-pass filter, which can effectively filter out the high-frequency spike burrs of the feedback clock. The third inductor module 142 includes a bead L2, which can also absorb the high-frequency spike burr interference of the feedback clock. The third inverting module 143 includes inverters U3D and U3C, which are used to shape the waveform of the feedback clock to make it more approximate to a square wave. Using two inverters can keep the waveform phase consistent and no inversion will occur.

[0040] In one embodiment, the feedback clock transmission module 140 further includes a resistor R10, a resistor R18, and a capacitor C5. The first end of the resistor R10 is connected to the CLLKIN pin of the isolation sampling ADC, the second end of the resistor R10 is connected to the input end of the inverter U3D, the output end of the inverter U3D is connected to the first end of the resistor R9, the second end of the resistor R9 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The second end of the resistor R9 is also connected to the first end of the bead L2, the second end of the bead L2 is connected to the first end of the resistor R8, and the second end of the resistor R8 is grounded. The first end of the resistor R8 is also connected to the first end of the capacitor C5, and the second end of the capacitor C5 is grounded. The first end of the capacitor C5 is also connected to the input end of the inverter U3C, the output end of the inverter U3C is connected to the first end of the resistor R7, the second end of the resistor R7 is connected to the first end of the capacitor C4, the second end of the capacitor C4 is grounded, and the first end of the capacitor C4 is also connected to the PIN2 pin of the FPGA.

[0041] It should be noted that the resistor R8 is a pull-down resistor, and the inverter U3D outputs the lowest voltage to the ground, and at the same time discharges the capacitor C5 in time. The capacitor C5 has a filtering and voltage stabilizing effect to improve the quality of the clock feedback waveform. The resistor R10 is a current-limiting resistor to protect the inverter U3D.

[0042] In summary, the FPGA samples through an isolated sampling ADC output by a sampling clock. After the isolated sampling ADC is completed, it returns to the FPGA through a feedback clock and a sampling current. If the delays of the sampling clock and the feedback clock paths are different, the data alignment will shift, resulting in jitter or timing errors. Therefore, the circuit structures in the sampling clock transmission module 130, the feedback clock transmission module 140, and the data receiving module 150 adopted in this application are basically similar. Although beads are mainly used for high-frequency suppression / anti-interference, they also have a slight delay on signals, especially in high-speed digital signal paths and cannot be ignored. Therefore, the number of beads in the sampling clock transmission module 130, the feedback clock transmission module 140, and the data receiving module 150 must be the same, and even the models and specifications are recommended to be the same. The delay of the inverter is relatively more obvious, generally ranging from dozens to hundreds of picoseconds for each inverter. If the number of inverters in the sampling clock transmission module 130, the feedback clock transmission module 140, and the data receiving module 150 is different, it will cause a deterministic time delay difference. Therefore, in this application, the number of inverters in the sampling clock transmission module 130, the feedback clock transmission module 140, and the data receiving module 150 must be equal.

[0043] In this application, the control module 110 is used to output a sampling clock, receive a feedback clock and a sampling current, record the time when the sampling clock is output and the time when the feedback clock is received. Half of the time difference between the two times is the delay error of the single-phase sampling output path, that is, the time difference for calibration. The control module 110 advances the delay error for any target sampling moment, so that the sampling module 120 can obtain the phase current of the motor to be sampled at the accurate moment of the target sampling moment. This application also utilizes the fact that the sampling clock transmission module 130 can filter and shape the high-frequency sampling clock, reducing the high-frequency glitch interference of the sampling clock. The data receiving module 150 and the feedback clock transmission module 140 respectively output the sampling current and the feedback clock from the sampling module 120 to the control module 110, and use the data receiving module 150 and the feedback clock transmission module 140 to filter and shape the sampling current and the feedback clock respectively, reducing the high-frequency glitch interference of the sampling current and the feedback clock. In this way, this application can achieve sampling the phase current of the motor to be sampled at the target sampling moment while reducing the interference of the sampling clock, the feedback clock, and the sampling current, ensuring the accuracy of clock and current transmission.

[0044] Please refer to Figure 7 and Figure 8 , and a specific embodiment is used to specifically elaborate on the correction of the target sampling moment in this application.

[0045] Please refer to Figure 7, when the target sampling time of the sampled current is not corrected, time point t1 is the time point when the FPGA outputs the sampling clock, and the corresponding phase current is Is1; time point t2 is the time point when the sampling clock is transmitted to the sampling module 120 through the sampling clock transmission module 130, and the corresponding phase current is Is2; time point t3 is the time point when the FPGA receives the feedback clock and the sampled current. When the FPGA executes the phase current sampling command of the motor to be sampled at time point t1, actually after the transmission delay of the sampling clock transmission module 130, at time point t2, the sampling module 120 can collect the phase current Is2, and after the transmission delay of the feedback clock transmission module 140 again, the FPGA can receive the phase current Is2 at time point t3 and process it. Therefore, the delay error from the time when the FPGA outputs the phase current sampling time to receiving the sampled current is , that is, the delay error between the time when the FPGA outputs the sampling clock and the time when it receives the feedback clock is . When the phase current acquisition command is output at time point t1, actually the Is2 corresponding to time point t2 is acquired, and the phase current error is |Is2 - Is1|, which will affect the control accuracy of the current loop in FOC control and further affect the motor torque control.

[0046] Please refer to Figure 8 , after calibration using the sampling system 100 provided by the present application, time point t0 is the time point when the FPGA outputs the sampling clock. Time point t1 is the time point when the sampling clock reaches the sampling module 120 through the sampling clock transmission module 130, that is, the time point of the target sampling time, and the corresponding phase current is Is1. Time point t2 is the time point when the FPGA receives the feedback clock, and the corresponding sampled current is Is2. Before the phase current sampling correction, the FPGA outputs the sampling clock and records the output time point of the sampling clock as t1, and records the reception time point as t3 after receiving the feedback clock, and the obtained delay error is , then half of the delay error is:

[0047] That is the delay error on the unidirectional transmission path circuit, that is, the time difference for calibration. Since the circuit structures of the sampling clock transmission module 130 and the feedback clock transmission module 140 in the present application are similar, the delay errors of the signals are also close, then:

[0048] When performing the phase current correction process of the motor to be sampled, in order to obtain the magnitude of the phase current of the acquisition command at the specified time point t1, on the basis of the time point of outputting the sampling clock at time point t1, advance , that is, the FPGA outputs the sampling clock at time t0, and the magnitude of the phase current at the specified time t1 (i.e., the target sampling time) can be obtained, effectively reducing the error time and avoiding collecting the phase current at the wrong sampling time, improving the control accuracy of the current loop, and thus making the motor torque control more accurate.

[0049] Please refer to Figure 9 , Another embodiment provides a motor driver 10 for connecting to a motor 20 to sample the phase current of the motor 20. Among them, the motor 20 can be a stepper motor or a servo motor. The motor driver 10 includes the sampling system 100 for the motor phase current in any of the above embodiments. Since the sampling system 100 for the motor phase current has been clearly described in the above embodiments, it will not be elaborated here.

[0050] Those skilled in the art can understand that all or part of the functions of the above methods can be implemented in a hardware manner or in a computer program manner. When all or part of the functions in the above embodiments are implemented in a computer program manner, the program can be stored in a computer-readable storage medium. The storage medium can include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions are realized by a computer executing the program. For example, the program is stored in the memory of the device, and when the processor executes the program in the memory, the above all or part of the functions can be realized. In addition, when all or part of the functions in the above embodiments are implemented in a computer program manner, the program can also be stored in a storage medium such as a server, another computer, magnetic disk, optical disk, flash drive or mobile hard disk, downloaded or copied and saved to the memory of the local device, or the system of the local device is updated. When the processor executes the program in the memory, the above all or part of the functions in the above embodiments can be realized.

[0051] The above uses specific examples to elaborate on the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art of the present invention, based on the idea of the present invention, several simple deductions, deformations or substitutions can also be made.

Claims

1. A sampling system for the phase current of a motor, characterized in that, Including: A control module for outputting a sampling clock; A sampling module, which samples the phase current of the motor to be sampled after receiving the sampling clock, and outputs the sampled current and a feedback clock synchronized with the sampled current to the control module; Wherein, for any target sampling moment: The control module calibrates the target sampling moment according to a preset calibration time difference to obtain a target moment, and outputs the sampling clock at the target moment, so that when the sampling module receives the sampling clock, the moment of sampling the phase current of the motor to be sampled is the target sampling moment; The calibration time difference is determined by the control module according to the moment of outputting the sampling clock and the moment of receiving the feedback clock.

2. The sampling system for the motor phase current according to claim 1, characterized in that The sampling system further includes a sampling clock transmission module and a feedback clock transmission module; The input end of the sampling clock transmission module is connected to the control module, and the output end of the sampling clock transmission module is connected to the sampling module; The input end of the feedback clock transmission module is connected to the sampling module, and the output end of the feedback clock transmission module is connected to the control module; The calibration time difference includes a first transmission delay duration for the sampling clock transmission module to output the sampling clock to the sampling module, and a second transmission delay duration for the feedback clock transmission module to output the feedback clock to the control module.

3. The sampling system for the motor phase current according to claim 2, characterized in that, The first transmission delay duration is equal to the second transmission delay duration, and the calibration time difference is the first transmission delay duration or the second transmission delay duration.

4. The sampling system for the motor phase current according to claim 2, characterized in that, The sampling system further includes a data receiving module, the input end of the data receiving module is connected to the sampling module, and the output end of the data receiving module is connected to the control module, and the data receiving module is used to input the sampled current to the control module.

5. The sampling system for the motor phase current according to claim 4, characterized in that, The data receiving module includes a first filtering module, a first inverting module and a first inductance module connected in sequence; the first filtering module is used to filter out high-frequency interference of the sampled current, the first inductance module is used to absorb high-frequency interference of the sampled current, and the first inverting module is used to shape the sampled current.

6. The sampling system for the motor phase current according to claim 5, characterized in that, The sampling clock transmission module includes a second filtering module, a second inverting module and a second inductance module connected in sequence; the second filtering module is used to filter out high-frequency interference of the sampling clock, the second inductance module is used to absorb high-frequency interference of the sampling clock, and the second inverting module is used to shape the sampling clock.

7. The sampling system for the motor phase current according to claim 6, wherein, The feedback clock transmission module includes a third filtering module, a third inverting module and a third inductance module connected in sequence; the third filtering module is used to filter out high-frequency interference of the feedback clock, the third inductance module is used to absorb high-frequency interference of the feedback clock, and the third inverting module is used to shape the feedback clock.

8. The sampling system for the motor phase current according to claim 7, characterized in that, The first inductance module, the second inductance module and the third inductance module all include magnetic beads, and the number of magnetic beads of the first inductance module, the second inductance module and the third inductance module is the same.

9. The sampling system for the motor phase current according to claim 7, characterized in that, The first inverter module, the second inverter module, and the third inverter module each include an inverter, and the number of inverters in the first inverter module, the second inverter module, and the third inverter module is the same.

10. A motor driver, characterized in that, The motor driver includes the sampling system for the motor phase current as described in any one of claims 1-9.

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