Warning generation circuit

Abstract

The invention provides a warning generating circuit. The warning generating circuit comprises a first phase inverter, a first delay circuit, a first logic circuit, a first trigger and an interrupt circuit, the first inverter inverts the time coincidence signal to generate an inverted time coincidence signal. The first delay circuit delays the inverted time coincidence signal to generate a first delay signal. The first logic circuit generates a trigger signal based on the time coincidence signal and the first delay signal. The first trigger sets the warning flag to be valid based on a signal source of the trigger signal. The interrupt circuit sets the interrupt signal to be valid based on the warning flag being valid. The first inverter, the first delay circuit, and the first logic circuit are configured to update the trigger signal only once within a predetermined time.

Description

Technical Field

[0001] The present invention relates to a warning generation circuit for a real-time clock (RTC). Background Art

[0002] A real-time clock (RTC) is an electronic device that outputs the actual time like a clock. Generally, it is an integrated circuit, so it is also called a clock chip. Usually, this electronic device is provided in a personal computer, a server, or an embedded system to accurately record time, and many systems that require accurate time have this function.

[0003] With the RTC counting time, setting a target time and generating a warning is a very common application. When the minimum scale of the set target time is minutes and seconds, the warning generation circuit usually issues a warning once per second until the current time exceeds the set target time. However, the warning once per second will cause trouble to the user, so it is necessary to optimize the warning generation circuit. Summary of the Invention

[0004] The present invention provides a warning generation circuit, which effectively solves the problem of the warning generation circuit generating an interrupt signal once per second. In addition, the warning generation circuit of the present invention further includes an automatic clearing circuit for automatically clearing the interrupt signal, which helps to reduce the burden on the host for periodically clearing the interrupt signal. Furthermore, the warning generation circuit of the present invention can also selectively clear the warning flag and the interrupt signal individually, so that after the interrupt signal is automatically cleared, the host can know that the interrupt signal comes from the time warning of the real-time clock circuit according to the warning flag. In addition, the present invention also maintains the possibility that the host can separately clear the warning flag and the interrupt signal, making the invalidation method of the warning flag and the interrupt signal more flexible.

[0005] In view of this, the present invention provides a warning generation circuit. The warning generation circuit includes a first inverter, a first delay circuit, a first logic circuit, a first flip-flop, and an interrupt circuit. The first inverter inverts a time coincidence signal to generate an inverted time coincidence signal. The first delay circuit delays the inverted time coincidence signal to generate a first delay signal. The first logic circuit generates a trigger signal based on the time coincidence signal and the first delay signal. The first flip-flop sets a warning flag to be valid based on the signal source of the trigger signal. The interrupt circuit sets an interrupt signal to be valid based on the warning flag being valid. The first inverter, the first delay circuit, and the first logic circuit are used to update the trigger signal only once within a first predetermined time. Brief Description of the Drawings

[0006] Figure 1 Shows a block diagram of an electronic circuit according to an embodiment of the present invention;

[0007] Figure 2 Shows a circuit diagram of an alarm generation circuit according to an embodiment of the present invention;

[0008] Figure 3 Shows a circuit diagram of a time comparison circuit according to an embodiment of the present invention;

[0009] Figures 4A - 4B Shows a timing diagram of an alarm generation circuit according to an embodiment of the present invention;

[0010] Figure 5 Shows a block diagram of an electronic circuit according to another embodiment of the present invention;

[0011] Figure 6 Shows a circuit diagram of an alarm generation circuit according to another embodiment of the present invention; and

[0012] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D Shows a timing diagram of an alarm generation circuit according to another embodiment of the present invention.

[0013] Reference Numerals

[0014] 100, 500: Electronic circuit

[0015] 110, 510: Real-time clock circuit

[0016] 111, 511: Alarm generation circuit

[0017] 120: Host

[0018] 200, 600: Alarm generation circuit

[0019] 201: Time comparison circuit

[0020] 202: First delay circuit

[0021] 203: First logic circuit

[0022] 204, 604: Interrupt circuit

[0023] 300: Time comparison circuit

[0024] 301: Second logic circuit

[0025] 610: Automatic clearing circuit

[0026] 611: Second delay circuit

[0027] 612: Pulse generator

[0028] 613: Second logic circuit

[0029] TC: Current time

[0030] TS: Set time

[0031] AF: Warning flag

[0032] INT: Interrupt signal

[0033] CLR: Clear signal

[0034] INV1: First inverter

[0035] FF1: First flip-flop

[0036] ATM: Time coincidence signal

[0037] IATM: Inverted time coincidence signal

[0038] DR: Driver

[0039] DP: Predetermined time

[0040] SEL1: First selection signal

[0041] DL1: First delay signal

[0042] DL2: Second delay signal

[0043] SU: Second update signal

[0044] UD: Update signal

[0045] TRI: Trigger signal

[0046] CMP1: First comparator

[0047] CMP2: Second comparator

[0048] CMP3: Third comparator

[0049] TCH: Current hour

[0050] TCM: Current minute

[0051] TCS: Current second

[0052] TSH: Set hour

[0053] TSM: Set minute

[0054] TSS: Set second

[0055] HM: Hour coincidence signal

[0056] MM: Minute coincidence signal

[0057] SM: Second coincidence signal

[0058] OR1: First OR gate

[0059] OR2: Second OR gate

[0060] OR3: Third OR gate

[0061] HDC: Hour ignore signal

[0062] MDC: Minute ignore signal

[0063] SDC: Second ignore signal

[0064] AND1: First AND gate

[0065] AND2: Second AND gate

[0066] AND3: Third AND gate

[0067] SL1: First logic signal

[0068] SL2: Second logic signal

[0069] SL3: Third logic signal

[0070] EXT_FCLR: External flag clear signal

[0071] EXT_INT_CLR: External interrupt clear signal

[0072] FF2: Second flip-flop

[0073] D: Input terminal

[0074] Q: Output terminal

[0075] RST: Reset terminal

[0076] INV2: Second inverter

[0077] MUX2: Second multiplexer

[0078] MUX3: Third multiplexer

[0079] MUX4: Fourth multiplexer

[0080] SIM: Pulse signal

[0081] ISIM: Inverted pulse signal

[0082] SEL2: Second selection signal

[0083] INT_CLR1: First interrupt clear signal

[0084] INT_CLR2: Second interrupt clear signal

[0085] BCLR: Simultaneous clear signal

[0086] FCLR: Flag clear signal

[0087] TS: Set time

[0088] TC: Current time

[0089] MUX1: First multiplexer Detailed implementation manners

[0090] The following description is of an embodiment of the present disclosure. Its purpose is to exemplify the general principles of the present disclosure and should not be regarded as a limitation of the present disclosure. The scope of the present disclosure shall be defined by the claims.

[0091] It should be noted that the content disclosed below can provide multiple embodiments or examples for practicing different features of the present disclosure. The specific element examples and arrangements described below are only used to briefly elaborate the spirit of the present disclosure and are not used to limit the scope of the present disclosure. In addition, the following specification may reuse the same element symbols or words in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0092] In addition, the descriptions in the following specification such as one feature being connected to, coupled to, and / or formed on another feature etc. may actually include multiple different embodiments, including these features being in direct contact, or including other additional features formed between these features etc., such that these features are not in direct contact.

[0093] Some embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn to the scale of actual devices and elements. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present disclosure. In addition, the structures and devices in the drawings are shown schematically to clearly show the features of the embodiments of the present disclosure.

[0094] In the drawings, similar elements and / or features may have the same element symbols. Various elements of the same type can be distinguished by adding letters or numbers after the element symbols for distinguishing similar elements and / or similar features.

[0095] Figure 1 Displays a block diagram of an electronic circuit according to an embodiment of the present invention. As Figure 1As shown, the electronic circuit 100 includes a real-time clock circuit 110 and a host 120. The real-time clock circuit 110 is used to count time to generate the current time TC, and provide the current time TC to the host 120. The user sets the set time TS through a man-machine interface, and the host 120 provides the set time TS input by the user to the real-time clock circuit 110.

[0096] As Figure 1 shown, the real-time clock circuit 110 includes a warning generation circuit 111. The warning generation circuit 111 compares the current time TC and the set time TS, and when the current time TC coincides with the set time TS, generates a valid warning flag AF and an interrupt signal INT. The host 120 issues a warning based on the valid interrupt signal INT, and determines that the interrupt signal INT is generated because the current time TC coincides with the set time TS according to the valid warning flag AF.

[0097] In addition, the host 120 can invalidate at least one of the warning flag AF and the interrupt signal INT by using a clear signal CLR. As Figure 1 shown, the host 120 further provides a second update signal SU and a first selection signal SEL1 to the warning generation circuit 111, and the detailed operations will be described in detail below. According to some embodiments of the present invention, the host 120 is a central processing unit or a microprocessor.

[0098] Figure 2 Show the circuit diagram of the warning generation circuit according to an embodiment of the present invention. As Figure 2 shown, the warning generation circuit 200 includes a time comparison circuit 201, a first inverter INV1, a first delay circuit 202, a first logic circuit 203, a first flip-flop FF1, and an interrupt circuit 204. According to an embodiment of the present invention, the warning generation circuit 200 corresponds to Figure 1 the warning generation circuit 111.

[0099] The time comparison circuit 201 is used to compare whether the current time TC coincides with the set time TS. When the current time TC coincides with the set time TS, the time coincidence signal ATM generated by the time comparison circuit 201 is valid (assertion). Otherwise, the time coincidence signal ATM is invalid (deassertion).

[0100] The first inverter INV1 inverts the time coincidence signal ATM to generate an inverted time coincidence signal IATM. The first delay circuit 202 delays the inverted time coincidence signal IATM to generate a first delay signal DL1. The first multiplexer MUX1 selects one of the first delay signal DL1 and the second update signal SU as the update signal UD based on the first selection signal SEL1. According to some embodiments of the present invention, the period of the second update signal SU is 1 second. According to some embodiments of the present invention, the second update signal SU can be externally provided by the warning generation circuit 200.

[0101] The first logic circuit 203 generates a trigger signal TRI based on the time coincidence signal ATM and the update signal UD. According to an embodiment of the present invention, the first logic circuit 203 includes a first AND gate AND1. The first AND gate AND1 performs a logical AND operation on the time coincidence signal ATM and the update signal UD to generate the trigger signal TRI. In other words, when both the time coincidence signal ATM and the update signal UD are at a high logic level, the trigger signal TRI is at a high logic level.

[0102] The first flip-flop FF1 sets the warning flag AF to valid based on the source of the trigger signal TRI, and sets the warning flag AF to invalid based on the clear signal CLR provided by the host 120. In Figure 2 the embodiment, the first flip-flop FF1 outputs the logic 1 (i.e., high logic level) at the input terminal D of the first flip-flop FF1 to the output terminal Q based on the rising edge of the trigger signal TRI, thereby setting the warning flag AF to valid (which can be regarded as setting the warning flag AF to a high logic level), and invalidates the warning flag AF to a low logic level based on the clear signal CLR input to the reset terminal RST of the first flip-flop FF1 being at a low logic level.

[0103] The interrupt circuit 204 sets the interrupt signal INT to valid based on the warning flag AF being valid. According to some embodiments of the present invention, Figure 1 the host 120 issues a warning based on the interrupt signal INT being valid. In Figure 2 the embodiment, the interrupt circuit 204 includes a driver DR. The driver DR generates the interrupt signal INT based on the warning flag AF, where the interrupt signal INT and the warning flag AF are in phase. In other words, when the warning flag AF is valid, the interrupt signal INT is valid; when the warning flag AF is invalid, the interrupt signal IINT is invalid.

[0104] According to some embodiments of the present invention, the first inverter INV1, the first delay circuit 202, and the first logic circuit 203 are used to update the trigger signal TRI only once within a predetermined time, where the predetermined time is determined by the set time TS. According to some embodiments of the present invention, when the seconds of the set time TS are ignored, the predetermined time is 1 minute. According to other embodiments of the present invention, when the minutes of the set time TS are ignored, the predetermined time is 1 hour.

[0105] Figure 3 Shows a circuit diagram of a time comparison circuit according to an embodiment of the present invention. According to some embodiments of the present invention, Figure 3 the time comparison circuit 300 corresponds to Figure 2 the time comparison circuit 201. As Figure 3 shown, the time comparison circuit 300 includes a first comparator CMP1, a second comparator CMP2, and a third comparator CMP3. According to an embodiment of the present invention, Figure 1 the current time TC includes the current hour TCH, the current minute TCM, and the current second TCS, and the set time TS includes the set hour TSH, the set minute TSM, and the set second TSS.

[0106] The first comparator CMP1 is used to compare the current hour TCH of the current time TC and the set hour TSH of the set time TS, where when the current hour TCH coincides with the set hour TSH, the first comparator CMP1 sets the hour coincidence signal HM to valid. The second comparator CMP2 is used to compare the current minute TCM and the set minute TSM, where when the current minute TCM of the current time TC and the set minute TSM of the set time TS coincide, the second comparator CMP2 sets the minute coincidence signal MM to valid. The third comparator CMP3 is used to compare the current second TCS of the current time TC and the set second TSS of the set time TS, where when the current second TCS of the current time TC coincides with the set second TSS of the set time TS, the third comparator CMP3 sets the second coincidence signal SM to valid.

[0107] As Figure 3 shown, the time comparison circuit 300 further includes a first OR gate OR1, a second OR gate OR2, and a third OR gate OR3. The first OR gate OR1 performs a logical OR operation on the hour coincidence signal HM and the hour ignore signal HDC to generate a first logic signal SL1. The second OR gate OR2 performs a logical OR operation on the minute coincidence signal MM and the minute ignore signal MDC to generate a second logic signal SL2. The third OR gate OR3 performs a logical OR operation on the second coincidence signal SM and the second ignore signal SDC to generate a third logic signal SL3.

[0108] According to some embodiments of the present invention, when any one of the hour ignore signal HDC, the minute ignore signal MDC, and the second ignore signal SDC is valid, it represents that the comparison of the current time TC and the set time TS in hours, minutes, or seconds is not performed. For example, when the second ignore signal SDC is valid, only the first comparator CMP1 and the second comparator CMP2 perform the comparison and the third comparator CMP3 does not operate.

[0109] In other words, when the hour ignore signal HDC is at a high logic level, whether the current hour TCH coincides with the set hour TSH is not considered. When the minute ignore signal MDC is at a high logic level, whether the current minute TCM and the set minute TSM coincide is not considered. When the second ignore signal SDC is at a high logic level, whether the current second TCS and the set second TSS coincide is not considered.

[0110] As Figure 3 shown, the time comparison circuit 300 further includes a second logic circuit 301. When the first logic signal SL1, the second logic signal SL2, and the third logic signal SL3 are all valid, the second logic circuit 301 generates a valid time coincidence signal ATM. According to an embodiment of the present invention, the second logic circuit 301 includes a second AND gate AND2. The second AND gate AND2 performs a logical AND operation on the first logic signal SL1, the second logic signal SL2, and the third logic signal SL3 to generate the time coincidence signal ATM.

[0111] In Figure 3 the embodiment, hours, minutes, and seconds are taken as examples for explanation and are not limited thereto in any form. For example, the current time TC and the set time TS may further include year, month, and day. When the year, month, day, hour, minute, and second of the current time TC and the set time TS all coincide with each other (or at least one of the year, month, day, hour, minute, and second can be ignored), the time comparison circuit 300 sets the time coincidence signal ATM to be valid. In the following description, hours, minutes, and seconds will be taken as examples for explanation and are not limited thereto in any form.

[0112] Figures 4A - 4B Show the timing diagram of the warning generation circuit according to an embodiment of the present invention. The following description of Figures 4A - 4B will be combined with Figure 1 , Figure 2 and Figure 3 for detailed explanation.

[0113] As Figure 4AAs shown, the first selection signal SEL1 is logic 0 (i.e., low logic level or invalid), the set time TS is 13:00:XX, where XX represents negligible. In other words, the first multiplexer MUX1 selects the second update signal SU as the update signal UD based on the first selection signal SEL1. In Figure 3 the second ignore signal SDC is logic 1 (i.e., high logic level), so the third comparator CMP3 does not compare the current second TCS and the set second TSS.

[0114] As Figure 4A shown, when the current time TC is 13:00:00, the time match signal ATM is high logic level and lasts until the current time TC is 13:00:59. Since the period of the second update signal SU is 1 second, and the time match signal ATM is high logic level from the current time TC of 13:00:00 to 13:00:59, the waveform of the trigger signal TRI is approximately the same as the second update signal SU.

[0115] Referring to Figure 2 , since the first flip-flop FF1 outputs logic 1 (i.e., high logic level) to the output terminal Q based on the rising edge of the trigger signal TRI, the warning flag AF becomes high logic level, as Figure 4A shown. Since the interrupt signal INT is in phase with the warning flag AF, the host 120 issues a warning based on the interrupt signal INT. Then, after the warning flag AF maintains the high logic level for a predetermined time DP, the host 120 issues a clear signal CLR to reset the warning flag AF, making the warning flag AF return to the low logic level.

[0116] As Figure 4A shown, when the current time TC matches the set time TS, the warning flag AF and the interrupt signal INT become valid along with the second update signal SU. In other words, when the set time TS ignores the seconds, the warning flag AF and the interrupt signal INT become valid once per second, causing the host 120 to issue a warning based on the interrupt signal INT every second.

[0117] As Figure 4B shown, the first selection signal SEL1 is logic 1 (i.e., high logic level), the set time TS is 13:00:XX, where XX represents negligible. In other words, the first multiplexer MUX1 selects the first delay signal DL1 as the update signal UD based on the first selection signal SEL1. Since Figure 4B the set time TS of Figure 4A is the same as the set time TS of

[0118] As Figure 4BAs shown, when the current time TC is 13:00:00, the time coincidence signal ATM is at a high logic level and remains so until the current time TC is 13:00:59. Since the first delay signal DL1 is only valid once near the rising edge of the time coincidence signal ATM between 13:00:00 and 13:00:59, the trigger signal TRI becomes valid based on the time coincidence signal ATM transitioning from a low logic level to a high logic level. Subsequently, the warning flag AF and the interrupt signal INT become valid based on the valid trigger signal TRI, and the host 120 issues a clear signal CLR after a predetermined time DP to invalidate the warning flag AF and the interrupt signal INT.

[0119] In other words, since the warning flag AF and the interrupt signal INT are only valid once during the period when the time coincidence signal ATM is valid, it means that the host 120 issues a warning only once during the period when the time coincidence signal ATM is valid. Therefore, through Figure 2 the first inverter INV1, the first delay circuit 202, and the first logic circuit 203, the trouble of issuing a warning once per second can be eliminated.

[0120] Figure 5 Shows a block diagram of an electronic circuit according to another embodiment of the present invention. The Figure 5 electronic circuit 500 is compared with the Figure 1 electronic circuit 100. The real-time clock circuit 110 and the warning generation circuit 111 are respectively replaced by the real-time clock circuit 510 and the warning generation circuit 511, and the host 120 provides an external flag clear signal EXT_FCLR and an external interrupt clear signal EXT_INT_CLR to the warning generation circuit 511 of the real-time clock circuit 510. In addition, the host 120 further provides a second update signal SU, a first selection signal SEL1, a second selection signal SEL2, and a third selection signal SEL3 to the warning generation circuit 511, the detailed operations of which will be described in detail below.

[0121] Figure 6 Shows a circuit diagram of a warning generation circuit according to another embodiment of the present invention. According to some embodiments of the present invention, the warning generation circuit 600 corresponds to the Figure 5 warning generation circuit 511. Compared with the Figure 2 warning generation circuit 200, the interrupt circuit 604 replaces the Figure 2 interrupt circuit 204, and the warning generation circuit 600 further includes an automatic clear circuit 610.

[0122] As Figure 6As shown, the interrupt circuit 604 includes a second flip-flop FF2. The second flip-flop FF2 outputs the logic 1 (i.e., high logic level) at the input terminal D to the output terminal Q based on the trigger signal TRI being active, such that the interrupt signal INT is active. In addition, the second flip-flop FF2 resets the interrupt signal INT to a low logic level based on the second interrupt clear signal INT_CLR2 input to the reset terminal RST of the second flip-flop FF2 being at a low logic level (or inactive).

[0123] As Figure 6 shown, the automatic clear circuit 610 includes a second delay circuit 611, a pulse generator 612, a second inverter INV2, a second multiplexer MUX2, a third multiplexer MUX3, a second logic circuit 613, and a fourth multiplexer MUX4. The second delay circuit 611 delays the interrupt signal INT and generates a second delay signal DL2. The pulse generator 612 generates a pulse signal SIM based on the signal source of the second delay signal DL2.

[0124] The second inverter INV2 inverts the pulse signal SIM and generates an inverted pulse signal ISIM. The second multiplexer MUX2 selects either the external interrupt clear signal EXT_INT_CLR or the inverted pulse signal ISIM as the first interrupt clear signal INT_CLR1 based on the second selection signal SEL2. According to some embodiments of the present invention, the second flip-flop FF2 of the interrupt circuit 604 invalidates the interrupt signal INT based on the first interrupt clear signal INT_CLR1.

[0125] The third multiplexer MUX3 selects either the first interrupt clear signal INT_CLR1 or the simultaneous clear signal BCLR as the second interrupt clear signal INT_CLR2 based on the third selection signal SEL3. According to some embodiments of the present invention, the second interrupt clear signal INT_CLR2 is input to the reset terminal RST of the second flip-flop FF2, and when the second interrupt clear signal INT_CLR2 is inactive, the second flip-flop FF2 invalidates the interrupt signal INT.

[0126] The second logic circuit 613 activates the simultaneous clear signal BCLR based on both the external flag clear signal EXT_FCLR and the first interrupt clear signal INT_CLR1 being active. In Figure 6 an embodiment, the second logic circuit 613 includes a third AND gate AND3. The third AND gate AND3 performs a logical AND operation on the external flag clear signal EXT_FCLR and the first interrupt clear signal INT_CLR1 to generate the simultaneous clear signal BCLR.

[0127] Figures 7A - 7D Shows a timing diagram of the warning generation circuit according to another embodiment of the present invention. The following is forFigures 7A - 7D The description will be paired with Figure 2 , Figure 5 and Figure 6 for detailed illustration.

[0128] As Figure 7A shown, the first selection signal SEL1, the second selection signal SEL2, and the third selection signal SEL3 are all logic 0 (i.e., low logic level), the setting time TS is 13:00:XX, where XX represents negligible. Therefore, the first multiplexer MUX1 selects the second update signal SU as the update signal UD, the second multiplexer MUX2 selects the external interrupt clear signal EXT_INT_CLR as the first interrupt clear signal INT_CLR1, the third multiplexer MUX3 selects the simultaneous clear signal BCLR as the second interrupt clear signal INT_CLR2, and the fourth multiplexer MUX4 selects the simultaneous clear signal BCLR as the flag clear signal FCLR.

[0129] As Figure 7A shown, when the current time TC is 13:00:00, the time match signal ATM is at a high logic level (i.e., valid) and remains so until the current time TC is 13:00:59. Since the period of the second update signal SU is 1 second, and the time match signal ATM is at a high logic level from the current time TC of 13:00:00 to 13:00:59, the waveform of the trigger signal TRI is approximately the same as that of the second update signal SU.

[0130] As Figure 7B shown, the first selection signal SEL1 is logic 1 (i.e., high logic level or valid), the second selection signal SEL2 and the third selection signal SEL3 are both logic 0 (i.e., low logic level or invalid), the setting time TS is 13:00:XX, where XX represents negligible. In other words, the first multiplexer MUX1 selects the first delay signal DL1 as the update signal UD based on the first selection signal SEL1, the second multiplexer MUX2 selects the external interrupt clear signal EXT_INT_CLR as the first interrupt clear signal INT_CLR1, the third multiplexer MUX3 selects the simultaneous clear signal BCLR as the second interrupt clear signal INT_CLR2, and the fourth multiplexer MUX4 selects the simultaneous clear signal BCLR as the flag clear signal FCLR. Since Figure 7B the setting time TS of Figure 7A is the same as that of

[0131] As Figure 7BAs shown, when the current time TC is 13:00:00, the time coincidence signal ATM is at a high logic level (i.e., valid), and it lasts until the current time TC is 13:00:59. Since the first delay signal DL1 and the update signal UD are only valid once near the rising edge of the time coincidence signal ATM between 13:00:00 and 13:00:59, the trigger signal TRI becomes valid based on the transition of the time coincidence signal ATM from a low logic level to a high logic level.

[0132] As Figure 7C shown, the first selection signal SEL1 and the second selection signal SEL2 are at logic 1 (i.e., high logic level), the third selection signal SEL3 is at logic 0 (i.e., low logic level), and the set time TS is 13:00:XX, where XX represents negligible. In other words, the first multiplexer MUX1 selects the first delay signal DL1 as the update signal UD based on the first selection signal SEL1, the second multiplexer MUX2 selects the inverted pulse signal ISIM as the first interrupt clear signal INT_CLR1, the third multiplexer MUX3 selects the simultaneous clear signal BCLR as the second interrupt clear signal INT_CLR2, and the fourth multiplexer MUX4 selects the simultaneous clear signal BCLR as the flag clear signal FCLR. Since Figure 7B the set time TS of Figure 7A and Figure 7B is the same as that of

[0133] As Figure 7C shown, since the waveform diagram of the trigger signal TRI is the same as that of Figure 7B , it will not be repeated here. Since in Figure 7C the second multiplexer MUX2 selects the inverted pulse signal ISIM as the first interrupt clear signal INT_CLR1, regardless of the logic state of the external flag clear signal EXT_FCLR, the invalid first interrupt clear signal INT_CLR1 generates an invalid simultaneous clear signal BCLR through the third AND gate AND3.

[0134] As Figure 7D shown, the first selection signal SEL1, the second selection signal SEL2, and the third selection signal SEL3 are all at logic 1 (i.e., high logic level), and the set time TS is the same as that of Figures 7A - 7CThe same applies and will not be repeated here. In other words, the first multiplexer MUX1 selects the first delay signal DL1 as the update signal UD based on the first selection signal SEL1. The second multiplexer MUX2 selects the inverted pulse signal ISIM as the first interrupt clear signal INT_CLR1. The third multiplexer MUX3 selects the first interrupt clear signal INT_CLR1 as the second interrupt clear signal INT_CLR2. The fourth multiplexer MUX4 selects the external flag clear signal EXT_FCLR as the flag clear signal FCLR. In addition, the external flag clear signal EXT_FCLR is provided by the host 120.

[0135] As Figure 7D shown, since the waveform diagram of the trigger signal TRI is the same as Figure 7B and Figure 7C the same, it will not be repeated here. In Figure 7D , since the second multiplexer MUX2 selects the inverted pulse signal ISIM as the first interrupt clear signal INT_CLR1 and the third multiplexer MUX3 selects the first interrupt clear signal INT_CLR1 as the second interrupt clear signal INT_CLR2, it means that the automatic clear circuit 610 generates a falling edge of the second interrupt clear signal INT_CLR2 based on the rising edge of the interrupt signal INT, thereby invalidating the interrupt signal INT.

[0136] In summary, for Figures 7A - 7D described above, Figure 6 the automatic clear circuit 610 can invalidate the interrupt signal INT based on the rising edge of the interrupt signal INT, or invalidate the interrupt signal INT and the warning flag AF simultaneously. In addition, the warning flag AF and the interrupt signal INT can be invalidated separately by controlling the second multiplexer MUX2, the third multiplexer MUX3, and the fourth multiplexer MUX4. Moreover, the warning flag AF and the interrupt signal INT can be invalidated separately by the external flag clear signal EXT_FCLR and the external interrupt clear signal EXT_INT_CLR provided by the host 120.

[0137] The present invention proposes a warning generation circuit, which effectively solves the problem of the warning generation circuit generating an interrupt signal once per second. In addition, the warning generation circuit of the present invention further includes an automatic clear circuit for automatically clearing the interrupt signal, which helps to reduce the burden on the host to periodically clear the interrupt signal. Furthermore, the warning generation circuit of the present invention can also selectively clear the warning flag and the interrupt signal individually, so that after the interrupt signal is automatically cleared, the host can know from the warning flag that the interrupt signal comes from the time warning of the real-time clock circuit. In addition, the present invention also maintains the possibility that the host can clear the warning flag and the interrupt signal separately, making the invalidation method of the warning flag and the interrupt signal more flexible.

[0138] Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosure content of some embodiments of the present disclosure. As long as they can perform substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. A warning generation circuit, characterized in that, Comprising: A first inverter that inverts a time coincidence signal to generate an inverted time coincidence signal; A first delay circuit that delays the inverted time coincidence signal to generate a first delay signal; A first logic circuit that generates a trigger signal based on the time coincidence signal and the first delay signal; A first flip-flop that enables a warning flag based on the source of the trigger signal; and An interrupt circuit that enables an interrupt signal based on the warning flag being enabled; Wherein the first inverter, the first delay circuit, and the first logic circuit are used to update the trigger signal only once within a first predetermined time.

2. The warning generation circuit according to claim 1, wherein Further comprising: A first multiplexer that selects the first delay signal or a one-second update signal as an update signal according to a selection signal; Wherein when both the time coincidence signal and the update signal are enabled, the first logic circuit enables the trigger signal; Wherein the period of the one-second update signal is 1 second; Wherein the first predetermined time is greater than the period of the one-second update signal; Wherein the first predetermined time is determined by a set time.

3. The warning generation circuit according to claim 2, wherein, When the first multiplexer selects the first delay signal as the update signal, the trigger signal is updated once within the first predetermined time; Wherein when the first multiplexer selects the one-second update signal as the update signal, the trigger signal is updated once per second; Wherein after a second predetermined time after the trigger signal is enabled, a host provides a clear signal to the first flip-flop to invalidate the warning flag and the interrupt signal.

4. The warning generation circuit according to claim 3, wherein The interrupt circuit includes: A driver that generates the interrupt signal based on the warning flag; Wherein when the warning flag is enabled, the interrupt signal is enabled; Wherein when the warning flag is disabled, the interrupt signal is disabled.

5. The warning generation circuit according to claim 2, wherein Further comprising: An automatic clear circuit, including: A second delay circuit that delays the interrupt signal to generate a second delay signal; A pulse generator that generates a pulse signal based on the source of the second delay signal; A second inverter that inverts the pulse signal to generate an inverted pulse signal; and A second multiplexer that selects an external interrupt clear signal or the inverted pulse signal as a first interrupt clear signal; Wherein the interrupt circuit invalidates the interrupt signal based on the first interrupt clear signal.

6. The warning generation circuit according to claim 5, wherein The automatic clear circuit further includes: A third multiplexer that selects the first interrupt clear signal or a simultaneous clear signal as a second interrupt clear signal; A second logic circuit that enables the simultaneous clear signal based on both an external flag clear signal and the first interrupt clear signal being enabled; and A fourth multiplexer that selects the external flag clear signal or the simultaneous clear signal as a flag clear signal.

7. The warning generation circuit according to claim 6, wherein, The interrupt circuit includes: A second flip-flop that enables the interrupt signal based on the source of the trigger signal.

8. The warning generation circuit according to claim 7, wherein The second flip-flop invalidates the interrupt signal based on the second interrupt clear signal; One of the hosts provides the above-mentioned external flag clearing signal and the above-mentioned external interrupt clearing signal.

9. The warning generation circuit according to claim 1, wherein Further comprising: A time comparison circuit compares a current time with a set time to generate the above-mentioned time coincidence signal; Wherein the above-mentioned set time is set by a user; Wherein the above-mentioned time comparison circuit further comprises: A first comparator, wherein when a current hour of the above-mentioned current time is equal to a set hour of the above-mentioned set time, the first comparator sets a time coincidence signal to be valid; A second comparator, wherein when a current minute of the above-mentioned current time is equal to a set minute of the above-mentioned set time, the second comparator sets a minute coincidence signal to be valid; A third comparator, wherein when a current second of the above-mentioned current time is equal to a set second of the above-mentioned set time, the third comparator sets a second coincidence signal to be valid; and A second logic circuit sets the above-mentioned time coincidence signal to be valid based on that the above-mentioned time coincidence signal, the above-mentioned minute coincidence signal, and the above-mentioned second coincidence signal are all valid.

10. The warning generation circuit according to claim 9, wherein, A host determines that the above-mentioned current time is equal to the above-mentioned set time based on that the above-mentioned warning flag is valid; Wherein the host issues a warning based on that the above-mentioned interrupt signal is valid.

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