Embedded PCB and manufacturing method thereof

Abstract

The invention relates to the technical field of printed embedded PCBs, and discloses an embedded PCB and a manufacturing method thereof.The embedded PCB comprises a daughter board, a first dielectric layer and a first circuit layer which are sequentially arranged in a stacked mode in the first direction, a device is embedded in the daughter board, the device is located on the side, close to the first dielectric layer, of the daughter board, and the first dielectric layer is located on the first circuit layer. One side, close to the first dielectric layer, of the device is provided with a first part, and the first part is provided with a first protection part; a first connection hole is formed in the first dielectric layer, a first conductive part is filled in the first connection hole, the first protection part is connected and electrically conducted with the first conductive part, and the first conductive part is connected and electrically conducted with the first circuit layer. The embedded PCB and the manufacturing method thereof provided by the invention are used for improving the problem of poor hole filling in the electroplating hole filling process in the related technology.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit boards, and particularly to an embedded PCB and a manufacturing method thereof. Background Art

[0002] With the continuous development of the electronic communication industry and the in-vehicle electronics industry, they are increasingly tending towards miniaturization and multi-functionality. Therefore, the requirements for related PCB (Printed Circuit Board) products are also getting higher and higher. The PCB not only needs to meet the working environment of high current, have ultra-high voltage resistance performance and excellent CAF (Conductive Anodic Filament) resistance requirements, but also needs to achieve high-density interconnection, and at the same time needs to have excellent heat dissipation performance. Therefore, for a PCB that meets the above requirements, devices (such as chips or heat sinks, etc.) are embedded in a multi-layer PCB to achieve related requirements. While making it have good heat dissipation performance, the dielectric layer close to the device also needs to reach a certain thickness.

[0003] In related technologies, to meet the requirements of high voltage resistance and excellent CAF resistance, it is necessary to increase the thickness of the dielectric layer close to the device. Subsequently, holes are drilled through this dielectric layer to the device, and then electroplating is carried out to fill the holes and conduct the device. However, problems of poor hole filling will occur during the electroplating hole filling process. Summary of the Invention

[0004] This application provides an embedded PCB and a manufacturing method thereof, which are used to improve the problem of poor hole filling during the electroplating hole filling process in related technologies.

[0005] In a first aspect, an embodiment of this application provides an embedded PCB, including a sub-board, a first dielectric layer, and a first circuit layer that are sequentially and stacked along a first direction. A device is embedded inside the sub-board, and the device is located on a side of the sub-board close to the first dielectric layer. A first part is provided on a side of the device close to the first dielectric layer, and a first protection part is provided on the first part; a first connection hole is provided inside the first dielectric layer, and a first conductive part is filled inside the first connection hole. The first protection part is connected to and electrically conductive with the first conductive part, and the first conductive part is connected to and electrically conductive with the first circuit layer.

[0006] In some of these embodiments, the embedded PCB further includes a second dielectric layer and a second circuit layer that are stacked. The second dielectric layer is located between the first circuit layer and the second circuit layer. A second connection hole is provided inside the second dielectric layer, and a second conductive part is filled inside the second connection hole. The first circuit layer is connected to and electrically conductive with the second conductive part, and the second circuit layer is connected to and electrically conductive with the second conductive part.

[0007] In some embodiments, a second portion is provided on a side of the device away from the first dielectric layer, and a second protective portion is provided on the second portion; the embedded PCB further includes a third dielectric layer and a third circuit layer stacked together, the third dielectric layer being located between the third circuit layer and the daughter board, a third connection hole being provided inside the third dielectric layer, the third connection hole being filled with a third conductive portion, the second protective portion being connected to and electrically conductive with the third conductive portion, and the third circuit layer being connected to and electrically conductive with the third conductive portion.

[0008] In some embodiments, the device includes a heat sink and a chip connected thereto, and the first portion is disposed on the chip; or the device includes a heat sink, and the first portion is disposed on the heat sink.

[0009] In some embodiments, the thickness of the first protection portion is 50 μm-300 μm.

[0010] In a second aspect, an embodiment of the present application provides a method for manufacturing an embedded PCB, comprising: Place the device into the receiving groove of the daughter board, wherein a first portion is provided on one side of the device, a first protective portion is provided on the first portion, and the size of the receiving groove is larger than the size of the device; A first dielectric layer and a first metal layer are stacked in sequence on the daughter board, the daughter board, the first dielectric layer and the first metal layer are arranged in sequence along a first direction, and the first portion is located on a side of the device close to the first dielectric layer; Laminating the daughter board, the device, the first dielectric layer, and the first metal layer together, with a portion of the first dielectric layer filling a gap between an inner wall of the receiving groove and the device; A first filling hole penetrating the first metal layer and a first connection hole penetrating the first dielectric layer are processed on a side of the first metal layer facing away from the first dielectric layer, the first connection hole and the first filling hole being coaxially arranged, and the first protective portion defining a bottom surface of the first connection hole; The first conductive part is filled in the first connecting hole by copper electroplating, and the first filling part is filled in the first filling hole by copper electroplating. The first conductive part is connected to the first filling part and is electrically conductive. The first metal layer and the first filling part constitute a first circuit layer.

[0011] In some embodiments, after filling the first conductive portion in the first connection hole, the method for manufacturing the embedded PCB further includes: A second dielectric layer and a second metal layer are sequentially stacked on the first circuit layer, and the second dielectric layer is located between the first circuit layer and the second metal layer; A second filling hole penetrating through the second metal layer and a second connection hole penetrating through the second dielectric layer are processed on a side of the second metal layer facing away from the second dielectric layer. The second connection hole and the second filling hole are coaxially arranged, and the first circuit layer defines a bottom surface of the second connection hole; The second connection hole is filled with a second conductive part by means of electroless copper plating, and the second filling hole is filled with a second filling part by means of electroless copper plating. The second conductive part is connected to and electrically conductive with the second filling part, and the second metal layer and the second filling part form a second circuit layer.

[0012] In some embodiments, before processing a first filling hole penetrating through the first metal layer and a first connection hole penetrating through the first dielectric layer on a side of the first metal layer facing away from the first dielectric layer, the thickness H0 of the first protection part and the thickness H1 of the first dielectric layer are obtained. The difference between H1 and H0 is H; the aperture of the first connection hole is D, and D is greater than 1.25*H.

[0013] In some embodiments, the first part is a pad; before placing the device into the accommodation groove of the daughter board, the first protection part is fabricated on the first part by means of electroplating or soldering; Alternatively, the device includes a heat sink, and one side of the heat sink includes a first forming part and a second forming part; before placing the device into the accommodation groove of the daughter board, a part of the second forming part is removed so that the first forming part protrudes from the remaining second forming part, and the second forming part includes the first part and the first protection part.

[0014] In some embodiments, the daughter board includes a first core board, a connection dielectric layer, and a second core board which are stacked. The first core board is provided with a first opening window, the connection dielectric layer is provided with a connection opening window, and the second core board is provided with a second opening window. The first opening window, the connection opening window, and the second opening window are connected and define the accommodation groove; when the daughter board, the device, the first dielectric layer, and the first metal layer are laminated together, a part of the connection dielectric layer fills the gap between the inner wall of the accommodation groove and the device.

[0015] The embedded PCB provided by the embodiment of the present application has the beneficial effect that: since a device is embedded inside the daughter board, the device is located on the side of the daughter board close to the first dielectric layer, a first part is provided on the side of the device close to the first dielectric layer, a first protection part is provided on the first part, and a first connection hole is provided inside the first dielectric layer. The inside of the first connection hole is filled with a first conductive part. The first protection part is connected to and electrically conducts with the first conductive part, and the first conductive part is connected to and electrically conducts with the first circuit layer. Therefore, the first part and the first circuit layer can be electrically conducted through the first protection part and the first conductive part, so that during the process of manufacturing the circuit board, when filling the first conductive part in the first connection hole by using the method of immersion copper plating, a depression will not occur at the corresponding position of the first circuit layer, and further, the problem of poor filling of the hole during the electroplating hole filling process can be avoided.

[0016] For the beneficial effect of the manufacturing method of the embedded PCB provided by the present application compared with the prior art, reference can be made to the description of the beneficial effect of the embedded PCB provided by the present application compared with the prior art, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a schematic structural diagram of an embedded PCB in the prior art; Figure 2 is a flowchart of the manufacturing method of the embedded PCB in one embodiment of the present application; Figure 3 is a schematic structural diagram of a daughter board, a device, a first dielectric layer and a first circuit layer in one embodiment of the present application; Figure 4 is in Figure 3 a schematic diagram of filling a first conductive part in the first connection hole shown in and filling a first filling part in the first filling hole; Figure 5 is a schematic structural diagram of an embedded PCB in one embodiment of the present application; Figure 6 is a schematic structural diagram of an embedded PCB in another embodiment of the present application; Figure 7 is a schematic structural diagram of an embedded PCB in yet another embodiment of the present application; Figure 8 is a schematic structural diagram of an embedded PCB in still another embodiment of the present application.

[0019] The meanings of the marks in the figure are as follows: 1. Embedded PCB; 2. Device; 3. Blind hole; 4. Depression; 5. Dielectric layer; 10. Daughter board; 11. First core board; 12. Connecting dielectric layer; 13. Second core board; 20. First dielectric layer; 21. First connection hole; 201. First conductive part; 30. First circuit layer; 300. First metal layer; 31. First filling hole; 301. First filling part; 40. Device; 41. Heat sink; 42. Chip; 401. First part; 402. First protection part; 403. Second part; 404. Second protection part; 50. Second dielectric layer; 501. Second conductive part; 60. Second circuit layer; 601. Second filling part; 70. Third dielectric layer; 80. Third circuit layer; 90. Fourth dielectric layer; 100. Fourth circuit layer. Detailed implementation mode

[0020] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0022] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0023] References to "one embodiment", "some embodiments", or "an embodiment" in the description of this application mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc., which appear in different places in this specification, are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments", unless otherwise specifically emphasized. In addition, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0024] To illustrate the technical solution of this application, the following will be described in conjunction with specific drawings and embodiments.

[0025] With the continuous development of the electronic communication industry and the in-vehicle electronics industry, they are increasingly tending towards miniaturization and multi-functionality. Therefore, the requirements for related PCB products are also getting higher and higher. The PCB not only needs to meet the working environment of high current, have ultra-high voltage resistance performance and excellent CAF resistance requirements, but also needs to achieve high-density interconnection, and at the same time needs to have excellent heat dissipation performance. Therefore, for PCBs that meet the above requirements, devices (such as chips or radiators, etc.) are embedded in multi-layer PCBs to meet the relevant requirements. While enabling good heat dissipation performance, the dielectric layer close to the device also needs to reach a certain thickness.

[0026] Please refer to Figure 1 , in the related art, to meet the requirements of high voltage resistance and excellent CAF resistance, it is necessary to increase the thickness of the dielectric layer 5 close to the device 2. Subsequently, a hole is drilled through this dielectric layer 5 to the device 2, and then electroplating is performed to fill the hole and conduct the device 2.

[0027] On the one hand, when the thickness of the dielectric layer 5 reaches a certain value, the processing difficulty of electroplating to fill the hole increases, and the normal electroplating hole filling process cannot meet its quality requirements. Since the aspect ratio (depth to diameter ratio) of the blind hole 3 exceeds the process capability of the hole filling electroplating line, a core wrapping phenomenon occurs during electroplating to fill the hole, resulting in the embedded PCB 1 being unable to meet the current-carrying requirements of the product. Moreover, the depression 4 at the hole opening after electroplating to fill the hole is too deep, and the flatness of its corresponding pad does not meet the requirements, affecting subsequent welding. At the same time, the too-deep depression 4 will also reduce the heat dissipation performance of the embedded PCB 1. In addition, for the embedded PCB 1 with a stacked via design for multi-order HDI (High Density Interconnector), the depression 4 at the hole opening after electroplating to fill the hole is too deep, unable to meet the design of the interlayer stacked vias, and its design has limitations.

[0028] Meanwhile, when the thickness of the dielectric layer 5 reaches a certain value, to avoid the electroplating of the blind vias 3 with a core or the depression 4 corresponding to the blind vias 3 being too deep, multiple via filling electroplating operations are generally required to barely meet the requirements. This results in low production efficiency, a long production cycle, high production costs, affects the production capacity of the factory, and is not suitable for mass production.

[0029] In summary, in the existing manufacturing method of the embedded PCB 1, problems of poor via filling occur during the electroplating via filling process.

[0030] On the other hand, since a certain amount of space is required for placing the device 2 before embedding, the overall shape of the device 2 is usually smaller than the shape of the receiving groove of the core board of the embedded PCB 1. During lamination, a certain amount of the dielectric layer 5 is required to fill the gap between the inner wall of the receiving groove and the device 2, which may cause part of the dielectric layer 5 in the area where the device 2 is embedded after lamination to flow into the gap between the inner wall of the receiving groove and the device 2, resulting in a certain depression in this area.

[0031] For example, if the device 2 includes a chip, the thickness of the chip's pad is usually less than 15 μm (nickel-gold layer or nickel-copper layer, the copper layer is generally 8 μm - 10 μm, the total thickness of the nickel-gold layer generally does not exceed 5 μm, and the total thickness of the nickel-copper layer generally does not exceed 15 μm). The pad is relatively thin, and the laser drilling energy corresponding to the ultra-thick dielectric layer 5 is relatively large. Also, due to a certain depression in the embedded area after lamination, it is difficult to control the drilling depth of the blind vias 3, and it is easy to break through the chip's pad due to excessive laser energy during drilling. After breakthrough, the chip is damaged and scrapped.

[0032] Meanwhile, to meet the requirements of high voltage resistance and excellent CAF resistance, the thickness of the dielectric layer 5 must be increased from the chip to the circuit layer. When the thickness of the dielectric layer 5 reaches a certain value, it will increase the processing difficulty of the blind vias 3 for interlayer conduction. And when the glue filling in the embedded area from the circuit layer to the chip is insufficient, resulting in depression in this area, the embedded area corresponding to the circuit layer is uneven, and the corresponding area of the blind vias 3 is also uneven. When drilling the hole above the blind vias 3, the board surface is uneven due to the depression in the embedded area, and it is difficult to control the laser drilling energy, resulting in residual glue at the bottom of the hole, which causes delamination between the plating layer and the low copper layer after electroplating, affecting the product reliability.

[0033] In summary, in the existing manufacturing method of the embedded PCB 1, it is difficult to control the depth of the hole during the drilling process, and it is easy to break through the pad of the device 2 due to excessive laser energy during drilling, resulting in scrapping of the device 2.

[0034] In view of this, an embodiment of the present application provides an embedded PCB and a manufacturing method thereof. Since a device is embedded inside the daughter board, the device is located on one side of the daughter board close to the first dielectric layer. A first part is provided on the side of the device close to the first dielectric layer, a first protection part is provided on the first part, and a first connection hole is provided inside the first dielectric layer. A first conductive part is filled inside the first connection hole. The first protection part is connected to and electrically conductive with the first conductive part, and the first conductive part is connected to and electrically conductive with the first circuit layer. Therefore, the first part and the first circuit layer can be electrically conducted through the first protection part and the first conductive part, so as to avoid the depression at the corresponding position of the first circuit layer when filling the first conductive part in the first connection hole by using the method of electroless copper plating during the process of manufacturing the circuit board, and further avoid the problem of poor filling during the electroplating hole filling process.

[0035] Please refer to Figures 2 to 5 , an embodiment of the present application provides an embedded PCB, including a daughter board 10, a first dielectric layer 20, and a first circuit layer 30 that are sequentially stacked along a first direction. A device 40 is embedded inside the daughter board 10. The device 40 is located on one side of the daughter board 10 close to the first dielectric layer 20. A first part 401 is provided on the side of the device 40 close to the first dielectric layer 20, and a first protection part 402 is provided on the first part 401.

[0036] The material of the first dielectric layer 20 can be PP (Prepreg, semi-cured sheet), etc., and the material of the first circuit layer 30 can be copper, silver, or aluminum, etc. The device 40 can include a chip 42 and / or a heat sink 41, and one or more devices 40 can be provided. The first part 401 can be one of the parts of the device 40. The material of the first protection part 402 can be copper, silver, or aluminum, etc. The first protection part 402 and the first part 401 can be integrally formed or separately provided, and one or more first parts 401 can be provided.

[0037] A first connection hole 21 is provided inside the first dielectric layer 20, a first conductive part 201 is filled inside the first connection hole 21, the first protection part 402 is connected to and electrically conductive with the first conductive part 201, and the first conductive part 201 is connected to and electrically conductive with the first circuit layer 30.

[0038] The material of the first conductive part 201 can be copper, silver, or aluminum, etc. For example, the materials of the first conductive part 201, the first protection part 402, and the first circuit layer 30 are all copper.

[0039] The manufacturing method of the embedded PCB provided in the above embodiment includes: S100: Place the device 40 into the accommodation groove of the daughter board 10. A first part 401 is provided on one side of the device 40, and a first protection part 402 is provided on the first part 401. The size of the accommodation groove is larger than the size of the device 40.

[0040] S200: Stack the first dielectric layer 20 and the first metal layer 300 on the daughter board 10 in sequence. The daughter board 10, the first dielectric layer 20, and the first metal layer 300 are arranged in sequence along the first direction. The first part 401 is located on the side of the device 40 close to the first dielectric layer 20.

[0041] Specifically, the daughter board 10, the first dielectric layer 20, and the first metal layer 300 can be riveted together.

[0042] S300: Press the daughter board 10, the device 40, the first dielectric layer 20, and the first metal layer 300 together. Part of the first dielectric layer 20 fills the gap between the inner wall of the accommodating groove and the device 40.

[0043] Specifically, due to the existence of the first protection part 402, the embedded areas of the first dielectric layer 20 and the first metal layer 300 corresponding to the device 40 will not sink due to part of the first dielectric layer 20 filling the gap between the inner wall of the accommodating groove and the device 40, and the overall board surface is flat.

[0044] S400: Process a first filling hole 31 penetrating the first metal layer 300 and a first connection hole 21 penetrating the first dielectric layer 20 from the side of the first metal layer 300 facing away from the first dielectric layer 20. The first connection hole 21 and the first filling hole 31 are coaxially arranged, and the first protection part 402 defines the bottom surface of the first connection hole 21.

[0045] Specifically, the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 can be processed from the side of the first metal layer 300 facing away from the first dielectric layer 20 by means of mechanical drilling and / or laser ablation.

[0046] It can be understood that due to the existence of the first protection part 402, the embedded areas of the first dielectric layer 20 and the first metal layer 300 corresponding to the device 40 will not sink due to part of the first dielectric layer 20 filling the gap between the inner wall of the accommodating groove and the device 40. Therefore, when processing the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 from the side of the first metal layer 300 facing away from the first dielectric layer 20, the depths of the first filling hole 31 and the first connection hole 21 can be accurately controlled without damaging the first part 401. When drilling, it is only necessary to sample and measure the thickness of the first dielectric layer 20 in the drilling area for the same batch of products, and there is no need to measure each product separately before drilling, nor is it necessary to set different drilling depths due to the sinking problem resulting in an uneven board surface to prevent drilling quality problems.

[0047] For example, when the thickness of the first dielectric layer 20 is relatively large, a high-energy laser is required to process the first filling hole 31 and the first connection hole 21. Due to the position corresponding to the first part 401 (the pad of the chip 42) of the device 40, the original position only had the first part 401 (with a thickness of 15 μm), and the first protection part 402 was added, and the corresponding thickness became 115 μm - 315 μm. Even if the laser energy is too large and it drills into part of the first protection part 402, it will not cause the pad of the chip 42 to be punctured and lead to the scrapping of the chip 42. The laser energy can be increased to ensure that the first dielectric layer 20 at the bottom of the first connection hole 21 is completely removed.

[0048] S500: Fill the first conductive part 201 in the first connection hole 21 by means of electroless copper plating, and fill the first filling part 301 in the first filling hole 31 by means of electroless copper plating. The first conductive part 201 is connected to the first filling part 301 and electrically conductive. The first metal layer 300 and the first filling part 301 form the first circuit layer 30.

[0049] It can be understood that even though the thickness of the first dielectric layer 20 is relatively thick, due to the existence of the first protection part 402, it is equivalent to reducing the distance between the first part 401 and the first circuit layer 30, thereby reducing the thickness of the first dielectric layer 20 at the corresponding part and reducing the aspect ratio of the blind hole formed by the first connection hole 21 and the first filling hole 31. Therefore, when filling the first conductive part 201 in the first connection hole 21 by means of electroless copper plating and filling the first filling part 301 in the first filling hole 31 by means of electroless copper plating, the first filling part 301 will not produce a depression. That is to say, when filling the first conductive part 201 in the first connection hole 21 by means of electroless copper plating, the corresponding position of the first circuit layer 30 will not produce a depression, thus avoiding the problem of insufficient plating hole ability during electroplating due to too large an aspect ratio during the electroplating filling hole process, and further avoiding the problem of poor filling hole.

[0050] As can be seen from the above, the embedded PCB and its manufacturing method provided in the embodiment of the present application are as follows: since the device 40 is embedded in the interior of the daughterboard 10, the device 40 is located on the side of the daughterboard 10 close to the first dielectric layer 20, a first portion 401 is provided on the side of the device 40 close to the first dielectric layer 20, and a first protective portion 402 is provided on the first portion 401. The interior of the first dielectric layer 20 is provided with a first connection hole 21, and the interior of the first connection hole 21 is filled with the first conductive portion 201. The first protective portion 402 is connected to the first conductive portion 201 and is electrically conductive, and the first conductive portion 201 is connected to the first circuit layer 30 and is electrically conductive. Therefore, the first portion 401 can be electrically conductive to the first circuit layer 30 through the first protective portion 402 and the first conductive portion 201. Therefore, during the process of manufacturing the circuit board, it is possible to avoid the occurrence of a depression at the corresponding position of the first circuit layer 30 when the first conductive portion 201 is filled in the first connection hole 21 by using copper plating, thereby avoiding the problem of poor hole filling during the electroplating hole filling process.

[0051] The embedded PCB and its manufacturing method provided in the embodiments of the present application can solve the problem of a recessed embedded area due to insufficient glue filling when pressing the daughterboard 10, the device 40, the first dielectric layer 20, and the first metal layer 300 together. It can also solve the problem of poor hole filling during the electroplating filling process of ultra-thick dielectric layers. It can also avoid the problem of the embedded PCB being scrapped due to the breakdown of the first portion 401 when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are processed on the side of the first metal layer 300 facing away from the first dielectric layer 20. It can also solve the problem of ineffective hole stacking due to a recessed bottom of the first connection hole 21 or residual glue during HDI build-up. The embedded PCB provided in the embodiment of the present application may be an embedded PCB product having an ultra-thick dielectric layer embedded with a device 40 .

[0052] Optionally, after the first conductive part 201 is filled in the first connection hole 21 by copper plating, and the first filling part 301 is filled in the first filling hole 31 by copper plating, the first circuit is made on the first circuit layer 30 by laminating, exposing, developing and etching.

[0053] In this embodiment, the device 40 includes a heat sink 41 and a chip 42 connected to each other, and the first portion 401 is disposed on the chip 42 .

[0054] By adopting the above solution, damage to the first portion 401 can be avoided when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are machined from the side of the first metal layer 300 facing away from the first dielectric layer 20 .

[0055] It can be understood that the first portion 401 can be a pad.

[0056] Before the device 40 is placed in the receiving groove of the daughter board 10 , the first protection portion 402 is manufactured on the first portion 401 by electroplating or welding.

[0057] With such an arrangement, the first protection portion 402 can be manufactured more conveniently.

[0058] It should be noted that the device 40 includes a heat sink 41 . When the heat sink 41 is made of ceramic, the first protection portion 402 is manufactured on the first portion 401 by electroplating or welding.

[0059] Optionally, the thickness of the first protection portion 402 is 50 μm-300 μm, such as 50 μm, 70 μm, 100 μm, 150 μm, 200 μm, 250 μm or 300 μm.

[0060] Such a configuration can avoid the problem of poor hole filling during the electroplating hole filling process, and can avoid damage to the first part 401 when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are processed from the side of the first metal layer 300 away from the first dielectric layer 20.

[0061] In this embodiment, the embedded PCB further includes a second dielectric layer 50 and a second circuit layer 60 that are stacked. The second dielectric layer 50 is located between the first circuit layer 30 and the second circuit layer 60. A second connection hole is provided inside the second dielectric layer 50. The interior of the second connection hole is filled with a second conductive portion 501. The first circuit layer 30 is connected to the second conductive portion 501 and is electrically conductive. The second circuit layer 60 is connected to the second conductive portion 501 and is electrically conductive.

[0062] The second dielectric layer 50 may be made of PP, the second circuit layer 60 may be made of copper, silver, or aluminum, etc. The second conductive portion 501 may be made of copper, silver, or aluminum, etc. For example, the second conductive portion 501 and the second circuit layer 60 may both be made of copper.

[0063] In the manufacturing method provided in the above embodiment, after the first conductive portion 201 is filled in the first connection hole 21, the manufacturing method of the embedded PCB further includes: First, the second dielectric layer 50 and the second metal layer are sequentially stacked on the first circuit layer 30 , with the second dielectric layer 50 being located between the first circuit layer 30 and the second metal layer.

[0064] Secondly, a second filling hole penetrating the second metal layer and a second connection hole penetrating the second dielectric layer 50 are processed from the side of the second metal layer away from the second dielectric layer 50. The second connection hole and the second filling hole are coaxially arranged, and the first circuit layer 30 defines the bottom surface of the second connection hole.

[0065] It can be understood that the addition of the first protective portion 402 avoids the problem of concavity caused by poor filling of the first dielectric layer 20. The entire surface of the embedded PCB is flat, and the thickness of the second dielectric layer 50 is consistent, eliminating the difficulty in controlling the drilling depth due to concavity in the embedded area. Furthermore, the addition of the first protective portion 402 solves the problem of concavity in the first filling portion 301 after copper plating. As a result, the first filling portion 301 remains flat, and the problem of conductivity failure between the first circuit layer 30 and the second circuit layer 60 caused by the concavity of the first filling portion 301 is eliminated.

[0066] Then, the second conductive part 501 is filled in the second connection hole by copper electroplating, and the second filling part 601 is filled in the second filling hole by copper electroplating. The second conductive part 501 is connected to the second filling part 601 and is electrically conductive. The second metal layer and the second filling part 601 constitute the second circuit layer 60.

[0067] By adopting the above solution, the problem of poor hole filling during the electroplating hole filling process can be avoided, and a multi-layer embedded PCB can be manufactured.

[0068] It should be noted that if the first protective portion 402 is not provided, when the first filling portion 301 is sunken, when the second dielectric layer 50 and the second metal layer (build-up layer) are sequentially stacked on the first circuit layer 30, the connection of the second circuit layer 60 will not be effectively connected to the first circuit layer 30 due to the sunken and suspended hole of the first filling portion 301. In addition, the embedded area itself is sunken. When the second circuit layer 60 is overall uneven during build-up, when the second filling hole penetrating the second metal layer and the second connection hole penetrating the second dielectric layer 50 are machined on the side of the second metal layer away from the second dielectric layer 50, it will be difficult to control the drilling depth.

[0069] The reason is that conventional drilling will use a sample measurement of the dielectric layer thickness after the same batch of boards are pressed to determine the blind hole drilling depth. The embedded product has a concave area due to the glue filling problem in the embedded area, which in turn causes the dielectric layer thickness in this area to be inconsistent with other non-embedded areas. The dielectric layer thickness in the concave area cannot be determined to be consistent because the concave area cannot completely contact the pressed cover plate. During pressing, the area is under virtual pressure, and the glue in the concave area will flow randomly, resulting in uneven glue flow in this area, thereby increasing the possibility of inconsistent dielectric layer thickness in this area. Before drilling, the dielectric layer thickness of each board cannot be obtained by sampling and measuring the entire batch of boards. The thickness of the embedded area of each board needs to be measured separately to set the drilling depth. If different thicknesses appear in the blind hole processing position of the embedded area of a single batch of boards, the drilling parameters need to be adjusted multiple times, thereby reducing the efficiency of blind hole processing.

[0070] The recessed embedded area makes it difficult to control the drilling depth. A too large depth will cause the laser energy to excessively drill through the first filling portion 301 , while a too small depth will cause excessive adhesive residue at the bottom of the second connection hole, resulting in connection failure after electroplating.

[0071] The present application adds a first protection portion 402 to the embedded device 40 so that after pressing, the embedded area will not be sunken due to insufficient glue filling, which is beneficial for blind hole processing and electroplating filling, and a semi-buried embedded PCB can be obtained.

[0072] Optionally, after the second conductive part 501 is filled in the second connection hole by copper plating and the second filling part 601 is filled in the second filling hole by copper plating, the second circuit is made on the second circuit layer 60 by laminating, exposing, developing and etching.

[0073] Before processing the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 from the side of the first metal layer 300 facing away from the first dielectric layer 20, the thickness H0 of the first protective portion 402 and the thickness H1 of the first dielectric layer 20 are obtained, and the difference between H1 and H0 is H; the aperture of the first connection hole 21 is D, and D is greater than 1.25*H.

[0074] By adopting the above solution, it is possible to avoid the problem that the aspect ratio of the blind hole composed of the first connecting hole 21 and the first filling hole 31 is too large, which leads to insufficient electroplating depth during filling and further causes the first filling part 301 at the hole mouth to be concave after filling.

[0075] For example, the thickness H1 of the first dielectric layer 20 is 300 μm, the thickness H0 of the first protective portion 402 is 180 μm, and the difference H between H1 and H0 is 300 μm-180 μm=120 μm. When the aperture D of the first connection hole 21 is 150 μm, the aspect ratio of the blind hole is 120:150=0.8:1. If the first protective portion 402 is not provided, the aspect ratio of the blind hole is 300:150=2:1. Due to the excessive aspect ratio, the electroplating depth capability during hole filling is insufficient, resulting in a hole mouth depression after hole filling.

[0076] It should be noted that the aperture D of the first connection hole 21 can be substantially equal to the aperture of the first filling hole 31, and the aperture of the blind hole formed by the first connection hole 21 and the first filling hole 31 can be equal to the aperture D of the first connection hole 21. The thickness H1 of the first dielectric layer 20 and the aperture of the blind hole are not limited to the ranges listed in this solution and can be adjusted according to product design, while also adjusting the thickness H0 of the first protective portion 402.

[0077] In this embodiment, the daughter board 10 includes a first core board 11, a connection dielectric layer 12, and a second core board 13 that are stacked. The first core board 11 is provided with a first opening window, the connection dielectric layer 12 is provided with a connection opening window, and the second core board 13 is provided with a second opening window. The first opening window, the connection opening window, and the second opening window are connected to define a receiving groove. When the daughter board 10, the device 40, the first dielectric layer 20, and the first metal layer 300 are pressed together, a part of the connection dielectric layer 12 fills the gap between the inner wall of the receiving groove and the device 40.

[0078] By adopting the above solution, the device 40 can be tightly fixed in the receiving groove, and the first dielectric layer 20 and the first circuit layer 30 corresponding to the device 40 can be prevented from being sunken by the first protection portion 402.

[0079] Among them, the first core board 11, the connection dielectric layer 12, and the second core board 13 can be cut out according to the panel size first, and the first opening window, the connection opening window, and the second opening window are respectively processed on the first core board 11, the connection dielectric layer 12, and the second core board 13. The sizes of the first opening window, the connection opening window, and the second opening window are all 0.1 mm larger than the size of the device 40.

[0080] Please refer to Figure 6 , in another embodiment, a second portion 403 is provided on the side of the device 40 away from the first dielectric layer 20, and a second protection portion 404 is provided on the second portion 403; the embedded PCB further includes a third dielectric layer 70 and a third circuit layer 80 that are stacked. The third dielectric layer 70 is located between the third circuit layer 80 and the daughter board 10. A third connection hole is provided inside the third dielectric layer 70, and a third conductive portion is filled inside the third connection hole. The second protection portion 404 is connected to and electrically conducts with the third conductive portion, and the third circuit layer 80 is connected to and electrically conducts with the third conductive portion.

[0081] By adopting the above solution, the problem of poor filling of the via holes during the electroplating filling process can be avoided, and the device 40 can be completely embedded inside the embedded PCB to manufacture an embedded PCB with a fully buried structure.

[0082] Optionally, after making the third circuit on the third circuit layer 80, a fourth dielectric layer 90 and a fourth circuit layer 100 can be provided on the side of the third circuit layer 80 away from the third dielectric layer 70, and a fourth circuit can be made on the fourth circuit layer 100. Then, processes such as AOI (Automated Optical Inspection), solder mask / character, forming (dividing the large panel into multiple unit boards by a conventional method), quality inspection / packaging and shipping are completed in sequence.

[0083] Please refer to Figure 7, in another embodiment, the device 40 includes a heat sink 41, and a first part 401 is disposed on the heat sink 41. The first part 401 is one of the parts of the device 40.

[0084] By adopting the above solution, it is possible to avoid the problem of poor via filling during the electroplating via filling process, and the heat sink 41 can be embedded into the embedded PCB to fabricate an embedded PCB with a semi-embedded structure.

[0085] Among them, the device 40 includes a heat sink 41. One side of the heat sink 41 includes a first forming part and a second forming part; before placing the device 40 into the receiving groove of the daughter board 10, a part of the second forming part is removed so that the first forming part protrudes from the remaining second forming part. The second forming part includes a first part 401 and a first protection part 402.

[0086] By adopting the above solution, it is possible to relatively conveniently fabricate the first part 401 and the first protection part 402.

[0087] Exemplarily, a part of the second forming part can be removed by etching or controlled-depth routing. The material of the heat sink 41 can be copper or aluminum.

[0088] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An embedded PCB, characterized in that, It includes a sub-board, a first dielectric layer, and a first circuit layer that are sequentially and stacked in a first direction. Devices are embedded inside the sub-board, and the devices are located on a side of the sub-board close to the first dielectric layer. A first part is provided on a side of the device close to the first dielectric layer, and a first protection part is provided on the first part; a first connection hole is provided inside the first dielectric layer, and a first conductive part is filled inside the first connection hole. The first protection part is connected to and electrically conductive with the first conductive part, and the first conductive part is connected to and electrically conductive with the first circuit layer.

2. The embedded PCB according to claim 1, wherein The embedded PCB further includes a second dielectric layer and a second circuit layer that are stacked. The second dielectric layer is located between the first circuit layer and the second circuit layer. A second connection hole is provided inside the second dielectric layer, and a second conductive part is filled inside the second connection hole. The first circuit layer is connected to and electrically conductive with the second conductive part, and the second circuit layer is connected to and electrically conductive with the second conductive part.

3. The embedded PCB according to claim 2, characterized in that, A second part is provided on a side of the device away from the first dielectric layer, and a second protection part is provided on the second part; the embedded PCB further includes a third dielectric layer and a third circuit layer that are stacked. The third dielectric layer is located between the third circuit layer and the sub-board. A third connection hole is provided inside the third dielectric layer, and a third conductive part is filled inside the third connection hole. The second protection part is connected to and electrically conductive with the third conductive part, and the third circuit layer is connected to and electrically conductive with the third conductive part.

4. The embedded PCB according to claim 1, characterized in that, The device includes a radiator and a chip that are connected, and the first part is provided on the chip; alternatively, the device includes a radiator, and the first part is provided on the radiator.

5. The embedded PCB according to any one of claims 1 to 4, characterized in that, The thickness of the first protection part is 50μm - 300μm.

6. A manufacturing method of an embedded PCB, characterized in that, It includes: Placing the device into the accommodation groove of the sub-board. A first part is provided on one side of the device, and a first protection part is provided on the first part. The size of the accommodation groove is larger than the size of the device. Stacking the first dielectric layer and the first metal layer on the sub-board in sequence. The sub-board, the first dielectric layer, and the first metal layer are sequentially arranged in the first direction. The first part is located on a side of the device close to the first dielectric layer. Pressing the sub-board, the device, the first dielectric layer, and the first metal layer together. Part of the first dielectric layer fills the gap between the inner wall of the accommodation groove and the device. Processing a first filling hole penetrating the first metal layer and a first connection hole penetrating the first dielectric layer from a side of the first metal layer away from the first dielectric layer. The first connection hole and the first filling hole are coaxially arranged. The first protection part defines the bottom surface of the first connection hole. Filling the first connection hole with the first conductive part by means of copper deposition electroplating, and filling the first filling hole with the first filling part by means of copper deposition electroplating. The first conductive part is connected to and electrically conductive with the first filling part. The first metal layer and the first filling part form the first circuit layer.

7. The manufacturing method of the embedded PCB according to claim 6, wherein After the first conductive portion is filled in the first connection hole, the method for manufacturing the embedded PCB further includes: stacking a second dielectric layer and a second metal layer in sequence on the first circuit layer, wherein the second dielectric layer is located between the first circuit layer and the second metal layer; A second filling hole penetrating the second metal layer and a second connection hole penetrating the second dielectric layer are processed on a side of the second metal layer facing away from the second dielectric layer, the second connection hole and the second filling hole are coaxially arranged, and the first circuit layer defines a bottom surface of the second connection hole; The second conductive part is filled in the second connecting hole by copper plating, and the second filling part is filled in the second filling hole by copper plating. The second conductive part is connected to the second filling part and is electrically conductive. The second metal layer and the second filling part constitute a second circuit layer.

8. The manufacturing method of the embedded PCB according to claim 6, characterized in that, Before processing the first filling hole penetrating the first metal layer and the first connecting hole penetrating the first dielectric layer from the side of the first metal layer facing away from the first dielectric layer, obtain the thickness H0 of the first protective portion and the thickness H1 of the first dielectric layer, and the difference between H1 and H0 is H; the aperture of the first connecting hole is D, and D is greater than 1.25*H.

9. The manufacturing method of the embedded PCB according to claim 6, characterized in that, The first portion is a solder pad; before placing the device into the receiving groove of the daughter board, the first protective portion is made on the first portion by electroplating or welding; Alternatively, the device includes a heat sink, one side of which includes a first molded portion and a second molded portion; before placing the device into the receiving groove of the sub-board, part of the second molded portion is removed so that the first molded portion protrudes from the remaining second molded portion, and the second molded portion includes the first portion and the first protective portion.

10. The manufacturing method of the embedded PCB according to any one of claims 6 to 9, characterized in that, The sub-board includes a first core board, a connecting dielectric layer and a second core board arranged in a stacked manner, the first core board is provided with a first window, the connecting dielectric layer is provided with a connecting window, and the second core board is provided with a second window. The first window, the connecting window and the second window are connected and define the accommodating groove; when the sub-board, the device, the first dielectric layer and the first metal layer are pressed together, part of the connecting dielectric layer fills the gap between the inner wall of the accommodating groove and the device.

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