A radiation-hardened SiC superjunction MOS structure and its preparation process

Abstract

The present invention discloses an irradiation-hardened SiC superjunction MOS structure and a preparation process thereof, belonging to the field of MOS semiconductor technology. The structure comprises a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. The present invention provides a lightly doped N layer in the middle of the N drift layer and laterally symmetrical trapezoidal P- layers on both sides of the N drift layer. These layers can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the impact of excess carriers on device performance, effectively reduce performance degradation caused by irradiation, and improve the reliability and stability of the device in an irradiated environment. The present invention forms a concave heavily doped N layer at the bottom end of the lightly doped N layer, thereby significantly increasing the carrier concentration in this region and significantly enhancing the conductive performance.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to an irradiation-strengthened SiC super junction MOS structure and a preparation process thereof. Background Art

[0002] In the evolution of modern power semiconductor devices, silicon carbide (SiC) has become an ideal material for building high-performance power devices due to its exceptional physical properties, such as wide bandgap, high breakdown electric field strength, high saturated electron drift velocity, and excellent thermal conductivity. The SiC-based superjunction metal-oxide-semiconductor field-effect transistor (MOSFET), or SiC superjunction MOS structure, combines the advantages of the superjunction structure in optimizing electric field distribution, improving voltage resistance, and reducing on-resistance with the inherent high-temperature and high-frequency properties of SiC, demonstrating enormous application potential in many cutting-edge fields.

[0003] The prior art (Announcement No.: CN210805778U) discloses a SiC-MOS device structure comprising a metal drain, a silicon carbide N+ substrate, and a silicon carbide N-epitaxial layer arranged sequentially from bottom to top. The silicon carbide N-epitaxial layer has source trenches at the upper left and upper right sides, and silicon carbide P+ doped regions and silicon carbide P-type doped regions are arranged from top to bottom below the source trenches. The source trenches are filled with Schottky contact metal, and the gate trenches have gate structures inside and on their surfaces. The first and second mesa structures are both composed of the silicon carbide N-epitaxial layer, the silicon carbide P-type doped region, and the silicon carbide N+ source region. This application can adjust the Schottky barrier height to form a Schottky contact with a low on-state voltage drop, significantly reducing the size of the power electronic system, reducing packaging costs, and improving system application reliability. It also significantly improves basic performance and long-term application reliability, and has low specific on-resistance and low leakage.

[0004] Among the above technologies, when the devices are used in fields such as aerospace, they need to face the complex and harsh space radiation environment, among which the problem of single-particle irradiation is particularly prominent. When high-energy particles pass through the device, they will violently collide with the lattice atoms inside the device, which may cause serious deterioration of the electrical performance of the device, such as causing single-particle flips, single-particle locks, and even single-particle burns. These phenomena greatly limit their application scope and reliability, and have become a key issue that needs to be solved urgently. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a solution to the problem that when high-energy particles pass through a device, they will violently collide with the lattice atoms inside the device, which may cause serious deterioration of the electrical performance of the device and may cause single-particle upset, single-particle lockout and even single-particle burnout.

[0006] Technical solution: A radiation-hardened SiC superjunction MOS structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell;

[0007] Furthermore, a laterally symmetric P-layer is provided inside a single MOS cell and on the left and right sides of the N drift layer. The cross-sectional profiles of the two laterally symmetric P-layers are both trapezoidal, and the bottom ends of the two laterally symmetric P-layers are in contact with the upper surface of the N substrate layer.

[0008] Furthermore, a heavily doped N layer is formed at the bottom of the lightly doped N layer by ion implantation, the cross-sectional profiles of the heavily doped N layer are all concave, and the bottom of the heavily doped N layer contacts the upper surface of the N substrate layer.

[0009] Furthermore, an arc-shaped P-layer is formed inside the heavily doped N layer by ion implantation, and the bottom end of the arc-shaped P-layer contacts the upper surface of the N substrate layer.

[0010] Furthermore, a lightly doped N-type half layer is formed inside the heavily doped N layer and on both sides of the arc-shaped P-layer by ion implantation.

[0011] Furthermore, the cross-sectional profiles of the lightly doped N-type half layers are all rectangular, and the bottom ends of the lightly doped N-type half layers are in contact with the upper surface of the N substrate layer.

[0012] Furthermore, semicircular lightly doped N layers are formed on both sides of the heavily doped N layer by ion implantation.

[0013] A process for preparing a radiation-hardened SiC superjunction MOS structure, comprising:

[0014] S1. Select an N-type SiC substrate as the N substrate layer, check the surface flatness and crystal orientation parameters of the substrate to ensure that it meets the process requirements, place the N substrate layer in acetone and ethanol solutions in sequence, and use an ultrasonic cleaner to perform ultrasonic cleaning to remove organic impurities on the surface. Then, soak the N substrate layer in a dilute hydrofluoric acid solution to remove the surface oxide layer, then rinse it with deionized water, and finally blow dry it with nitrogen or spin dryer;

[0015] S2. Growing the N drift layer on the cleaned N substrate layer using chemical vapor deposition technology;

[0016] S3, coating, exposing, and developing a photoresist in the middle region of the N drift layer using a photolithography technique to form a rectangular mask pattern for the lightly doped N layer, and implanting nitrogen ions into the rectangular mask pattern region using an ion implantation process to form the lightly doped N layer. After implantation of the lightly doped N layer is completed, removing the photoresist, and again using the photolithography technique to form a concave mask pattern in the bottom region of the lightly doped N layer. Implanting nitrogen ions into the concave mask pattern region to form the heavily doped N layer. After the implantation is completed, placing the layer in an annealing furnace to repair lattice damage.

[0017] S4, using photolithography to form a trapezoidal mask pattern of the laterally symmetric P-layer on the left and right regions of the N-drift layer, respectively, and then using an ion implantation process to implant boron ions into the region covered by the trapezoidal mask to form the laterally symmetric P-layer with a trapezoidal cross-sectional profile, and performing an annealing treatment after the implantation;

[0018] S5. Forming a curved mask pattern of the curved P-layer inside the heavily doped N-layer by photolithography, implanting boron ions by ion implantation to form the curved P-layer, and performing annealing after implantation;

[0019] S6. Implanting nitrogen ions into the heavily doped N-type layer and the areas on both sides of the arc-shaped P-type layer using photolithography and ion implantation processes to form the lightly doped N-type half layer, and performing annealing after the implantation.

[0020] S7. Using photolithography technology, define the regions of the P+ layer, the N-well layer, and the P-well layer, respectively. For the P+ layer, perform boron ion implantation. For the N-well layer, perform nitrogen ion implantation. For the P-well layer, perform boron ion implantation. After the implantation, perform annealing to activate impurities and repair lattice damage.

[0021] S8. Depositing and patterning metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain, the source, and the gate.

[0022] Beneficial effects:

[0023] 1. The present invention provides a lightly doped N layer in the middle of the N drift layer and laterally symmetrical trapezoidal P- layers on both sides of the N drift layer. This can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the impact of excess carriers on device performance, effectively reduce performance degradation caused by radiation, and improve the reliability and stability of the device in an irradiated environment.

[0024] 2. By forming a concave heavily doped N layer at the bottom of the lightly doped N layer, the present invention can significantly increase the carrier concentration in this area and significantly enhance the conductive performance. At the same time, it is interconnected with the surrounding laterally symmetrical P-layer, arc-shaped P-layer and other structures to jointly shape the electric field and carrier transmission path within the device, thereby effectively regulating the carrier concentration and distribution and reducing the on-resistance.

[0025] 3. The present invention forms an arc-shaped P-layer below the heavily doped N-layer, thereby reducing the interference of excess carriers on the core area of ​​the device, further reducing the degree of damage to the device caused by radiation, and significantly improving the device's radiation resistance. At the same time, by forming a lightly doped N-type half-layer with a rectangular cross-sectional profile inside the heavily doped N-layer and outside the arc-shaped P-layer, excessive concentration of local electric fields is avoided, further improving the overall voltage withstand capability of the device, and making the device more stable and reliable when operating in a high-voltage environment;

[0026] 4. The present invention adopts a semicircular side lightly doped N layer to make the stress distribution of the internal structure of the device more uniform, reduce the stress concentration problem caused by structural mismatch, thereby further enhancing the stability of the device and reducing the probability of structural defects in the device during manufacturing and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a structural diagram of embodiment 1 of the present invention;

[0028] Figure 2 is a schematic structural diagram of embodiment 2 of the present invention;

[0029] Figure 3 is a schematic structural diagram of embodiment 3 of the present invention;

[0030] Figure 4 is a schematic structural diagram of embodiment 4 of the present invention;

[0031] Figure 5 It is a structural diagram of Example 5 of the present invention.

[0032] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N substrate layer; 5. N drift layer; 6. P+ layer; 7. N well layer; 8. P well layer; 9. Lightly doped N layer; 10. Laterally symmetrical P- layer; 11. Heavily doped N layer; 12. Arc-shaped P- layer; 13. Lightly doped N-type half layer; 14. Semicircular side lightly doped N layer. DETAILED DESCRIPTION

[0033] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1-5As shown, according to one aspect of the present invention, a process for preparing a radiation-hardened SiC super junction MOS structure is provided, comprising:

[0035] Step 1: Select an N-type SiC substrate as the N substrate layer 4, check the surface flatness and crystal orientation parameters of the substrate to ensure that it meets the process requirements, place the N substrate layer 4 in acetone and ethanol solutions in sequence, and use an ultrasonic cleaner to perform ultrasonic cleaning to remove organic impurities on the surface. Then, soak the N substrate layer 4 in a dilute hydrofluoric acid solution to remove the surface oxide layer, then rinse it with deionized water, and finally dry it with nitrogen or spin dryer. In this way, organic impurities, oxide layers and other contaminants on the surface of the N substrate layer 4 are removed to prevent these impurities from affecting the arrangement and bonding of atoms in the subsequent epitaxial growth process, ensuring that the N substrate layer 4 has good lattice matching and interface characteristics, thereby improving the quality of the subsequently grown semiconductor epitaxial layer and laying the foundation for the preparation of high-performance SiC super-junction MOS structures.

[0036] Step 2: Using chemical vapor deposition technology to grow an N drift layer 5 on the cleaned N substrate layer 4, the purpose is to grow an N drift layer 4 with a specific thickness, doping concentration and crystal quality on the N substrate layer 4, as a key component of the MOS structure.

[0037] Step 3: Photoresist coating, exposure and development are performed in the middle area of ​​the N drift layer 5 by photolithography technology to form a rectangular mask pattern of the lightly doped N layer 9. Nitrogen ions are implanted into the rectangular mask pattern area by ion implantation to form the lightly doped N layer 9. After the implantation of the lightly doped N layer 9 is completed, the photoresist is removed. Photolithography technology is used again to form a concave mask pattern in the bottom area of ​​the lightly doped N layer 9. Nitrogen ions are implanted into the concave mask pattern area to form a heavily doped N layer 11. After the implantation is completed, the device is placed in an annealing furnace to repair lattice damage. By adjusting the doping concentration of the local area, the electrical properties of the area are changed, and the electric field distribution inside the device is further optimized. The setting of the lightly doped N layer 9 and the heavily doped N layer 11 can effectively regulate the concentration and distribution of carriers, reduce the on-resistance, and enhance the stability of the device in an irradiated environment, providing a basis for the subsequent formation of other special structures and improving the overall performance of the device.

[0038] Step 4: Use photolithography technology to form a trapezoidal mask pattern of the laterally symmetric P-layer 10 on the left and right areas of the N-drift layer 5 respectively, and then use an ion implantation process to implant boron ions into the area covered by the trapezoidal mask to form a laterally symmetric P-layer 10 with a trapezoidal cross-sectional profile, which is annealed after implantation; the laterally symmetric P-layer 10 can interact with the N-drift layer 5 to make the electric field distribution more uniform, avoiding the occurrence of local electric field concentration. The uniform electric field distribution helps to improve the voltage resistance of the device, so that the device can work stably in a high voltage environment and reduce the risk of breakdown caused by uneven electric field.

[0039] Step 5: Inside the heavily doped N layer 11, an arc-shaped mask pattern of the arc-shaped P-layer 12 is formed by photolithography technology, and boron ions are implanted by ion implantation to form the arc-shaped P-layer 12, which is then annealed after implantation. The arc-shaped P-layer 12 can utilize its own structure and doping characteristics to quickly collect and neutralize some of the carriers generated by radiation, reducing the interference of excess carriers on the core area of ​​the device, thereby effectively reducing the degree of damage to the device caused by radiation and improving the device's radiation resistance.

[0040] Step 6: Nitrogen ions are implanted into the heavily doped N-layer 11 and on both sides of the arc-shaped P-layer 12 using photolithography and ion implantation processes to form a lightly doped N-type half-layer 13, which is then annealed. The formation of the lightly doped N-type half-layer 13 in a specific region of the heavily doped N-layer 11 changes the charge distribution in that region, further optimizing the internal electric field of the device, thereby further avoiding premature breakdown of the device due to an overly concentrated electric field, improving the device's withstand voltage performance, and enhancing its reliability in high-voltage environments.

[0041] Step 7: Use photolithography technology to define the regions of P+ layer 6, N-well layer 7 and P-well layer 8 respectively. For P+ layer 6, boron ion implantation is used, for N-well layer 7, nitrogen ion implantation is used, and for P-well layer 8, boron ion implantation is used. After the implantation is completed, annealing treatment is performed to activate impurities and repair lattice damage; the core conductive channel and carrier injection region of the MOS device can be constructed. The P+ layer 6 provides a low-resistance carrier injection path, and the N-well layer 7 and the P-well layer 8 cooperate with each other to form a conductive channel that can be regulated by the gate voltage, thereby realizing control of the device current.

[0042] Step 8: Deposit and pattern metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain 1, source 2 and gate 3.

[0043] Example 1

[0044] like Figure 1 As shown, a radiation-hardened SiC superjunction MOS structure is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3; the semiconductor epitaxial layer comprises an N substrate layer 4, an N drift layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8; a lightly doped N layer 9 is provided in the middle of the N drift layer 5 of the single MOS cell; a laterally symmetrical P- layer 10 is provided inside the single MOS cell and on the left and right sides of the N drift layer 5; the cross-sectional profiles of the two laterally symmetrical P- layers 10 are both trapezoidal, and the bottom ends of the two laterally symmetrical P- layers 10 are in contact with the upper surface of the N substrate layer 4;

[0045] In a single MOS cell, the drain 1 serves as the current outflow terminal, connected to the N substrate layer 4, responsible for conducting the current within the device. The source 2 and gate 3 are used to control the conduction and cutoff of the current. The semiconductor epitaxial layer serves as the core functional area of ​​the device. The N substrate layer 4 provides stable base support and a low-resistance current path. The N drift layer 5 serves as the main voltage-resistant area, responsible for withstanding high voltages. The lightly doped N layer 9 in the middle changes the doping characteristics of this area, making the resistance distribution of the N drift layer 5 more reasonable. Laterally symmetric P-layers 10 are provided on both sides of the N drift layer 5, with a trapezoidal cross-section. This shape design allows the junction area between the laterally symmetric P-layer 10 and the N drift layer 5 to better regulate the electric field distribution. The bottom end of the laterally symmetric P-layer 10 contacts the N substrate layer 4, forming a charge compensation structure from the N substrate layer 4 to the N drift layer 5. In addition, the P+ layer 6, N well layer 7, and P well layer 8 cooperate with each other to form a conductive channel under the action of the gate voltage, achieving precise control of the current.

[0046] That is, the holes in the laterally symmetrical P-layer 10 can interact with the electrons in the N-drift layer 5 to accelerate carrier recombination, reduce the impact of excess carriers on device performance, effectively reduce performance degradation caused by radiation, and improve the reliability and stability of the device in an irradiated environment.

[0047] Example 2

[0048] like Figure 2 As shown, a heavily doped N layer 11 is formed at the bottom of the lightly doped N layer 9 by ion implantation. The cross-sectional profile of the heavily doped N layer 11 is concave, and the bottom of the heavily doped N layer 11 contacts the upper surface of the N substrate layer 4.

[0049] A heavily doped N layer 11 with a concave cross-sectional profile is formed at the bottom of the lightly doped N layer 9. The concave design makes the heavily doped N layer 11 present a structural feature of being concave in the middle and convex on both sides in the lateral direction. Its bottom end maintains complete contact with the upper surface of the N substrate layer 4, forming a continuous conductive channel, thereby retaining the high conductivity advantage of the heavily doped area and specially regulating the electric field distribution through the concave profile. It cooperates with the surrounding laterally symmetrical P-layer 10 and other structures to construct a complex and orderly charge distribution system, which can effectively regulate the concentration and distribution of carriers, reduce the on-resistance, and enhance the stability of the device in an irradiated environment.

[0050] Example 3

[0051] like Figure 3 As shown, an arc-shaped P-layer 12 is formed inside the heavily doped N layer 11 by ion implantation, and the bottom end of the arc-shaped P-layer 12 contacts the upper surface of the N substrate layer 4;

[0052] An ion implantation process is used to implant boron ions at a specific energy and dose to form an arc-shaped P-layer 12 inside the heavily doped N layer 11. The bottom of the arc-shaped P-layer 12 is tightly attached to the upper surface of the N substrate layer 4. Its arc-shaped profile design cooperates with the heavily doped N layer 11 and other structures, changing the originally uniform charge distribution in the area to form an arc-shaped P-layer 12 with a certain thickness and doping concentration. This layer forms a PN junction with the heavily doped N layer 11, and together with the surrounding area, constructs a complex and ordered semiconductor structure system. The arc-shaped P-layer 12 can quickly collect and neutralize some of the carriers generated by radiation due to its doping characteristics and arc-shaped structure. When high-energy particles are incident, the holes in the arc-shaped P-layer 12 can combine with the electrons in the heavily doped N layer 11, reducing the interference of excess carriers on the core area of ​​the device, further reducing the degree of damage to the device caused by radiation, and significantly improving the device's radiation resistance.

[0053] Example 4

[0054] like Figure 4 As shown, lightly doped N-type half layers 13 are formed inside the heavily doped N layer 11 and on both sides of the arc-shaped P-layer 12 by ion implantation. The cross-sectional profiles of the lightly doped N-type half layers 13 are all rectangular, and the bottom ends of the lightly doped N-type half layers 13 are in contact with the upper surface of the N substrate layer 4;

[0055] After the heavily doped N layer 11 and the curved P-layer 12 have been formed, photolithography technology is used to precisely position the mask. A low dose of nitrogen ions is implanted into the area within the heavily doped N layer 11 and outside the curved P-layer 12, forming a lightly doped N-type half-layer 13 with a rectangular cross-section. The bottom of the lightly doped N-type half-layer 13 is in close contact with the upper surface of the N substrate layer 4. During the implantation process, parameters such as the energy and dose of the nitrogen ions are strictly controlled to ensure that the lightly doped N-type half-layer 13 has an appropriate doping concentration and depth. This ensures that the lightly doped N-type half-layer 13 cooperates with the heavily doped N layer 11 and the curved P-layer 12 in terms of electrical properties and spatial structure, jointly constructing a complex and orderly semiconductor internal structure system. This further changes the charge distribution state in the heavily doped N layer 11 region, making the electric field distribution in this region more refined and reasonable. This effectively mitigates the electric field mutation caused by the heavy doping and curved P-layer 12, avoids excessive local electric field concentration, further improves the overall voltage withstand capability of the device, and makes the device more stable and reliable when operating in a high-voltage environment.

[0056] Example 5

[0057] like Figure 5 As shown, a semicircular lightly doped N layer 14 is formed on both sides of the heavily doped N layer 11 by ion implantation;

[0058] Nitrogen ion implantation is performed through a semicircular mask to form a semicircular side lightly doped N layer 14, whose geometric structure matches the electric field distribution and effectively neutralizes the excess electrons in the heavily doped N layer 11;

[0059] This enhances the stability of the device's internal structure. Its semicircular design can better adapt to internal stress changes, reduce stress concentration problems caused by structural mismatch, and lower the probability of structural defects in the device during manufacturing and use, further ensuring the stable performance of the device.

[0060] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A radiation-hardened SiC superjunction MOS structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3); the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a P+ layer (6), an N well layer (7) and a P well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; The bottom end of the lightly doped N layer (9) is formed with a heavily doped N layer (11) by ion implantation, the cross-sectional profile of the heavily doped N layer (11) is concave, and the bottom end of the heavily doped N layer (11) is in contact with the upper surface of the N substrate layer (4); An arc-shaped P-layer (12) is formed inside the heavily doped N layer (11) by ion implantation, and the bottom end of the arc-shaped P-layer (12) contacts the upper surface of the N substrate layer (4); A lightly doped N-type half layer (13) is formed inside the heavily doped N layer (11) and on both sides of the arc-shaped P-layer (12) by ion implantation; The cross-sectional profiles of the lightly doped N-type half layers (13) are all rectangular, and the bottom ends of the lightly doped N-type half layers (13) are in contact with the upper surface of the N substrate layer (4).

2. The radiation-hardened SiC superjunction MOS structure according to claim 1, characterized in that: A lateral symmetric P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5); the cross-sectional profiles of the two lateral symmetric P-layers (10) are both trapezoidal; and the bottom ends of the two lateral symmetric P-layers (10) are in contact with the upper surface of the N substrate layer (4).

3. The radiation-hardened SiC superjunction MOS structure according to claim 1, wherein: Semicircular lightly doped N layers (14) are formed on both sides of the heavily doped N layer (11) by ion implantation.

4. A process for preparing an irradiation-hardened SiC superjunction MOS structure, characterized in that: The invention comprises the radiation-hardened SiC super-junction MOS structure as claimed in claim 2, wherein the preparation process of the radiation-hardened SiC super-junction MOS structure comprises the following steps: S1. Select an N-type SiC substrate as the N substrate layer (4), check the surface flatness and crystal orientation parameters of the substrate to ensure that it meets the process requirements, place the N substrate layer (4) in acetone and ethanol solutions in turn, use an ultrasonic cleaning machine to perform ultrasonic cleaning to remove organic impurities on the surface, then soak the N substrate layer (4) in a dilute hydrofluoric acid solution to remove the surface oxide layer, then rinse with deionized water, and finally blow dry with nitrogen or spin dryer; S2, growing the N drift layer (5) on the cleaned N substrate layer (4) using chemical vapor deposition technology; S3, coating, exposing and developing a photoresist in the middle area of ​​the N drift layer (5) by photolithography technology to form a rectangular mask pattern of the lightly doped N layer (9), and using an ion implantation process to implant nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer (9). After the implantation of the lightly doped N layer (9), the photoresist is removed, and photolithography technology is used again to form a concave mask pattern in the bottom area of ​​the lightly doped N layer (9). Nitrogen ions are implanted into the concave mask pattern area to form the heavily doped N layer (11). After the implantation is completed, the heavily doped N layer (11) is placed in an annealing furnace to repair lattice damage. S4, using photolithography technology to form a trapezoidal mask pattern of the side-symmetrical P-layer (10) on the left and right areas of the N drift layer (5), and then using an ion implantation process to implant boron ions into the area covered by the trapezoidal mask to form the side-symmetrical P-layer (10) with a trapezoidal cross-sectional profile, and performing annealing after implantation; S5, forming an arc-shaped mask pattern of the arc-shaped P-layer (12) inside the heavily doped N-layer (11) by photolithography technology, implanting boron ions by ion implantation technology to form the arc-shaped P-layer (12), and performing annealing after implantation; S6, using photolithography and ion implantation processes to implant nitrogen ions inside the heavily doped N layer (11) and in areas on both sides of the arc-shaped P-layer (12) to form the lightly doped N-type half layer (13), and then performing annealing after the implantation; S7, respectively defining the regions of the P+ layer (6), the N-well layer (7), and the P-well layer (8) by photolithography technology, using boron ion implantation for the P+ layer (6), nitrogen ion implantation for the N-well layer (7), and boron ion implantation for the P-well layer (8), and performing annealing after the implantation is completed to activate impurities and repair lattice damage; S8. Depositing and patterning metal layers in sequence through photolithography or sputtering processes to form ohmic contacts and Schottky contacts of the drain (1), the source (2) and the gate (3).

Images