Zero current detector

Abstract

The present disclosure relates to a zero current detection (101) circuit, comprising:-a first comparator (101-Comp) configured to compare a first voltage (Vsw100) representative of a first current (IL101) with a first threshold voltage (Vos101); -a calibration circuit (101-CAL) configured to modify a value of the first threshold voltage (Vos101) according to process, voltage and / or temperature variations.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits and devices, and more particularly to a zero current detection circuit. Background Art

[0002] Zero current detection circuits are circuits that can sense current to detect when the current is equal to zero. They are commonly used in voltage converter circuits, such as DC-DC converters.

[0003] The present disclosure contemplates at least some improvements to certain aspects of known zero current detection circuits. Summary of the Invention

[0004] A zero current detection circuit with relatively high accuracy is needed.

[0005] One embodiment addresses all or some of the shortcomings of known zero current detection circuits.

[0006] One embodiment provides a zero current detection circuit, including:

[0007] - a first comparator configured to compare a first voltage representing the first current with a first threshold voltage;

[0008] - a calibration circuit configured to modify the value of the first threshold voltage according to process, voltage and / or temperature variations.

[0009] According to an embodiment, the first threshold voltage is an offset voltage of the first comparator.

[0010] According to an embodiment, the calibration circuit comprises a second comparator circuit.

[0011] According to an embodiment, the second comparator circuit is more accurate than the first comparator.

[0012] According to an embodiment, the circuit includes a logic circuit configured as a main control circuit of the zero current detection circuit.

[0013] Another embodiment provides a DC-DC converter including the zero current detection circuit described previously.

[0014] According to an embodiment, a converter includes two switches coupled in series, and a coil having one of its terminals coupled to an intermediate node between the two switches.

[0015] According to an embodiment, the zero current detection circuit is configured to detect when the current in the coil is equal to zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above-mentioned features and advantages and other features and advantages will be apparent from the following description of specific embodiments given by way of example and not limitation with reference to the accompanying drawings, in which:

[0017] Figure 1 An example application of an embodiment of a zero current detection circuit is shown;

[0018] Figure 2 A timing diagram illustrating an example of an implementation of a zero current detection circuit;

[0019] Figure 3 is a block diagram illustrating a zero current detector according to an embodiment;

[0020] Figure 4 Shown in more detail Figure 3 A circuit of an embodiment;

[0021] Figure 5 Shown in more detail Figure 3 Another circuit of an embodiment of the present invention;

[0022] Figure 6 Shown in more detail Figure 3 Another circuit of an embodiment of the present invention;

[0023] Figure 7 More detailed and partially shown in block diagram form Figure 3 Another circuit of an embodiment of the present invention;

[0024] Figure 8 Shown in more detail Figure 7 part of the circuit;

[0025] Figure 9 Shown in more detail Figure 7 part of the circuit;

[0026] Figure 10 Shown in more detail Figure 7 part of the circuit;

[0027] Figure 11 Shown in more detail Figure 7 part of the circuit; and

[0028] Figure 12 Shown in more detail Figure 3 Another circuit of an embodiment. DETAILED DESCRIPTION

[0029] In the various drawings, similar features are represented by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0030] For clarity, only the operations and elements that are helpful for understanding the embodiments described herein are shown and described in detail.

[0031] Unless otherwise specified, when two elements are referred to as being connected together, this indicates a direct connection without any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this indicates that the two elements can be connected or can be coupled via one or more other elements.

[0032] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "up", "down", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "higher", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., please refer to the directions shown in the accompanying drawings.

[0033] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0034] Figure 1 A DC-DC converter circuit 100 is shown very schematically and partly in block diagram form, including an embodiment of a zero current detection (ZCD) circuit 101 .

[0035] The DC-DC converter circuit 100 includes two switches S101 and S102 connected in series between a first node receiving an input voltage Vin100 and a second node (eg, ground) receiving a first reference voltage PWRGND100 .

[0036] According to an example, both switches S101 and S102 are metal oxide semiconductor field effect transistors, also known as MOSFET transistors or MOS transistors. More specifically, switch S101 is a P-type MOS transistor, also known as a P-channel MOS transistor or PMOS transistor, while switch S102 is an N-type transistor, also known as an N-channel MOS transistor or NMOS transistor. The source terminal of switch S101 is coupled to, and preferably connected to, a first node receiving an input voltage Vin100, and the drain terminal of switch S101 is coupled to, and preferably connected to, a drain terminal of switch S102. The source terminal of switch S102 is coupled to, and preferably connected to, a second node receiving a reference voltage PWRGND100. The gate terminals of the switches receive control voltages from a driver circuit 102 (logic driver). More specifically, switch S101 receives a control voltage Pdrv100 from the driver circuit 102 at its gate terminal, and switch S102 receives a control voltage Ndrv100 from the driver circuit 102 at its gate terminal.

[0037] According to another example, both switches S101 and S102 are NMOS transistors.

[0038] According to another example, the switches S101 and S102 can be implemented by another type of transistors (eg, bipolar transistors).

[0039] Driver circuit 102 is a circuit capable of providing control voltages Pdrv100 and Ndrv100 after receiving two pulse signals Pon100 and Non100 from pulse modulator (Pulse Mod) circuit 103 and control voltage VZCD100 from an embodiment of zero current detection circuit 101. In an exemplary embodiment, signals Pon100 and Non100 are non-overlapping signals. Those skilled in the art will understand how to implement such a circuit. In an exemplary embodiment, pulse modulator circuit 103 is powered by supply voltage AVD100 and a second reference voltage GND100 that is different from first reference voltage PWRGND100.

[0040] The pulse modulator circuit 103 is a circuit capable of providing two pulse signals Pon100 and Non100 based on a reference voltage Vref100. The reference voltage Vref100 is different from the reference voltage GND100. Those skilled in the art will understand how to implement such a circuit.

[0041] The DC-DC converter circuit 100 also includes a coil L101 coupled between an intermediate node (labeled A101, corresponding to the drain terminals of switches S101 and S102) between switches S101 and S102 and an output node B101. The zero-current detection circuit 101 is configured to monitor the input current IL101 of the coil L101. The voltage between node A101 and a reference voltage GND100 is labeled Vsw100. The output voltage Vout100 of the DC-DC converter 100 is provided between node B101 and a node receiving the reference voltage GND100.

[0042] The DC-DC converter circuit 100 further includes a capacitor C101 coupled between the node B101 and a node receiving the second reference voltage GND100 .

[0043] The DC-DC converter circuit 100 further includes a current source I101 coupled between the node B101 and a node receiving a second reference voltage GND100 .

[0044] According to an embodiment, zero current detection circuit 101 includes a comparator 101-Comp capable of comparing voltage Vsw100 with a threshold voltage Vos101. Voltage Vsw100 represents input current IL101 of coil L101. Threshold voltage Vos101 is used to compensate for internal offset and delay of comparator 101-Comp, for example, due to process, voltage, and temperature (PVT) variations.

[0045] The zero current detection circuit 101, also referred to herein as the zero current detector 101, further includes a voltage source 101-Vos that provides a threshold voltage Vos101 and an automatic calibration circuit 101-CAL. According to an embodiment, the automatic calibration circuit 1011-CAL is configured to configure the voltage source 101-Vos to account for environmental variations, such as temperature variations, and / or manufacturing variations (e.g., process variations and / or voltage variations). In other words, the automatic calibration circuit 101-CAL is configured to account for what is commonly referred to as PVT variations of the comparator 101-Comp, where PVT stands for process voltage and temperature.

[0046] Combine Figure 2 The operation of the zero current detection circuit 101 will be described in more detail.

[0047] Voltage Vsw100 is generated by the switching action of the DC-DC converter via power switches S101 and S102. More specifically, the basic operation of the DC-DC is as follows.

[0048] When switch S101 is turned on and switch S102 is turned off (controlled by Pdrv and Ndrv voltages), the node providing voltage Vsw100 receives voltage Vin100 via switch S101 , and output voltage Vout100 , capacitor C101 and inductor L101 are charged (so inductor current IL101 ramps up).

[0049] When switch S101 is off, switch S102 is on (controlled by Pdrv and Ndrv signals), the node providing voltage Vsw100 receives voltage PWRGND100 via switch S102 , and output voltage Vout100 , capacitor C101 and inductor L101 discharge (so inductor current IL101 ramps down).

[0050] The zero current detector operates as follows.

[0051] Voltage Vsw100 is used to detect the condition of the inductor current during the ramp-down period of inductor L101 when switch S101 is off and switch S102 is on. In particular:

[0052] - If switch S102 opens before the inductor current reaches zero amperes, the inductor current will trigger the body diode of switch S102, so that the voltage Vsw100 is equal to -VD, which is opposite to the voltage VD of the body diode of switch S102. This means that the main comparator of the ZCD detects the zero current condition too early, and

[0053] If the switch S102 is turned off after the inductor current reaches zero amperes, the inductor current will continue to flow through the switch S102, so the voltage Vsw100 is equal to the product of the inductor current value and the on-resistance of the N-type power switch S102, which means that the main comparator of the ZCD detects the zero current state too late.

[0054] The ZCD turn is then used to correct for premature or late detection, as described in detail below. The ZCD turn block also has a comparator that compares the voltage Vsw100 with the voltage PWRGND100 and adjusts a correction voltage, described below. This correction voltage Vcorr300 then changes the offset voltage of the main comparator via a current, described below.

[0055] Figure 2 Is shown in conjunction with Figure 1 A timing chart illustrating an operation example of the DC-DC converter circuit 100 is described, and more specifically, the operation of the zero current detection circuit 101 is shown.

[0056] Figure 2 include:

[0057] - trace 201 showing the temporal evolution of the pulse voltage Pon100;

[0058] - trace 202 showing the temporal evolution of the pulse voltage Non100;

[0059] - trace 203 showing the temporal evolution of the control voltage Pdrv100;

[0060] - trace 204 showing the temporal evolution of the control voltage Ndrv100;

[0061] - trace 205 showing the temporal evolution of the input current IL101 of the coil L101;

[0062] - trace 206 showing the temporal evolution of voltage Vsw100; and

[0063] - Trace 207 showing the temporal evolution of the control voltage VZCD100.

[0064] Each rising edge of the pulse voltage Pon100 triggers a rising edge of the control voltage Pdrv100. This causes the input voltage Vin100 to be transferred to the coil L101. As a result, the current IL101 increases. Similarly, each falling edge of the pulse voltage Pon100 triggers a falling edge of the control voltage Pdrv100, thereby stopping the rise of the current IL101.

[0065] Each rising edge of the pulse voltage Non100 causes a rising edge of the control voltage Ndrv100. This causes the reference voltage GND100 to be transferred to the coil L101. As a result, the current IL101 decreases.

[0066] However, the falling edge of the pulse signal Non100 does not result in a falling edge of the control voltage Ndrv100. The falling edge of the pulse signal Non100 is controlled by the driver circuit 102 based on the internal delay of the circuit 102 configuration and based on the control voltage VZCD100 provided by the zero current detection circuit 101. More specifically, the falling edge of the control voltage Ndrv100 should occur when the current IL101 reaches zero amperes.

[0067] The magnitude of threshold voltage Vos 101 should be set to compensate for the internal offset voltage of comparator 101-Comp and to account for delay Tdrv 100 of driver circuit 102. Delay Tdrv 100 corresponds to the duration between the time when the driver circuit detects the rising edge of control voltage VZCD 100 and the time when the driver circuit causes the falling edge of control voltage Ndrv 100. However, due to PVT variations, threshold voltage Vos 101 should generally be adjusted in real time to ensure high accuracy of DC-DC converter circuit 100.

[0068] Figure 3 Is shown in conjunction with Figure 1 A block diagram of an embodiment of a zero current detection circuit 300 of a similar type to the zero current detection circuit 100 is depicted.

[0069] The zero current detection circuit 300, also referred to herein as a zero current detector 300 or a ZCD circuit 300, includes:

[0070] - Logic circuit 301 (logic control);

[0071] - Comparator 302 (comparator);

[0072] - Circuit 303 (push right); and

[0073] - Circuit 304 (ZCD transition).

[0074] The logic circuit 301 is the main control circuit of the ZCD circuit 300. The logic circuit 301 provides a similar Figure 1According to an example, the logic circuit 301 also provides internal voltages and currents, such as voltages ACT300, ACTB300, Poni300, Noni300, AfterN300 and NdrviB300, which will be combined with Figures 4 to 12 The example of logic circuit 301 will be combined with Figure 12 Describe in more detail.

[0075] According to an example, the logic circuit 301 receives an internal reset voltage RSTN300 (combined with Figures 4 to 12 which are described in more detail) and external voltages, such as:

[0076] - Combine Figures 4 to 12 A more detailed description of the enable voltage EN300;

[0077] - Voltage Pon300, its type and combination Figure 1 The voltage described is similar to Pon100 and is combined Figures 4 to 12 Describe it in more detail; and

[0078] - Voltage Ndrv300, its type and combination Figure 1 The voltage described is similar to Ndrv100 and is combined with Figures 4 to 12 Describe it in more detail.

[0079] Comparator 302 is the main comparator of zero current detection circuit 300. Type and combination of comparator 302 Figure 1 According to an example, the comparator 302 receives the following voltages and currents: voltage ACTB300, Ndrvi300, PWRGND100, Vsw100, VPP300 and VPN300, which will be combined Figures 4 to 12 Described in more detail; and currents Icorr300 and IcorrAVS300, which will be combined Figures 4 to 12 Describe in more detail.

[0080] According to an example, the comparator 302 is configured to generate a reset voltage RSTN300 and a voltage VBP300, which are combined with Figures 4 to 12 This is described in more detail. According to an example, voltage VBP300 is a bias voltage.

[0081] The combination of circuits 303 and 304 forms a Figure 1 The auto-calibration circuit 101-CAL is a similar type of auto-calibration circuit as described.

[0082] Circuit 303 is a circuit capable of detecting when the internal offset voltage of comparator 302 causes an erroneous detection of the monitored current. More specifically, due to the value of the offset voltage, circuit 303 is capable of generating a push signal whenever the comparator detects that the monitored current is positive. The operation of circuit 303 will be combined with Figure 6 Provide a description.

[0083] According to an example, the circuit 303 receives the voltage VBP300, the correction voltage Vcorr300 and the voltage SWON300, which are combined Figures 4 to 12 Describe in more detail.

[0084] According to an example, the circuit 303 is configured to generate a voltage ACT300 and a current IPR300 . According to an example, the current IPR300 is provided to the comparator 302 .

[0085] As previously described, circuit 304 is part of the auto-calibration circuit and is used to correct the offset voltage of comparator 302. For example, circuit 304 receives voltages Poni300, Noni300, AfterN300, ACT300, Vsw100, and reference voltage PWRGND100.

[0086] For example, circuit 304 is configured to generate the following voltages and currents:

[0087] - Correction voltage Vcorr300;

[0088] - Voltage SWON300;

[0089] - current Icorr300; and

[0090] - Current IcorrAVS300.

[0091] Figure 4 An example of a logic circuit 400 is shown in more detail for implementing the combined Figure 3 The logic circuit 301 of the zero current detection circuit 300 is described.

[0092] As described above, the logic circuit 400 receives the voltages Pon 300 , EN 300 , and Ndrv 300 .

[0093] For example, logic circuit 400 includes three inverters INV401, INV402, and INV403, and a NOR gate NOR401. Inverter INV401 receives voltage Pon300, and inverter INV402 receives voltage EN300. A first input of NOR gate NOR401 is coupled to, and preferably connected to, the output of inverter INV401, and a second input of NOR gate NOR402 is coupled to, and preferably connected to, the output of inverter INV402 providing voltage ENiB400. An input of inverter INV403 is coupled to, and preferably connected to, the output of inverter INV402.

[0094] The logic circuit 400 further includes a flip-flop FF401 , an inverter INV404 , and three NOR gates NOR402 , NOR403 , and NOR404 .

[0095] The trigger FF401 is a D-type trigger, which includes three inputs R, CLK and D, and two outputs Q and The input D of the flip-flop FF401 receives the power supply voltage AVD100, and the input CLK of the flip-flop FF401 is coupled to, preferably connected to, the output of the inverter INV404 and receives the voltage PoniB400. The input of the inverter INV404 is coupled to, preferably connected to, the output of the NOR gate NOR401 providing the voltage Poni300.

[0096] A first input of NOR gate NOR402 is coupled to, preferably connected to, output Q of flip-flop FF401, and a second input of NOR gate NOR402 is coupled to, preferably connected to, the output of NOR gate NOR403. The output of NOR gate NOR402 is coupled to, preferably connected to, a first input of NOR gate NOR403.

[0097] A second input of NOR gate NOR 403 is coupled to, and preferably connected to, the output of NOR gate NOR 401. A third input of NOR gate NOR 403 receives reset voltage RST 300, and a fourth input of NOR gate NOR 403 receives voltage ENiB 300.

[0098] A first input of NOR gate NOR404 provides voltage Noni300 and is coupled to, preferably connected to, the output of NOR gate NOR403, and a second input of NOR gate NOR404 receives voltage ENiB400. An output of NOR gate NOR404 is coupled to, preferably connected to, a reset input R of flip-flop FF401.

[0099] Logic circuit 400 further includes two inverters INV405 and INV406. The input of inverter INV405 is coupled to, preferably connected to, the output of NOR gate NOR403, and the output of inverter INV405 is coupled to, preferably connected to, the input of inverter INV406. The output of inverter INV406 provides voltage NON-ZCD300.

[0100] The logic circuit 400 further includes a second flip-flop FF402 , two inverters INV407 and INV408 , a level shifter LS401 (LS), another NOR gate NOR405 , and a delay element D401 .

[0101] The trigger FF402 is a D-type trigger, which includes three inputs R, CLK and D, and two outputs Q and . Input D of flip-flop FF402 receives voltage Poni300. Input CLK of flip-flop FF402 receives voltage NdrviB300 and is coupled to, preferably connected to, the output of inverter INV407 and the input of inverter INV408. The input of inverter INV407 is coupled to, preferably connected to, the output of level shifter LS401, and the output of inverter INV408 provides voltage Ndrvi300. According to an example, the input of level shifter LS401 receives voltage Ndrv300. Output Q of flip-flop FF402 provides voltage AfterN300 and is coupled to, preferably connected to, the input of delay element D401.

[0102] The output of delay element D401 provides voltage AfterNRST400 and is coupled to, preferably connected to, a first input of NOR gate NOR405. A second input of NOR gate NOR405 receives voltage ENiB400. The output of NOR gate NOR405 is coupled to, preferably connected to, a reset input R of flip-flop FF402.

[0103] Logic circuit 400 also includes two NOR gates NOR406 and NOR407 and two inverters INV409 and INV410. A first input of NOR gate NOR406 receives voltage Poni300, and a second input of NOR gate NOR406 is coupled to, and preferably connected to, the output of NOR gate NOR407. The output of NOR gate NOR406 is coupled to, and preferably connected to, the input of inverter INV409 and to the first input of NOR gate NOR407. The output of inverter INV409 provides voltage ACT300 and is coupled to, and preferably connected to, the input of inverter INV410. The output of inverter INV410 provides voltage ACTB300.

[0104] A second input of the NOR gate NOR 407 receives a voltage ENiB 400 , and a third input of the NOR gate NOR 407 receives a voltage AfterNRST 400 .

[0105] Figure 5 An example of a comparator 500 is shown in more detail, which is used to implement the combined Figure 1 The main comparator 101-COMP of the zero current detection circuit 101 described, or combined with Figure 3 The main comparator 302 of the zero voltage detection circuit 300 is described.

[0106] As described above, the comparator 500 receives the voltages ACTB300 , NdrviB300 , PWRGND100 , Vsw100 , VPP300 , VPN300 and the currents Icorr300 , IcorrAVS300 and IPR300 .

[0107] For example, the comparator 500 includes a PMOS transistor T501 that receives a voltage ACT300 at its gate terminal. The source terminal of the transistor T501 is coupled to, preferably connected to, a node providing a power supply voltage AVD100. The drain terminal of the transistor T501 is coupled to, preferably connected to, a gate terminal of the first differential pair. The transistor T501 is, for example, formed by a circuit similar to that of the first differential pair. Figure 3 The circuit 301 described or combined Figure 4 The circuit control of the circuit 400 is described. The transistor T501 is used to turn off the comparator 400 when needed.

[0108] The first differential pair includes two PMOS transistors T502 and T503. The source terminals of transistors T502 and T503 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the source terminal of transistor T501 and to a node providing power supply voltage AVD100. The gate terminals of transistors T502 and T503 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the drain terminal of transistor T501.

[0109] Comparator 500 also includes a PMOS transistor T504, an NMOS transistor T513, and a current source C501. The source terminal of transistor T504 is coupled to, preferably connected to, a node providing a power supply voltage AVD100. The drain terminal of transistor T504 receives a bias voltage VBP300. The gate terminal of transistor T504 is coupled to, preferably connected to, the gate terminals of transistors T502 and T503, and receives bias voltage VBP300. The source terminal of transistor T513 receives the current generated by current source C501. The drain terminal of transistor T513 is coupled to, preferably connected to, the drain terminal of transistor T504. The gate terminal of transistor T513 receives voltage ACT300. Current source C501 receives reference voltage GND100. Transistors T504 and T513 and current source C501 are used for biasing.

[0110] Comparator 500 also includes two PMOS transistors T514 and T515, two NMOS transistors T516 and T517, and resistor R503. The source terminal of transistor T514 is coupled to, and preferably connected to, a node providing power supply voltage AVD100. The drain terminal of transistor T514 is coupled to, and preferably connected to, the gate terminal of transistor T515 and the drain terminal of transistor T516. The gate terminal of transistor T514 receives bias voltage VBP300. The source terminal of transistor T515 receives bias voltage VBP300. The drain terminal of transistor T514 is coupled to, and preferably connected to, the first terminal of resistor R503. The source terminal of transistor T516 is coupled to, and preferably connected to, the source terminal of transistor T517. The gate terminal of transistor T516 receives voltage ACTB300. The gate terminal of transistor T517 receives voltage ACT300. When the voltage ACT300 is equal to a high level, the transistors T514 to T517 are used to quickly pull down the bias voltage VBP300 .

[0111] For example, comparator 500 further includes a second differential pair comprising two PMOS transistors T505 and T506. The source terminal of transistor T505 is coupled to, and preferably connected to, the drain terminal of transistor T502. The source terminal of transistor T506 is coupled to, and preferably connected to, the drain terminal of transistor T503. The gate terminals of transistors T505 and T506 are coupled to, and preferably connected to, each other, and to, and preferably connected to, a node receiving voltage VPP300.

[0112] For example, comparator 500 further includes a level shifter LS501 (LS-RST) and an inverter INV501. The input of level shifter LS501 is coupled to, and preferably connected to, the drain terminal of transistor T506. The output of level shifter LS501 is coupled to, and preferably connected to, the input of inverter INV501. The output of inverter INV501 provides reset voltage RSTN300.

[0113] For example, the comparator 500 further includes a current mirror including two NMOS transistors T507 and T508. The drain terminal of the transistor T507 is coupled to, preferably connected to, the drain terminal of the transistor T505 and to the gate terminals of the transistors T507 and T508. The drain terminal of the transistor T508 is coupled to, preferably connected to, the drain terminal of the transistor T506.

[0114] For example, comparator 500 further includes a third differential pair comprising two NMOS transistors T509 and T510. The source terminal of transistor T509 is coupled to, and preferably connected to, the source terminal of transistor T507. The source terminal of transistor T510 is coupled to, and preferably connected to, the source terminal of transistor T508. The gate terminals of transistors T509 and T510 are coupled to, and preferably connected to, each other, and to, and preferably connected to, a node receiving voltage VPN300.

[0115] According to an example, current Icorr300 can be provided to the comparator 500 at the source terminals of transistors T508 and T510 .

[0116] For example, comparator 500 further includes a PMOS transistor T518. The source terminal of transistor T518 receives current IcorrAVS300 and current IRP300. The drain terminal of transistor T518 is coupled to, and preferably connected to, the drain terminal of transistor T509. The gate terminal of transistor T518 is coupled to, and preferably connected to, a node receiving voltage VPP300.

[0117] Comparator 500 also includes two resistors R501 and R502. A first terminal of resistor R501 is coupled to, preferably connected to, the drain terminal of transistor T509, and a second terminal of resistor R501 is coupled to, preferably connected to, a node receiving reference voltage PWRGND100. A first terminal of resistor R502 is coupled to, preferably connected to, the drain terminal of transistor T510, and a second terminal of resistor R502 is coupled to, preferably connected to, a node receiving voltage Vsw100.

[0118] For example, transistors T502, T503, T507, and T508 and resistors R501 and R502 form a comparator 500. For example, transistors T505, T506, T509, and T510 are protection devices.

[0119] Comparator 500 also includes, for example, a level shifter LS502 (LS) and an NMOS transistor T511. The input of level shifter LS502 receives voltage NdrviB300. The output of level shifter LS502 is coupled to, and preferably connected to, the gate terminal of transistor T511. The drain terminal of transistor T511 is coupled to, and preferably connected to, the drain terminals of transistors T506 and T508. The source terminal of transistor T511 receives reference voltage PWRGND100.

[0120] For example, comparator 500 further includes a level shifter LS503 (LS) and an NMOS transistor T512. The input of level shifter LS503 receives voltage ACTB300. The output of level shifter LS503 is coupled to, and preferably connected to, the gate terminal of transistor T512. The drain terminal of transistor T512 is coupled to, and preferably connected to, the drain terminals of transistors T505 and T507. The source terminal of transistor T512 receives reference voltage PWRGND100.

[0121] According to an example, the comparator 500 does not use the same ground domain as other circuits of the zero current detection circuit. In this case, the level shifters LS501 , LS502 and LS503 are used to switch the ground domain within the comparator 500 , for example.

[0122] Figure 6 More details are shown for achieving the combination Figure 3 An example of a circuit 600 of the circuit 303 of the zero current detection circuit 300 is described.

[0123] As previously described, circuit 600 receives voltages VACT300 , VBP300 , SWON300 , and Vcorr300 , and current IPR300 .

[0124] For example, the circuit 600 includes a PMOS transistor T601 that receives a voltage ACT300 at its gate terminal. The source terminal of the transistor T601 is coupled to, preferably connected to, a node providing a power supply voltage AVD100. The drain terminal of the transistor T601 is coupled to, preferably connected to, a gate terminal of the first differential pair. The transistor T601 is coupled to, preferably connected to, a gate terminal of the first differential pair. Figure 3 The circuit 301 described or combined Figure 4 A similar type of circuit control is described for circuit 400. Transistor T601 is used to shut down circuit 600 when needed.

[0125] For example, the first differential pair includes two PMOS transistors T602 and T603. The source terminal of transistor T602 and the source terminal of transistor T603 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the source terminal of transistor T601 and to a node providing power supply voltage AVD100. The gate terminal of transistor T602 and the gate terminal of transistor T603 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the drain terminal of transistor T601.

[0126] For example, circuit 600 further includes a current source C601 and an NMOS transistor T615. A source terminal of transistor T615 receives current from current source C601. A drain terminal of transistor T615 is coupled to, and preferably connected to, a drain terminal of transistor T602. A gate terminal of transistor T615 receives voltage ACT300.

[0127] Circuit 600 also includes two PMOS transistors T616 and T617, two NMOS transistors T618 and T619, and a resistor R601. The source terminal of transistor T616 is coupled to, preferably connected to, a node providing power supply voltage AVD100. The drain terminal of transistor T616 is coupled to, preferably connected to, the gate terminal of transistor T617 and to the drain terminal of transistor T619. The gate terminal of transistor T616 receives bias voltage VBP300. The source terminal of transistor T617 receives bias voltage VBP300. The drain terminal of transistor T617 is coupled to, preferably connected to, the first terminal of resistor R601. The second terminal of resistor R601 is coupled to, preferably connected to, the drain terminal of transistor T618. The source terminal of transistor T618 is coupled to, preferably connected to, the source terminal of transistor T619. The gate terminal of transistor T619 receives voltage ACTB300. The gate terminal of transistor T618 receives voltage ACT300. When voltage AZCT300 is high, transistors T616 to T619 are used to quickly pull down bias voltage VBP300.

[0128] For example, circuit 600 further includes three transistors T604, T605, and T606. The source terminal of transistor T604 is coupled to, and preferably connected to, the drain terminal of transistor T603. The drain terminal of transistor T604 is coupled to, and preferably connected to, the drain terminals of transistors T605 and T606. The gate terminals of transistors T604 and T605 are coupled to, and preferably connected to, each other. The gate terminal of transistor T606 is coupled to, and preferably connected to, a node that receives correction voltage VCorr600. For example, the source terminals of transistors T605 and T606 are referenced to ground.

[0129] For example, the circuit 600 further includes two inverters INV601 and INV602, a flip-flop FF601, and a NAND gate NAND601. For example, the flip-flop FF601 is a D-type flip-flop, including three inputs R, CLK, and D, and two outputs Q and .

[0130] The input of inverter INV601 is coupled to, preferably connected to, the drain terminals of transistors T604, T605, and T606. The output of inverter INV601 is coupled to, preferably connected to, the input of inverter INV602. The output of inverter INV602 is coupled to, preferably connected to, the CLK input of flip-flop FF601. For example, the D input of flip-flop FF601 receives the power supply voltage AVD100. The output of flip-flop FF601 is coupled to, preferably connected to, the input of inverter INV602. Coupled to, preferably connected to, a first input of NAND gate NAND 601. A second input of NAND gate NAND 601 receives voltage 16Cy600. A third input of NAND gate NAND 601 receives voltage 2Cy600. A fourth input of NAND gate NAND 601 receives voltage ACT300. An output of NAND gate NAND 601 is coupled to, preferably connected to, the gate terminals of transistors T604 and T605.

[0131] For example, circuit 600 further includes four transistors T607, T608, T609, and T610. The source terminal of transistor T607 is coupled to, preferably connected to, a node providing power supply voltage AVD100. The drain terminal of transistor T607 is coupled to, preferably connected to, the source terminal of transistor T608. The gate terminal of transistor T607 is coupled to, preferably connected to, the gate terminals of transistors T602 and T603.

[0132] The drain terminal of transistor T608 is coupled to, and preferably connected to, the drain terminals of transistors T609 and T610. The gate terminals of transistors T608 and T609 are coupled to, and preferably connected to, each other. The gate terminal of transistor T610 is coupled to, and preferably connected to, a node receiving correction voltage VCorr600. The source terminals of transistors T609 and T610 are referenced to ground.

[0133] For example, the circuit 600 further includes two inverters INV603 and INV604, a flip-flop FF602 and a NAND gate NAND602. The flip-flop FF602 is a D-type flip-flop including three inputs R, CLK and D, and two outputs Q and .

[0134] The input of inverter INV603 is coupled to, preferably connected to, the drain terminals of transistors T608, T609, and T610. The output of inverter INV603 is coupled to, preferably connected to, the input of inverter INV604. The output of inverter INV604 is coupled to, preferably connected to, the CLK input of flip-flop FF602. The D input of flip-flop FF602 receives the power supply voltage AVD100. The output of flip-flop FF602 is coupled to, and preferably connected to, a first input of a NAND gate NAND 602. A second input of the NAND gate NAND 602 receives a voltage 16Cy600. A third input of the NAND gate NAND 602 receives a voltage 8Cy600. A fourth input of the NAND gate NAND 602 receives a voltage ACT300. An output of the NAND gate NAND 602 is coupled to, and preferably connected to, the gate terminals of transistors T608 and T609.

[0135] For example, circuit 600 further includes a second differential pair comprising two PMOS transistors T611 and T612. The source terminals of transistors T611 and T612 are coupled to, preferably connected to, a node providing power supply voltage AVD100. The gate terminals of transistors T611 and T612 are coupled to, preferably connected to, each other, and to, preferably connected to, a node receiving voltage VBP300.

[0136] For example, circuit 600 further includes two PMOS transistors T613 and T614. The source terminal of transistor T613 is coupled to, and preferably connected to, the drain terminal of transistor T611. The source terminal of transistor T614 is coupled to, and preferably connected to, the drain terminal of transistor T612. The drain terminals of transistors T613 and T614 receive current IPR300.

[0137] For example, circuit 600 further includes circuit 610 that provides voltages 2Cy600, 8Cy600, and 16Cy600.

[0138] For example, circuit 610 includes a NOR gate NOR601 that receives voltage I6Cy600 at a first input and current SWON300 at a second input.

[0139] For example, the circuit 610 further includes five flip-flops FF603, FF6064, FF605, FF606, and FF607. The flip-flops FF603 to FF607 are D-type flip-flops, each of which includes three inputs R, CLK, and D, and two outputs Q and The output of the NOR gate NOR601 is coupled to, preferably connected to, the CLK terminal of the flip-flop FF603. The output of the flip-flop FF603 Coupled to, preferably connected to, the input D of the flip-flop FF603 and to the CLK terminal of the flip-flop FF604. The output of the flip-flop FF604 Coupled to, preferably connected to, input D of flip-flop FF604 and to the CLK terminal of flip-flop FF605. Output Q of flip-flop FF604 provides voltage 2Cy600. Output of flip-flop FF605 Coupled to, preferably connected to, input D of flip-flop FF605 and to the CLK terminal of flip-flop FF606. Output of flip-flop FF606 Coupled to, preferably connected to, input D of flip-flop FF606 and to the CLK terminal of flip-flop FF607. Output Q of flip-flop FF606 provides voltage 8Cy600. Output Q of flip-flop FF607 provides voltage 16Cy600.

[0140] Circuit 600 is used to verify the detection of the inductor current and ensure that the inductor current is negative, i.e., less than zero, to allow the zero current detection circuit to operate properly. Operation is divided into two phases. During the first phase, after two first cycles of the SWON signal, if the inductor current is positive, transistor T613 becomes conductive to provide more offset current to the main current comparator by injecting more current into the main current comparator. In the second phase, after eight first cycles of the SWON signal, if the inductor current is still positive, transistor T614 becomes conductive to provide more offset current to the main current comparator by injecting more current into the main current comparator.

[0141] Figure 7 More details are shown for achieving the combination Figure 3 An example of a circuit 700 of the circuit 304 of the zero current detection circuit 300 is described.

[0142] As previously described, the circuit 700 receives the voltages Poni300, Noni300, AfterN300, and ACT300.

[0143] For example, the circuit 700 includes a PMOS transistor T701 that receives a voltage ACT300 at its gate terminal. The source terminal of the transistor T701 is coupled to, preferably connected to, a node providing a power supply voltage AVD100. The drain terminal of the transistor T701 is coupled to, preferably connected to, a gate terminal of a first differential pair. For example, the transistor T701 is coupled to, preferably connected to, a gate terminal of a first differential pair. Figure 3 The circuit 301 described or combined Figure 4 A similar type of circuit control is described for circuit 400. Transistor T701 is used to shut down circuit 700 when needed.

[0144] For example, the first differential pair includes two PMOS transistors T702 and T703. The source terminal of transistor T702 and the source terminal of transistor T703 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the source terminal of transistor T701 and to a node providing power supply voltage AVD100. The gate terminal of transistor T702 and the gate terminal of transistor T703 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the drain terminal of transistor T701.

[0145] For example, circuit 700 also includes two PMOS transistors T704 and T705 and a current source CS701. The source terminal of transistor T704 is coupled to, and preferably connected to, a node providing a power supply voltage AVD100. The drain terminal of transistor T704 is coupled to, and preferably connected to, the drain terminal of transistor T705. The source terminal of T705 is coupled to, and preferably connected to, an input of current source CS701. The gate terminal of transistor T704 is coupled to, and preferably connected to, the gate terminals of transistors T702 and T703. The gate terminal of transistor T705 receives a voltage ACT300.

[0146] For example, circuit 700 also includes two PMOS transistors T731 and T732, two NMOS transistors T733 and T734, and a resistor T704. The source terminal of transistor T731 is coupled to, preferably connected to, a node receiving voltage AVD100. The drain terminal of transistor T731 is coupled to, preferably connected to, the drain terminal of transistor T734 and to the gate terminal of transistor T732. The drain terminal of transistor T731 is coupled to, preferably connected to, the source terminal of transistor T732 and to the gate terminal of transistor T704. The drain terminal of transistor T732 is coupled to, preferably connected to, the first terminal of resistor R704. The second terminal of resistor R704 is coupled to, preferably connected to, the drain terminal of transistor T733. The source terminal of transistor T733 is coupled to, preferably connected to, the source terminal of transistor T734. The gate terminal of transistor T733 receives voltage ACT300. The gate terminal of transistor T734 receives voltage ACTB300. These four transistors form a fast startup circuit, so that when the voltage ACT300 reaches a high level, the voltage VBPT700 can be quickly pulled down.

[0147] For example, circuit 700 further includes a PMOS transistor T706 and an NMOS transistor T707. The source terminal of transistor T706 is coupled to, and preferably connected to, the drain terminal of transistor T703. The drain terminal of transistor T706 is coupled to, and preferably connected to, the drain terminal of transistor T707. The gate terminal of transistor T706 receives a voltage AfterNiB700. The gate terminal of transistor T707 receives a voltage AfterNiNor700.

[0148] For example, the circuit 700 also includes a combination of Figure 8 The clamping circuit CL701 (CLAMP) is described in more detail. The output of the clamping circuit CL701 is coupled to, preferably connected to, the source terminal of the transistor T707.

[0149] For example, the circuit 700 further includes a current mirror including two NMOS transistors T708 and T709. The drain terminal of the transistor T708 is coupled to, preferably connected to, the gate terminals of the transistors T708 and T709 and to the drain terminal of the transistor T702. The drain terminal of the transistor T709 is coupled to, preferably connected to, the drain terminal of the transistor T707.

[0150] For example, circuit 700 further includes a differential pair of two NMOS transistors, T710 and T711. The source terminal of transistor T710 is coupled to, preferably connected to, the source terminal of transistor T708. The source terminal of transistor T711 is coupled to, preferably connected to, the source terminal of transistor T709. The gate terminals of transistors T710 and T711 are coupled to, preferably connected to, each other, and to, preferably connected to, a node receiving voltage VPNT700.

[0151] For example, circuit 700 further includes two resistors R701 and R702. A first terminal of resistor R701 is coupled to, preferably connected to, the drain terminal of transistor T710, and a second terminal of resistor R701 is coupled to, preferably connected to, a node receiving voltage PWRGND100. A first terminal of resistor R702 is coupled to, preferably connected to, the drain terminal of transistor T711, and a second terminal of resistor R702 is coupled to, preferably connected to, a node receiving voltage Vsw100.

[0152] For example, circuit 700 further includes a level shifter LS701 and an NMOS transistor T711-2. The input of level shifter LS701 receives voltage ACTB300. The output of level shifter LS701 is coupled to, and preferably connected to, the gate terminal of transistor T711-2. The drain terminal of transistor T711-2 is coupled to, and preferably connected to, the drain terminal of transistor T708. The source terminal of transistor T711-2 is coupled to, and preferably connected to, the second terminal of resistor R701 and to a node receiving reference voltage PWRGND100.

[0153] For example, the circuit 700 further includes a circuit 701 (PROBE) capable of exchanging voltages with the control circuit 301 of the zero current detection circuit. More specifically, the circuit 701 provides a voltage END700 to the control circuit 301 and receives voltages Noni300 and NoniB300 from the control circuit 301. Furthermore, the input of the circuit 701 is coupled to, preferably connected to, the drain terminal of the transistor T711. Figure 11 An example of circuit 701 is described in more detail.

[0154] For example, circuit 700 also includes four transistors T712, T713, T714, and T714-2. The source terminal of transistor T712 receives a power supply voltage AVD100. The drain terminal of transistor T712 is coupled to, and preferably connected to, the drain and gate terminals of transistor T714-2. The drain terminal of transistor T712 provides voltage VBNT700. The gate terminal of transistor T712 is coupled to, and preferably connected to, the gate terminals of transistors T703 and T713. The source terminal of transistor T713 is coupled to, and preferably connected to, a node providing power supply voltage AVD100. The drain terminal of transistor T713 is coupled to, and preferably connected to, the source terminal of transistor T714. The drain terminal of transistor T714 is coupled to, and preferably connected to, the drain terminals of transistors T706 and T707. The source terminal of transistor T714-2 receives reference voltage GND100.

[0155] For example, the circuit 700 also includes a combination of Figure 10 The circuit 702 (RESCUE) is described in more detail. The output of the circuit 702 is coupled to, preferably connected to, the gate terminal of the transistor T714. The circuit 702 receives the combined Figure 10 Several voltages are described.

[0156] For example, the circuit 700 further includes two initialization circuits 703 (NLOOK BOOSTING) and 704 (NLOOK INIT), which are combined with Figure 9The output of circuit 702 is coupled to, and preferably connected to, the drain terminal of transistor T714. Circuit 703 and circuit 704 receive a combined Figure 10 Several voltages are described.

[0157] For example, the circuit 700 further includes three PMOS transistors T715 , T717 , and T718 , an NMOS transistor T716 , a NOR gate NOR701 , a flip-flop FF701 , and an inverter INV701 .

[0158] The first input of the NOR gate NOR701 receives the voltage AfterNi700. The second input of the NOR gate NOR701 is coupled to, preferably connected to, the output of the circuit 702 providing the voltage RESCUE700. The third input of the NOR gate NOR701 is connected to the output of the flip-flop FF701. The voltage INIT 700 is received. The output of the NOR gate NOR 701 is coupled to, preferably connected to, the input of the inverter INV 701 and to the gate terminal of the transistor T715. The output of the inverter INV 701 is coupled to, preferably connected to, the gate terminal of the transistor T717.

[0159] About the trigger FF701:

[0160] - Input D of flip-flop FF701 receives voltage AVD100;

[0161] - The clock input CLK of the flip-flop FF701 receives the voltage NoniB300;

[0162] - The inverting reset input of the flip-flop FF701 receives the voltage EN300; and

[0163] - Output Q of flip-flop FF701 provides voltage InitB700.

[0164] The drain terminals of transistors T715 and T716 are coupled to, preferably connected to, the drain terminal of transistor T706, to the drain terminal of transistor T717, and to the source terminal of transistor T718. The source terminals of transistors T715 and T716 are coupled to, preferably connected to, each other. The drain terminal of transistor T717 is coupled to, preferably connected to, the drain terminal of transistor T718.

[0165] For example, circuit 700 also includes a comparator COMP701, two NMOS transistors T719 and T735, a current source CS702, and a capacitor C701. A first input (+) of comparator COMP701 is coupled to, and preferably connected to, the drain terminal of transistor T717 and the drain terminal of transistor T718. A second input (-) of comparator COMP701 is coupled to, and preferably connected to, the output of comparator COMP701 and the source terminals of transistors T715 and T716. A power supply terminal of comparator COMP701 is coupled to, and preferably connected to, the drain terminal of transistor T735. A source terminal of transistor T735 is coupled to, and preferably connected to, an output terminal of current source CS702. Current source CS702 receives reference voltage GND100. A drain terminal of transistor T719 is coupled to, and preferably connected to, the power supply terminal of comparator COMP701. A source terminal of transistor T719 is coupled to, and preferably connected to, a node receiving reference voltage GND300. According to one embodiment, the comparator COMP701 compares the combined Figure 5 The described comparator 500 is more precise.

[0166] For example, circuit 700 further includes capacitor C701 disposed between the drain terminal of transistor T718 and a node receiving reference voltage GND300. Furthermore, capacitor C701 receives voltage VCorr300, which is controlled by voltage AfterN300. Circuit 700 uses voltage AfterN300 to trigger charging and discharging of capacitor C701, and thus voltage VCorr300. More specifically, such charging is triggered by a high level of voltage AfterN300.

[0167] The circuit 700 further includes two PMOS transistors T720 and T721. The gate terminals of the transistors T720 and T721 receive the voltage ACT300. The source terminals of the transistors T720 and T721 receive the power supply voltage AVD100.

[0168] For example, circuit 700 also includes a current mirror including two PMOS transistors T722 and T723. The source terminals of transistors T722 and T723 are coupled to each other, preferably connected to each other, and receive a power supply voltage AVD100. The gate terminals of transistors T722 and T723 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the drain terminal of transistor T720 and to the drain terminal of transistor T722. The drain terminal of transistor T723 provides correction current ICorr300.

[0169] For example, the circuit 700 further includes a PMOS transistor T724. A source terminal of the transistor T724 receives the power supply voltage AVD100. A gate terminal of the transistor T724 is coupled to, and preferably connected to, the gate terminals of the transistors T722 and T723.

[0170] For example, circuit 700 also includes a current mirror including two PMOS transistors T725 and T726. The source terminals of transistors T725 and T726 are coupled to each other, preferably connected to each other, and receive a power supply voltage AVD100. The gate terminals of transistors T725 and T726 are coupled to each other, preferably connected to each other, and are coupled to, preferably connected to, the drain terminal of transistor T725, the drain terminal of transistor T721, and the drain terminal of transistor T724. The drain terminal of transistor T726 provides a correction current ICorrAVS300.

[0171] For example, circuit 700 also includes two NMOS transistors T727 and T728 and a resistor R703. The drain terminal of transistor T727 is coupled to, and preferably connected to, the drain terminal of transistor T722. The source terminal of transistor T727 is coupled to, and preferably connected to, a first terminal of resistor R703. The second terminal of resistor R703 is coupled to, and preferably connected to, the drain terminal of transistor T728. The source terminal of transistor T728 is coupled to, and preferably connected to, a node providing reference voltage GND300. The gate terminal of transistor T727 is coupled to, and preferably connected to, the source terminal of transistor T728. The gate terminal of transistor T728 receives voltage ACTB300.

[0172] For example, circuit 700 also includes two NMOS transistors T729 and T730. The drain terminal of transistor T729 is coupled to, and preferably connected to, the drain terminals of transistors T724 and T725. The source terminal of transistor T729 is coupled to, and preferably connected to, a node providing reference voltage GND300. The gate terminal of transistor T729 is coupled to, and preferably connected to, the gate terminals of transistors T714-2 and T719. The drain terminal of transistor T730 is coupled to, and preferably connected to, the gate terminal of transistor T729. The source terminal of transistor T730 is coupled to, and preferably connected to, a node providing reference voltage GND300. The gate terminal of transistor T730 receives voltage ACT300.

[0173] Circuit 700 operates as follows. When voltage ACT300 reaches a high level corresponding to a logic 1, the zero current detection circuit begins operating. During the period when voltage AfterN300 is at a logic 1, comparator COMP701 of circuit 700 compares voltages PWRGND100 and Vsw100. Sampling transistors T715 to T718 conduct, and the voltage across sample-and-hold capacitor C701 changes. Correction voltage Vcorr300 changes currents Icorr and IcorrAVS applied to the main comparator of circuit 500.

[0174] When voltage ACT300 reaches a low level corresponding to logic 0, the current comparator and other sub-circuits of the zero-current detection circuit are turned off to save power, and sampling transistors T715 to T718 are also turned off. However, by using buffer COMP701, which clamps the voltage between the source and drain of transistors T717 and T718 to reduce leakage, the voltage on capacitor C701 can be maintained even after a long period of time.

[0175] Figure 8 More details are shown for achieving the combination Figure 7 An example of a clamping circuit 800 of circuit 701 of circuit 700 is described.

[0176] For example, the circuit 800 includes a flip-flop FF801. The flip-flop FF801 is a D-type flip-flop including three inputs R, CLK, and D, and two outputs Q and Input D receives the power supply voltage AVD100. Input R receives the voltage ACT300. Input CLK receives the voltage NoniB300.

[0177] For example, circuit 800 further includes a PMOS transistor T801 and an NMOS transistor T802. The source terminal of transistor T801 receives a power supply voltage AVD100. The drain terminal of transistor T801 is coupled to, and preferably connected to, the drain terminal of transistor T802. The source terminal of transistor T802 provides a voltage to an output node OUT800 of circuit 800.

[0178] According to an example, the output node OUT800 is coupled to, preferably connected to, the source terminal of the transistor T707 of the circuit 700. The circuit 800 is used to prevent a rapid discharge that may occur in the source terminal of the transistor T707 of the circuit 700.

[0179] Figure 9 More details are shown for achieving the combination Figure 7 An example of a boost circuit 900 is described for circuit 703 of circuit 700 .

[0180] For example, circuit 900 includes a resistor R901, a PMOS transistor T901, and two NMOS transistors T902 and T903. A first terminal of resistor R901 is coupled to, and preferably connected to, a node providing a power supply voltage AVD100. A second terminal of resistor R901 is coupled to, and preferably connected to, a drain terminal of transistor T902. A source terminal of transistor T901 is coupled to, and preferably connected to, a node providing a power supply voltage AVD100. A drain terminal of transistor T901 is coupled to, and preferably connected to, a gate terminal of transistor T902. The gate terminal of transistor T901 receives voltage VBPT300. A source terminal of transistor T902 is coupled to, and preferably connected to, a drain terminal of transistor T903. A source terminal of transistor T903 is coupled to, and preferably connected to, an output node OUT900 of circuit 900.

[0181] For example, circuit 900 further includes an NMOS transistor T904 and a resistor R902. The drain terminal of transistor T904 is coupled to, preferably connected to, the gate terminal of transistor T902 and to the drain terminal of transistor T901. The source terminal of transistor T904 is coupled to, preferably connected to, a first terminal of resistor R902. The second terminal of resistor R902 is coupled to, preferably connected to, a node that receives reference voltage GND300.

[0182] For example, the circuit 900 further includes three NMOS transistors T905, T906, and T907. The drain terminal of the transistor T905 is coupled to, preferably connected to, its gate terminal and to the drain terminal of the transistor T904. The drain terminal of the transistor T906 is coupled to, preferably connected to, its gate terminal and to the source terminal of the transistor T907. The drain terminal of the transistor T907 is coupled to, preferably connected to, its gate terminal and to a node receiving the reference voltage GND300.

[0183] For example, circuit 900 further includes an NMOS transistor T908. The drain terminal of transistor T908 is coupled to, preferably connected to, the drain terminal of transistor T904. The source terminal of transistor T908 is coupled to, preferably connected to, a node receiving reference voltage GND 300. The gate terminal of transistor T908 receives voltage ENiB 400.

[0184] According to an example, the output node OUT900 is coupled to, preferably connected to, the source terminal of the transistor T707 of the circuit 700. The circuit 900 is used to increase the voltage at the source terminal of the transistor T707 of the circuit 700.

[0185] With some minor modifications, circuit 900 can also provide an example implementation of circuit 704 of circuit 700. In this case, circuit 900 is used to help initialize the voltage at the source terminal of transistor T707 of circuit 700. More specifically, as an example of circuit 704, voltage SWON300 is replaced by voltage INIT300, and voltage ENiB400 is replaced by voltage INITB300.

[0186] Figure 10 More details are shown for achieving the combination Figure 7 Examples of clamping circuits 1000 are described for circuits 700 and 702 .

[0187] For example, the circuit 1000 includes a flip-flop FF1001 and two delay elements D1001 and D1002. The flip-flop FF1001 is a D-type flip-flop, including three inputs R, CLK, and D, and two outputs Q and The input D of flip-flop FF1001 is coupled to, and preferably connected to, the output of delay element D1001. The input of delay element D1001 receives voltage Noni300. The input CLK of flip-flop FF1001 receives voltage Poni300. The input R of flip-flop FF1001 is coupled to, and preferably connected to, the output of delay element D1002. The input of delay element D1002 receives reset voltage RST1000.

[0188] For example, circuit 1000 further includes a PMOS transistor T1001 and an NMOS transistor T1002. The source terminal of transistor T1001 is coupled to, and preferably connected to, a node providing a power supply voltage AVD100. The gate terminal of transistor T1001 is coupled to, and preferably connected to, an output Q of flip-flop FF1001. The source terminal of transistor T1002 is coupled to, and preferably connected to a node providing a voltage GND300. The gate terminal of transistor T1002 is coupled to, and preferably connected to, an output of flip-flop FF1002. .

[0189] For example, circuit 1000 also includes an NMOS transistor T1003, two PMOS transistors T1004 and T1005, and a resistor R1001. The source terminal of transistor T1003 receives a power supply voltage AVD100. The drain terminal of transistor T1003 is coupled to, and preferably connected to, the drain terminal of transistor T1001 and to the drain terminal of transistor T1004. The gate terminal of transistor T1003 receives a voltage VBPT700. The source terminal of transistor T1004 is coupled to, and preferably connected to, the drain terminal of transistor T1005. The gate terminal of transistor T1004 receives a voltage CCM1000. The source terminal of transistor T1005 is coupled to, and preferably connected to, a first terminal of resistor R1001. The second terminal of resistor R1001 is coupled to, and preferably connected to, a node providing a reference voltage GND300.

[0190] For example, circuit 1000 also includes two PMOS transistors T1006 and T1007. The source terminals of transistors T1006 and T1007 are coupled to, preferably connected to, a node providing a power supply voltage AVD100. The gate terminals of transistors T1006 and T1007 are coupled to, preferably connected to, each other, and to, preferably connected to, the drain terminal of transistor T1007 and to the drain terminal of transistor T1003. The drain terminal of transistor T1006 is coupled to, preferably connected to, the drain terminal of transistor T1002 and to the gate terminal of transistor T1002.

[0191] For example, circuit 1000 further includes an NMOS transistor T1008. The source terminal of transistor T1008 is coupled to, and preferably connected to, a node receiving reference voltage GND300. The drain terminal of transistor T1008 is coupled to, and preferably connected to, the gate terminal of transistor T1005 and to the drain terminal of transistor T1003. The gate terminal of transistor T1008 receives voltage VBNT700.

[0192] For example, circuit 1000 also includes two NMOS transistors T1009 and T1010 and a resistor R1002. The drain terminal of transistor T1009 is coupled to, and preferably connected to, the drain terminal of transistor T1003. The source terminal of transistor T1009 is coupled to, and preferably connected to, the source terminal of transistor T1010. The drain terminal of transistor T1010 is coupled to, and preferably connected to, a first terminal of resistor R1002. The gate terminal of transistor T1010 receives voltage VPNT700. The second terminal of resistor R1002 receives voltage Vsw100.

[0193] The circuit 1000 further includes a flip-flop FF1002, a delay element D1003, a NOR gate NOR1001, a NAND gate NAND1001, and an inverter INV1001. The flip-flop FF1002 is a D-type flip-flop having three inputs R, CLK, and D, and two outputs Q and Input D of flip-flop FF1002 is coupled to, and preferably connected to, the output of delay element D1003. The input of delay element D1003 receives voltage Noni300. Input CLK of flip-flop FF1002 receives voltage Poni300. Input R of flip-flop FF1002 is coupled to, and preferably connected to, the output of NOR gate NOR1001. A first input of NOR gate NOR1001 is coupled to, and preferably connected to, the drain terminal of transistor T1003. A second input of NOR gate NOR1001 receives voltage AfterNi700. Output Q of flip-flop FF1002 is coupled to, and preferably connected to, a first input of NAND gate NAND1001. A second input of NAND gate NAND1001 receives voltage Noni300. The output of NAND gate NAND1001 is coupled to, and preferably connected to, the input of inverter INV1001 and provides voltage RESCUEB1000. The output of inverter INV1001 provides voltage RESCUE1000.

[0194] According to an example, voltage RESCUE 1000 is used to control transistor T714 of circuit 700 and voltage RESCUE 1000 is provided to the input of NOR gate NOR 701. Circuit 1000 is used to increase the voltage at the source terminal of transistor T707 of circuit 700.

[0195] According to the example, and refer to Figure 1 , when the current in diode L101 is not equal to zero, circuit 1000 can be used to keep the offset of comparator 101-Comp at the same level.

[0196] Figure 11 More details are shown for achieving the combination Figure 7 An example of a clamp circuit 1100 of circuit 700 and circuit 701 is described.

[0197] For example, the circuit 1100 includes a PMOS transistor T1101. A source terminal of the transistor T1101 is coupled to, preferably connected to, a node providing a power supply voltage AVD100. A gate terminal of the transistor T1101 receives a voltage NoniB300.

[0198] For example, the circuit 1100 further includes two resistors R1101 and R1102. A first terminal of the resistor R1101 is coupled to, preferably connected to, a first terminal of the resistor R1101 and a node providing a supply voltage AVD100.

[0199] For example, circuit 1100 also includes three PMOS transistors T1102, T1103, and T1104, and two NMOS transistors T1105 and T1106. The source terminal of transistor T1102 is coupled to, preferably connected to, the second terminal of resistor R1101. The drain terminal of transistor T1102 is coupled to, preferably connected to, the source terminal of transistor T1103. The drain terminal of transistor T1103 is coupled to, preferably connected to, the source terminal of transistor T1104. The drain terminal of transistor T1104 is coupled to, preferably connected to, the drain terminal of transistor T1105. The source terminal of transistor T1105 is coupled to, preferably connected to, the drain terminal of transistor T1106. The source terminal of transistor T1105 is coupled to, preferably connected to, a node providing reference voltage GND300. The gate terminals of transistors T1104 and T1106 receive voltage Ns21100. The gate terminal of the transistor T1105 receives the voltage NoniB300.

[0200] For example, circuit 1100 also includes five PMOS transistors, T1107, T1108, T1109, T1110, and T1111. The drain terminal of transistor T1107 is coupled to, and preferably connected to, the drain terminal of transistor T1106. The source terminal of transistor T1107 is coupled to, and preferably connected to, a node providing reference voltage GND300. The gate terminals of transistors T1107 and T1108 are coupled to, and preferably connected to, each other, and to, and preferably connected to, the gate terminal of transistor T1103. The two conductive terminals of transistor T1108 are coupled to, and preferably connected to, each other, and to, and preferably connected to, a node providing reference voltage GND300. The drain terminal of transistor T1109 is coupled to, and preferably connected to, the gate terminals of transistors T1108 and T1109. The source terminal of transistor T1108 receives reference voltage GND300. The drain terminal of transistor T1110 is coupled to, preferably connected to, the drain terminals of transistors T1106 and T1107. The source terminal of transistor T1110 receives reference voltage GND300. Two conductive terminals of transistor T1111 are coupled to, preferably connected to, each other, and to, preferably connected to, a node providing reference voltage GND300.

[0201] For example, circuit 1100 further includes a PMOS transistor T1112. The source terminal of transistor T1112 is coupled to, preferably connected to, the second terminal of resistor R1102. The drain terminal of transistor T1112 is coupled to, preferably connected to, the gate terminal of transistor T1103 and to the gate terminals of transistors T1107 and T1108. The gate terminal of transistor T1112 is coupled to, preferably connected to, the gate terminal of transistor T1109 and receives voltage Noni300.

[0202] For example, circuit 1100 further includes an inverter INV1101. The input of inverter INV1101 is coupled to, and preferably connected to, the drain terminals of transistors T1101, T1104, and T1105, and to the gate terminal of transistor T1111. The output of inverter INV1101 provides voltage END700 to the gate terminals of transistors T1102 and T1110. This output of inverter INV1101 also forms the output node of circuit 1100.

[0203] According to an example, the circuit 1100 is used to enable and disable the tuning operation of the offset voltage of the comparator.

[0204] Figure 12 More details are shown for achieving the combination Figure 3 Logic circuit 301 of circuit 300 is described as an example of logic circuit 1200 .

[0205] Logic circuit 1200 includes two inverters INV1201 and INV1202 connected in series. The input of inverter INV1201 receives voltage Pon300, and the output of inverter INV1201 provides voltage PoniB300. The input of inverter INV1202 receives voltage PoniB300, and the output of inverter INV1202 provides voltage Poni300.

[0206] Logic circuit 1200 further includes two inverters INV1203 and INV1204 connected in series. The input of inverter INV1203 receives voltage Non300, and the output of inverter INV1203 provides voltage NoniB300. The input of inverter INV1204 receives voltage NoniB300, and the output of inverter INV1204 provides voltage Noni300.

[0207] Logic circuit 1200 further includes two inverters INV1205 and INV1206 connected in series. The input of inverter INV1205 receives voltage EN300, and the output of inverter INV1205 provides voltage ENiB300. The input of inverter INV1206 receives voltage ENiB300, and the output of inverter INV1206 provides voltage ENi300.

[0208] Logic circuit 1200 further includes two inverters INV1207 and INV1208 connected in series. The input of inverter INV1207 receives voltage ACT300, and the output of inverter INV1207 provides voltage ACTiB300. The input of inverter INV1208 receives voltage ACTiB300, and the output of inverter INV1208 provides voltage ACTi300.

[0209] Logic circuit 1200 also includes two NAND logic gates Nand1201 and Nand1202. Gate Nand1201 provides voltage AfterNiB300 and receives:

[0210] - Voltage AfterN300;

[0211] - Voltage ENi300; and

[0212] - Output of NAND gate Nand1202.

[0213] The NAND gate Nand1202 receives the voltages END700 and Poni300.

[0214] Logic circuit 1200 also includes an inverter INV1209, a flip-flop FF1201, a NOR logic gate NOR1201, and a NOR logic gate NOR1202. The input of inverter INV1209 receives voltage AfterNiB300, and the output of inverter INV1209 is coupled to, and preferably connected to, the clock input CLK of flip-flop FF1201. Input D of flip-flop FF1201 receives voltage AVD100. The reset input of flip-flop FF1201 is coupled to, and preferably connected to, the output of NOR logic gate NOR1201. Output Q of flip-flop FF1201 provides AfterNiN1200. The output of flip-flop FF1201 Provides AfterNiNB1200. NOR gate NOR1201 receives voltage ENi300 and END700. NOR gate NOR1202 receives voltage AfterNiB300 and AfterNiNB1200 and provides voltage AfterNNOR1200.

[0215] Various embodiments and variations have been described herein. Those skilled in the art will appreciate that certain features of these embodiments can be combined, and those skilled in the art will readily conceive of other variations.

[0216] Finally, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A zero current detection circuit (101; 300), comprising: - First comparator (101-Comp; 302 ; 500 ), configured to compare a first voltage ( Vsw100 ) representing a first current ( IL101 ) with a first threshold voltage ( Vos101 ); - a calibration circuit (101-CAL; 303, 304; 700) configured to modify the value of said first threshold voltage (Vos101) according to process, voltage and / or temperature variations.

2. The circuit according to claim 1, wherein The first threshold voltage (Vos101) is an offset voltage of the first comparator (101-Comp; 302; 500).

3. The circuit according to claim 1, wherein The calibration circuit (700) comprises a second comparator circuit (COMP701).

4. The circuit according to claim 3, wherein The second comparator circuit (COMP701) is more accurate than the first comparator (101-Comp; 302; 500).

5. The circuit according to claim 1, comprising a logic circuit (301; 400) configured as a main control circuit of the zero current detection circuit (101; 300). 6 . A DC-DC converter comprising the zero current detection circuit according to claim 1 .

7. The converter according to claim 6, comprising two switches (S101, S102) coupled in series; and a coil (L101) having one of its terminals coupled to an intermediate node between the two switches (S101, S102).

8. The converter according to claim 7, wherein The zero current detection circuit is configured to detect when the current in the coil is equal to zero.

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