Semiconductor optical element and method for manufacturing semiconductor optical element

Abstract

The invention provides a semiconductor optical element and a manufacturing method of the semiconductor optical element, which can inhibit undesired etching and inhibit light loss. This semiconductor optical element is provided with: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a first waveguide, a first recessed portion, a land, and a first slat portion, the first recessed portion being a portion recessed from a surface of the first waveguide, the land, and the first slat portion, and the first slat portion being a portion recessed from a surface of the first waveguide, the land, and the first slat portion. The first recessed portion and the platform are arranged in this order on both sides of the first waveguide, the first waveguide is connected to one end of the first lath portion, the first lath portion is connected to the platform, and the semiconductor element has a second lath portion, a protruding portion, and a mesa. The second batten portion is located above the first batten portion, the protruding portion protrudes from the second batten portion to a position above the first waveguide, and the mesa is located above the second batten portion and the protruding portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor optical element and a method for manufacturing the semiconductor optical element. Background Art

[0002] A hybrid semiconductor optical element can be formed by bonding a semiconductor element made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) with a waveguide formed thereon (e.g., Non-Patent Document 1). After bonding, the semiconductor element is etched, etc., allowing light to migrate between the silicon waveguide and the semiconductor element.

[0003] Prior art literature Non-patent literature Non-Patent Literature 1: D. Huang, et al. “High-power sub-kHz linewidth lasers fully integrated on silicon” Optica Vol.6, No.6 745-752 (June 2019) Summary of the Invention Problems to be solved by the invention Grooves (grooves) are provided in the substrate. Etchant may enter the grooves, etching the semiconductor element from the bonding interface. To prevent damage to the semiconductor element, it is necessary to suppress unwanted etching. To reduce light loss, it is necessary to improve the coupling efficiency between the waveguide and the semiconductor element. Therefore, an object of the present invention is to provide a semiconductor optical element and a method for manufacturing a semiconductor optical element that can suppress unwanted etching and light loss.

[0004] Means used to solve problems A semiconductor optical element according to the present invention comprises: a substrate having a silicon layer; and a semiconductor element formed of a Group III-V compound semiconductor and bonded to the silicon layer; the silicon layer having a first waveguide, a first recess, a terrace, and a first slab portion; the first recess being a portion recessed relative to the surfaces of the first waveguide, the terrace, and the first slab portion; the first recess and the terrace being sequentially arranged on either side of the first waveguide; the first waveguide being connected to one end of the first slab portion; the first slab portion being connected to the terrace; the semiconductor element having a second slab portion, a protrusion, and a terrace; the second slab portion being located above the first slab portion; the protrusion protruding from the second slab portion above the first waveguide; and the terrace being located above the second slab portion and the protrusion.

[0005] Effects of the Invention According to the present invention, it is possible to provide a semiconductor optical element and a method for manufacturing the semiconductor optical element that can suppress unintended etching and light loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a plan view illustrating a semiconductor optical element according to an embodiment.

[0007] Figure 2A This is an enlarged top view of the area near the migration structure.

[0008] Figure 2B FIG. 1 is a top view illustrating an example of a substrate.

[0009] Figure 3A is a cross-sectional view illustrating a semiconductor optical element.

[0010] Figure 3B is a cross-sectional view illustrating a semiconductor optical element.

[0011] Figure 3C is a cross-sectional view illustrating a semiconductor optical element.

[0012] Figure 4A is a cross-sectional view illustrating a semiconductor optical element.

[0013] Figure 4B is a cross-sectional view illustrating a semiconductor optical element.

[0014] Figure 4C is a cross-sectional view illustrating a semiconductor optical element.

[0015] Figure 5A It is a diagram showing an example of the calculation results of the transmittance.

[0016] Figure 5B It is a diagram showing an example of the calculation results of the transmittance.

[0017] Figure 6 It is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0018] Figure 7A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0019] Figure 7B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0020] Figure 7C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0021] Figure 8A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0022] Figure 8B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0023] Figure 8C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0024] Figure 9 It is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0025] Figure 10A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0026] Figure 10B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0027] Figure 10C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0028] Figure 11A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0029] Figure 11B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0030] Figure 11C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0031] Figure 12 It is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0032] Figure 13A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0033] Figure 13B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0034] Figure 13C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0035] Figure 14A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0036] Figure 14B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0037] Figure 14C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0038] Figure 15 It is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0039] Figure 16A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0040] Figure 16B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0041] Figure 16C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0042] Figure 17A It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0043] Figure 17B It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0044] Figure 17C It is a cross-sectional view illustrating a method for manufacturing a semiconductor optical element.

[0045] Figure 18 It is a plan view illustrating a semiconductor optical element according to a comparative example.

[0046] Figure 19A is a cross-sectional view illustrating a semiconductor optical element.

[0047] Figure 19B is a cross-sectional view illustrating a semiconductor optical element.

[0048] Figure 19C is a cross-sectional view illustrating a semiconductor optical element.

[0049] Figure 20A FIG. 1 is a plan view illustrating a semiconductor optical element according to a modified example.

[0050] Figure 20B FIG. 1 is a top view illustrating an example of a substrate.

[0051] Description of Reference Numerals 10, 12, 60: substrate; 11: insulating film; 14: buried oxide layer; 16: silicon layer; 20, 22: waveguide; 21, 23, 31, 34, 38: cone; 24, 26: recess; 25, 29, 36, 37: portion; 27: platform; 28, 32, 39: slab portion; 30: semiconductor element; 33: protrusion; 35: table; 40, 44: cladding layer; 42: active layer; 46: contact layer; 48, 49: electrode; 50, 52, 54: mask; 100, 110: semiconductor optical element; 101, 102: migration structure; 103: ring resonator; 104: loop mirror. DETAILED DESCRIPTION

[0052] [Description of Embodiments of the Invention] First, the contents of the embodiments of the present invention will be listed and described.

[0053] One embodiment of the present invention is (1) a semiconductor optical element, wherein the semiconductor optical element comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a first waveguide, a first recess, a terrace, and a first slab portion, the first recess being a portion recessed relative to the surface of the first waveguide, the terrace, and the first slab portion, the first recess and the terrace being sequentially arranged on both sides of the first waveguide, the first waveguide being connected to one end of the first slab portion, the first slab portion being connected to the terrace, the semiconductor element having a second slab portion, a protrusion, and a terrace, the second slab portion being located above the first slab portion, the protrusion protruding from the second slab portion above the first waveguide, and the terrace being located above the second slab portion and the protrusion. The first slab portion is connected to the terrace, and the first recess terminates near the end of the first slab portion. Since the first recess terminates near the semiconductor element, unwanted etching of the semiconductor element can be suppressed. Since light is confined near the terrace of the semiconductor element, light loss can be suppressed.

[0054] (2) Alternatively, in addition to the above (1), the silicon layer may include a second waveguide and a second recess, the second waveguide being connected to the end of the first slat portion opposite to the first waveguide, the second recess and the terrace being sequentially arranged on either side of the second waveguide, the first slat portion being located between the first recess and the second recess, the second slat portion being located above the first slat portion, the second waveguide, the second recess, and the terraces on either side of the second waveguide, the terraces extending from a position overlapping the first waveguide to a position overlapping the second waveguide. Since the second recess is closed by the first and second slat portions, intrusion of an etchant into the second recess can be suppressed.

[0055] (3) Alternatively, in addition to the above (1) or (2), the semiconductor element may include a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in order from the side closest to the substrate, the protrusion includes the first semiconductor layer, the second stripe includes the first semiconductor layer and the active layer, the portion of the mesa located above the protrusion includes the active layer and the second semiconductor layer, and the portion of the mesa located above the second stripe includes the second semiconductor layer. Since light is confined near the mesa of the semiconductor element, light loss can be suppressed.

[0056] (4) In the above (3), the first semiconductor layer and the second semiconductor layer may include indium phosphide, and the active layer may include gallium indium arsenide phosphide. The semiconductor element may be processed by wet etching. Entry of the etchant into the second recess may be suppressed. Undesirable etching of the semiconductor element may be suppressed.

[0057] (5) Alternatively, based on the above (3) or (4), the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer, forming a pin structure capable of injecting current into the active layer.

[0058] (6) In any one of (1) to (5) above, the protrusion may be located inward of the first waveguide, and the mesa may be located inward of the protrusion. Etching of the semiconductor element from the bonding interface can be suppressed. The protrusion and the mesa can be easily manufactured.

[0059] (7) In any one of (1) to (6) above, the first waveguide may include a first tapered portion, the protruding portion may include a second tapered portion, and the mesa may include a third tapered portion, wherein the widths of the first tapered portion, the second tapered portion, and the third tapered portion increase as they are closer to the first slat portion and decrease as they are farther away from the first slat portion. This improves the coupling efficiency between the substrate and the semiconductor element, thereby suppressing light loss.

[0060] (8) In the above (7), the second tapered portion may be joined to the first tapered portion, and the third tapered portion may be located above the second tapered portion. This improves the coupling efficiency between the substrate and the semiconductor element, thereby suppressing light loss.

[0061] (9) In any one of (1) to (8) above, the semiconductor optical element may include an insulating film covering the silicon layer and the semiconductor element. The insulating film functions as a cladding layer and can suppress light loss.

[0062] (10) A method for manufacturing a semiconductor optical element, wherein the method comprises: a step of bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate; and a step of wet etching the bonded semiconductor element, wherein the silicon layer has a first waveguide, a first recess, a terrace, and a first slat portion, wherein the first recess is a portion recessed relative to the surface of the first waveguide, the terrace, and the first slat portion, wherein the first recess and the terrace are sequentially arranged on both sides of the first waveguide, wherein the first waveguide is connected to one end of the first slat portion, and the first slat portion is connected to the terrace, wherein the step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slat portion, and the terrace on both sides of the first waveguide, wherein during the wet etching step, a second slat portion, a protrusion, and a terrace are formed on the semiconductor element, wherein the second slat portion is located above the first slat portion, the protrusion protrudes from the second slat portion to above the first waveguide, and the terrace is located above the second slat portion and the protrusion. Undesirable etching of the semiconductor element can be suppressed. Since light is confined near the mesa of the semiconductor element, light loss can be suppressed.

[0063] (11) Alternatively, in the above (10), the silicon layer may include a second waveguide and a second recess, the second waveguide being connected to the end of the first slat portion opposite to the first waveguide, the second recess and the terrace being sequentially arranged on both sides of the second waveguide, the first slat portion being located between the first recess and the second recess, the bonding step being a step of bonding the semiconductor element to the first waveguide, the first slat portion, the second waveguide, and the terraces on both sides of the first waveguide, the terraces extending from a position overlapping the first waveguide to a position overlapping the second waveguide. Since the second recess is closed by the first slat portion and the second slat portion, intrusion of an etchant into the second recess can be suppressed.

[0064] [Details of the embodiments of the present invention] Hereinafter, specific examples of semiconductor optical devices and methods for manufacturing semiconductor optical devices according to embodiments of the present invention will be described with reference to the accompanying drawings. The present invention is not limited to these examples, but is intended to encompass all modifications within the meaning and scope of the claims, which are equivalent to the claims.

[0065] <Implementation Method> (Semiconductor Optical Components) Figure 1FIG1 is a top view illustrating a semiconductor optical element 100 according to an embodiment. Semiconductor optical element 100 is a hybrid-type wavelength-tunable laser element comprising a substrate 10 and a semiconductor element 30. Semiconductor element 30 provides optical gain and is bonded to one surface of substrate 10. The Z-axis is the normal to the top surface of substrate 10. The X-axis is parallel to the waveguide. A direction along the X-axis is designated as the +X direction. The direction opposite to the +X direction is designated as the -X direction. The Y-axis is orthogonal to the X- and Z-axis directions.

[0066] The semiconductor optical element 100 includes a transition structure 101, a transition structure 102, two ring resonators 103, and two loop mirrors 104. In the X-axis direction, the loop mirrors 104, the ring resonators 103, the transition structure 102, the semiconductor element 30, the transition structure 101, the ring resonators 103, and the loop mirrors 104 are arranged in this order. These components form a laser resonator.

[0067] The ring resonator 103 and the loop mirror 104 are provided on the substrate 10 . The migration structure 101 and the migration structure 102 are portions for migrating light between the substrate 10 and the semiconductor element 30 , and are formed by the substrate 10 and the semiconductor element 30 .

[0068] Figure 2A It is an enlarged top view of the vicinity of the migration structure 101. Figure 2B is a top view showing an example of the substrate 10, from Figure 2A The semiconductor element 30 is removed. Figures 3A to 4C is a cross-sectional view showing an example of a semiconductor optical element 100, and Figure 2A The cross sections of line A1, line A2, line A3, line A4, line A5 and line A6. Figures 3A to 4C The dotted line in FIG. 4 shows the light distribution as an example.

[0069] like Figures 3A to 4C As shown, substrate 10 is an SOI (Silicon on Insulator) substrate and includes a substrate 12, a buried oxide layer 14, and a silicon (Si) layer 16 stacked sequentially in the Z-axis direction. Substrate 12 is formed, for example, of Si. Buried oxide layer 14 is formed, for example, of silicon oxide (SiO2). The thickness of buried oxide layer 14 is, for example, 3 μm. The thickness of silicon layer 16 is, for example, 220 nm. The upper surface of substrate 10 and the surface of semiconductor element 30 are covered by insulating film 11. Insulating film 11 is formed, for example, of SiO2 with a thickness of 1 μm. The refractive index of silicon layer 16 is 3.45. The refractive index of buried oxide layer 14 and insulating film 11 is lower than that of silicon layer 16, at 1.45. Functional components such as waveguides are provided in silicon layer 16 in substrate 10.

[0070] like Figure 2Aas well as Figure 2B As shown, the substrate 10 has a waveguide 20 (first waveguide), a waveguide 22 (second waveguide), a recess 24 (first recess), a recess 26 (second recess), a platform 27 , and a strip portion 28 (first strip portion).

[0071] The waveguide 20, slat portion 28, and waveguide 22 are arranged in this order from the +X side toward the -X side. The waveguide 20 is connected to one end of the slat portion 28 in the X-axis direction (the end on the +X side). The waveguide 22 is connected to the other end of the slat portion 28 (the end on the -X side). The waveguide 20 and waveguide 22 are parallel to the X-axis direction.

[0072] The waveguide 20 has a tapered portion 21 (first tapered portion). The waveguide 22 has a tapered portion 23. The widths of the tapered portion 21 and the tapered portion 23 increase as they are closer to the strip portion 28 and decrease as they are farther away from the strip portion 28. Figure 2B The width W1 of the front end of the waveguide 20 is shown to be 420 nm, for example. The dimensions of the waveguide 22 may be the same as or different from those of the waveguide 20. The dimensions of the recess 26 may be the same as or different from those of the recess 24.

[0073] In the Y-axis direction, recesses 24 and terraces 27 are sequentially provided on both sides of waveguide 20. That is, recesses 24 are arranged next to waveguide 20. Terraces 27 are arranged opposite recesses 24 from waveguide 20. Recesses 26 and terraces 27 are sequentially provided on both sides of waveguide 22. Recesses 24 extend along waveguide 20 and have a tapered shape corresponding to tapered portion 21 of waveguide 20. Recesses 26 extend along waveguide 22 and have a tapered shape corresponding to tapered portion 23 of waveguide 22.

[0074] The strip portion 28 is plate-shaped and is located between the recess 24 and the recess 26 and is connected to the two terraces 27 on both sides of the waveguide. The recess 24 and the recess 26 are separated by the strip portion 28.

[0075] like Figures 3A to 4A As shown, the waveguide 20 and the terrace 27 are portions of the silicon layer 16 that protrude further in the Z-axis direction (upward) than the recess 24. The surface of the waveguide 20 is located at the same height as the surface of the terrace 27. The recess 24 is a portion that is recessed relative to the surfaces of the waveguide 20 and the terrace 27. Figure 4C As shown, the surface of waveguide 22 is located at the same height as the surface of terrace 27. Recess 26 is a portion recessed relative to the surfaces of waveguide 22 and terrace 27. Silicon layer 16 forms the bottom surface of recess 24 and recess 26. The thickness of silicon layer 16 in the recess is, for example, 30 nm. Recess 24 and recess 26 may extend to the middle of silicon layer 16 in the Z-axis direction, or may extend through silicon layer 16 to the buried oxide layer 14. Insulating film 11 is embedded in recess 24 and recess 26.

[0076] like Figure 4B As shown, the surface of the strip portion 28 is located at the same height as the surface of the platform 27. The strip portion 28 is formed integrally with the platform 27, extends parallel to the XY plane, and forms the surface of the silicon layer 16.

[0077] like Figure 1 As shown, semiconductor element 30 includes a strip portion 32 (second strip portion), two protrusions 33, a mesa 35, an electrode 48, and an electrode 49. Protrusion 33, strip portion 32, and protrusion 33 are arranged in this order from the +X side to the -X side. Mesa 35 extends from one protrusion 33 to the other.

[0078] like Figure 2A as well as Figure 4B As shown, the strip portion 32 is joined to the strip portion 28 of the substrate 10. The strip portion 32 is plate-shaped and has a width greater than the protrusion 33 and the terrace 35. The planar shape of the strip portion 32 is rectangular. In the X-axis direction, the strip portion 32 does not protrude outward from the strip portion 28. The strip portion 28 extends outward from the strip portion 32 from the position where it overlaps with the strip portion 32. Figures 2A to 4A As shown, the protrusion 33 extends parallel to the X-axis, protrudes from the strip portion 32 to above the waveguide 20 , and is located above the tapered portion 21 of the waveguide 20 .

[0079] The protrusion 33 has a tapered portion 34 (second tapered portion). Figure 2A In the example, the entire protrusion 33 is a tapered portion 34. The width of the tapered portion 34 increases as it approaches the slat portion 32 and decreases as it moves away from the slat portion 32. The protrusion 33 has a width greater than that of the terrace 35. From the tip of the protrusion 33 toward the side closest to the slat portion 32, the widths of the protrusion 33 are denoted by W2, W3, W4, and W5. Width W2 is, for example, 1.7 μm. Width W3 is, for example, 2.7 μm. Width W4 is, for example, 3.7 μm. Width W5, the portion of the protrusion 33 connected to the slat portion 32, is, for example, 5.7 μm.

[0080] like Figure 2A As shown, the mesa 35 extends parallel to the X-axis, from a position overlapping with the waveguide 20 to a position overlapping with the waveguide 22. Figure 2A as well as Figures 3C to 4C As shown, the mesa 35 is located above the slat portion 32 and the protrusion 33. The mesa 35 has a portion 36 and a portion 37. The portion 36 protrudes out of the slat portion 32 and is located above the protrusion 33 and the waveguide 20. The portion 37 is located above the slat portion 32 and the waveguide 22.

[0081] like Figure 2AAs shown, portion 36 of mesa 35 has a tapered portion 38 (third tapered portion). Tapered portion 38 is located above protrusion 33. The width of tapered portion 38 increases as it approaches strip portion 28 and decreases as it moves away from strip portion 28. Width W6 at the front end of mesa 35 is, for example, 400 nm.

[0082] The tapered portion 31 of the semiconductor element 30 protrudes from the strip portion 32 in the X-axis direction, is located on both sides of the mesa 35 in the Y-axis direction, and is located between the strip portion 32 and the tapered portion 38 of the mesa 35 in the X-axis direction. The width W7 of the portion of the tapered portion 31 connected to the strip portion 32 is, for example, 3 μm.

[0083] The protrusion 33 and the mesa 35 do not protrude outward from the waveguide 20 in a plan view, but are located inside the waveguide 20. The waveguide 20 protrudes from below the protrusion 33 and the mesa 35 to the outside of the protrusion 33.

[0084] like Figures 3B to 4C As shown, the semiconductor element 30 includes a cladding layer 40 (first semiconductor layer), an active layer 42, a cladding layer 44, and a contact layer 46 (these two layers are second semiconductor layers). Figures 3B to 4A As shown, the protrusion 33 of the semiconductor element 30 is formed by the cladding layer 40 .

[0085] The mesa 35 includes an active layer 42, a cladding layer 44 and a contact layer 46. Figure 3C as well as Figure 4A As shown, the portion 36 of the mesa 35 includes an active layer 42, a cladding layer 44, and a contact layer 46, and has a deep ridge structure. Figure 4B as well as Figure 4C As shown, a portion 37 of the mesa 35 does not include the active layer 42 , but includes the cladding layer 44 and the contact layer 46 , and has a shallow ridge structure.

[0086] like Figure 4A As shown, the cone portion 31 is formed by the active layer 42. Figure 4B as well as Figure 4C As shown, the strip portion 32 includes a cladding layer 40 and an active layer 42 .

[0087] The insulating film 11 covers the substrate 10, the strip portion 32, the protrusion 33, and the mesa 35. The insulating film 11 has an opening above the mesa 35. The electrode 48 is a p-type electrode and is provided in the opening. The electrode 48 is in contact with the surface of the contact layer 46 and is electrically connected to the contact layer 46. The insulating film 11 also has an opening at a position separated from the mesa 35. Figure 1 The electrode 49 shown is an n-type electrode and is connected to the cladding layer 40 via the opening.

[0088] The cladding layer 40 is formed, for example, of n-type indium phosphide (n-InP). The active layer 42 has a quantum well structure (MQW: Multiple Quantum Well) and includes barrier layers and well layers. Multiple barrier layers and multiple well layers are alternately stacked. The barrier layers and well layers are formed, for example, of i-type gallium indium arsenide phosphide (GaInAsP). The cladding layer 44 is formed, for example, of p-type indium phosphide (p-InP). The contact layer 46 is formed, for example, of p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 30 may also be formed of Group III-V compound semiconductors other than those described above.

[0089] Electrodes 48 and 49 are formed of metal. Electrode 48 is formed, for example, of a stack of titanium (Ti), platinum (Pt), and gold (Au) stacked from the side closest to mesa 35. Electrode 49 is formed, for example, of an alloy of gold, germanium, and nickel (AuGeNi).

[0090] Migration structure 102 has the same configuration as migration structure 101. Waveguide 22, recess 26, and platform 27 extend from migration structure 101 to migration structure 102. Recess 26 is located between waveguide 22 and platform 27. Slat portion 32 of semiconductor element 30 extends from migration structure 101 to migration structure 102 and is located above recess 26, platform 27, and waveguide 22. Recess 26 is sealed by slat portion 28 and slat portion 32.

[0091] A voltage is applied to the semiconductor element 30 using electrodes 48 and 49 to inject carriers into the active layer 42. The active layer 42 has optical gain and generates light by carrier injection. The wavelength of the light is, for example, 1.55 μm. The semiconductor element 30 and the substrate 10 are evanescently coupled. The light generated by the semiconductor element 30 propagates in the waveguide 22 and is transferred to the waveguide 20 in the migration structure 101 and the migration structure 102. The light resonates in the ring resonator 103 and is reflected by the loop mirror 104. The reflected light propagates toward the semiconductor element 30 and is transferred from the waveguide 20 to the waveguide 22 in the migration structure 101 and the migration structure 102. The light oscillates as a laser by repeated reflection.

[0092] The diameter of one of the two ring resonators 103 is different from the diameter of the other ring resonator. The oscillation wavelength is determined by the Vernier effect of the two ring resonators 103. The transmittance of one of the two loop mirrors 104 is higher than the transmittance of the other loop mirror. A portion of the laser light passes through the loop mirror 104 and is emitted from the semiconductor optical element 100.

[0093] exist Figures 3A to 4C In FIG, the shape of light is schematically illustrated by a dotted ellipse. The light mode is defined by the waveguide and the mesa 35. Figure 3AIn the cross-section, light is concentrated in waveguide 20. In the migration structure 101, light is transferred from waveguide 20 to semiconductor element 30. Because the protrusion 33 and mesa 35 of semiconductor element 30 have tapered shapes, the light is gradually transferred, and the light mode is smoothly converted. Light is confined near mesa 35 of semiconductor element 30, making it difficult to spread. Consequently, the light mode is maintained, minimizing light loss.

[0094] Figure 5A as well as Figure 5B It is a diagram showing an example of the calculation results of the transmittance. Figure 5A The figure shows the calculation results of the transmittance of the protrusion 33. The horizontal axis represents the length of the tapered portion 34 of the protrusion 33. The vertical axis represents the transmittance of light. When the tapered portion 34 is 5 μm or larger, the transmittance exceeds 0.9.

[0095] Figure 5B The results of calculations for the transmittance of the tapered portion 38 of the mesa 35 are shown. The horizontal axis represents the length of the tapered portion 38. The vertical axis represents the transmittance of light. The longer the tapered portion 38, the higher the transmittance. The transmittance exceeds 0.9 for a length of 15 μm or greater. As described above, the tapered protrusion 33 and the mesa 35 can suppress light loss.

[0096] (Manufacturing Method) Figure 6 、 Figure 9 、 Figure 12 as well as Figure 15 1 is a plan view illustrating a method for manufacturing the semiconductor optical element 100 . 7A to 8C is a cross-sectional view illustrating a method of manufacturing a semiconductor optical element 100, and illustrates a method of manufacturing a semiconductor optical element 100 along the Figure 6 A cross section from line A1 to line A6. Figures 10A to 11C is a cross-sectional view illustrating a method of manufacturing a semiconductor optical element 100, and illustrates a method of manufacturing a semiconductor optical element 100 along the Figure 9 A cross section from line A1 to line A6. 13A to 14C is a cross-sectional view illustrating a method of manufacturing a semiconductor optical element 100, and illustrates a method of manufacturing a semiconductor optical element 100 along the Figure 12 A cross section from line A1 to line A6. 16A to 17C is a cross-sectional view illustrating a method of manufacturing a semiconductor optical element 100, and illustrates a method of manufacturing a semiconductor optical element 100 along the Figure 15 A cross section from line A1 to line A6.

[0097] exist Figure 6 In the previous step, silicon layer 16 of substrate 10 is dry-etched, for example. Portions exposed by a mask (not shown) are etched, forming recesses 24 and 26. Portions covered by a mask (not shown) remain unetched. Waveguides 20 and 22, terraces 27, and slats 28 are formed.

[0098] On an InP substrate, different from the SOI substrate (substrate 10), a contact layer 46, a cladding layer 44, an active layer 42, and a cladding layer 40 are epitaxially grown in this order by methods such as metal organic chemical vapor deposition (MOCVD). The InP substrate is then diced to form the semiconductor element 30. Immediately after dicing, the semiconductor element 30 is a rectangular parallelepiped and lacks the slat portion 32, the protrusion 33, or the mesa 35.

[0099] like Figures 6 to 8C As shown, a semiconductor element 30 is bonded to the upper surface of substrate 10. Plasma is irradiated onto one surface of silicon layer 16 and one surface of semiconductor element 30 to activate these surfaces. The surface of semiconductor element 30 is brought into contact with the surface of silicon layer 16, thereby bonding semiconductor element 30 to silicon layer 16. For example, semiconductor element 30 covers the upper surface of silicon layer 16 and is positioned above waveguides 20 and 22, recesses 24 and 26, terraces 27, and strips 28. After bonding, wet etching is performed to remove the InP substrate. Semiconductor layers from contact layer 46 to cladding layer 40 remain.

[0100] like Figures 9 to 11C As shown, a portion of the semiconductor element 30 is covered with a mask 50. For example, dry etching and wet etching are performed on the semiconductor element 30 to form a mesa 35. For example, a hydrochloric acid-based solution is used as an etchant for the wet etching. The portion of the semiconductor element 30 covered by the mask 50 is not etched, forming the mesa 35. The mesa 35 is formed by the cladding layer 44 and the contact layer 46. In the portion exposed from the mask 50, the contact layer 46 and the cladding layer 44 are etched, exposing the active layer 42. The cladding layer 40 and the active layer 42 cover the waveguides 20 and 22, the recesses 24 and 26, the terraces 27, and the slats 28 of the silicon layer 16. After etching, the mask 50 is removed.

[0101] like Figures 12 to 14C As shown in FIG. 5 , a mask 52 is provided on the semiconductor element 30. Figures 13C to 14C As shown, the mask 52 covers the upper surface and side surfaces of the mesa 35 and covers a portion of the active layer 42. Another portion of the active layer 42 is exposed from the mask 52. For example, wet etching is performed to remove the portion of the active layer 42 exposed from the mask 52. 13A to 13C As shown, the cladding layer 40 is exposed in the wet-etched portion. The portion covered by the mask 52 is not etched, and the mesa 35, the active layer 42, and the cladding layer 40 remain.

[0102] like Figure 13C as well as Figure 14A As shown, the portion 36 in the mesa 35 contains the active layer 42 and is a deep ridge structure. Figure 14AAs shown in FIG. 3 , a portion of the cladding layer 40 that protrudes in the Y-axis direction from the terrace 35 is formed as a tapered portion 31. Figure 14B as well as Figure 14C As shown, portion 37 of mesa 35 includes cladding layer 44 and contact layer 46, having a shallow ridge structure. Active layer 42 and cladding layer 40 form slab portion 32. After etching, mask 52 is removed.

[0103] like Figures 15 to 17C As shown in FIG. 5 , a mask 54 is provided on the semiconductor element 30. Figures 16C to 17C As shown, the mask 54 covers the upper surface and side surfaces of the mesa 35. Figure 17B as well as Figure 17C As shown, the mask 54 covers the strip portion 32. Figure 16B As shown, mask 54 covers the portion of cladding layer 40 above waveguide 20. A portion of cladding layer 40 is exposed from mask 54. For example, wet etching is performed to remove the portion of cladding layer 40 exposed from mask 54, thereby forming protrusion 33. By removing cladding layer 40 through wet etching, silicon layer 16 is exposed. After etching, mask 54 is removed.

[0104] By plasma CVD method (PECVD, Plasma Enhanced Chamical Vapor Deposition), etc. Figures 3A to 4C Insulating film 11 is formed in this manner. Openings are formed in portions of insulating film 11 that are located on mesas 35. Electrodes 48 and 49 are formed in the openings by vacuum deposition or the like. Semiconductor optical element 100 is formed through the above steps.

[0105] As described above, after bonding, semiconductor element 30 is wet-etched. During the wet etching process, insulating film 11 is not formed, and recess 24 is exposed. During the wet etching process, etchant enters recess 24. Since stripe 28 is provided between recess 24 and recess 26, the etchant is blocked by stripe 28, suppressing its entry into recess 26. Consequently, etching of semiconductor element 30 is suppressed from the bonding interface.

[0106] (Comparative Example) Figure 18 FIG. 1 is a plan view illustrating a semiconductor optical element 110 according to a comparative example. 19A to 19C is a cross-sectional view showing an example of a semiconductor optical element 110, and illustrating the Figure 18 The description of the same configuration as that of the embodiment will be omitted.

[0107] like Figures 18 to 19CAs shown, substrate 10 has a waveguide 20, a recess 24, and a platform 27, but no slats. Waveguide 20, recess 24, and platform 27 extend from one end of substrate 10 to the other in the X-axis direction. Waveguide 20 has a tapered portion 21, a portion 29, and a portion 25. In the X-axis direction, portion 29, tapered portion 21, portion 25, tapered portion 21, and portion 29 are arranged in this order. Portion 25 is wider than portion 29. Tapered portion 21 connects portion 29 and portion 25.

[0108] The semiconductor element 30 includes a strip portion 39 and a protrusion 33. The protrusion 33 protrudes from the strip portion 39 in the X-axis direction and is located above the portion 25 of the waveguide 20. The strip portion 39 is located above the waveguide 20, the recess 24, and the terrace 27.

[0109] The recesses 24 are located on both sides of the waveguide 20, extending from outside the semiconductor element 30 to below the semiconductor element 30. During the wet etching process of the semiconductor element 30, liquid such as an etchant enters the recesses 24 and flows under the semiconductor element 30. The semiconductor element 30 is etched from the bottom surface (bonding interface), causing damage to the semiconductor element 30. This reduces the bond strength between the semiconductor element 30 and the substrate 10.

[0110] According to this embodiment, the silicon layer 16 of the substrate 10 includes waveguides 20 and 22, recesses 24 and 26, and a strip portion 28. Strip portion 28 is located between recesses 24 and 26, dividing the gap between recesses 24 and 26. Recess 24 terminates just before semiconductor element 30 and is not connected to recess 26. Semiconductor element 30 is bonded to the silicon layer 16 and includes a strip portion 32. Strip portion 32 is located above strip portion 28, waveguide 22, recess 26, and terrace 27. Recess 26 is sealed by strip portions 28 and 32. Liquids such as etchants are less likely to enter recess 26. Undesirable etching of semiconductor element 30 can be suppressed.

[0111] Semiconductor element 30 is formed from a Group III-V compound semiconductor. After bonding, wet etching is performed to form strip portions 32, protrusions 33, and mesas 35. Semiconductor element 30 includes an InP cladding layer, an InGaAsP active layer 42, and an InGaAs contact layer 46. During wet etching, an etchant suitable for these semiconductors is used. For example, a hydrochloric acid-based solution is used as the etchant. Strip portions 28 and 32 suppress the intrusion of the etchant into recesses 26, thereby preventing undesirable etching of semiconductor element 30.

[0112] The substrate 10 and the semiconductor element 30 form a migration structure 101 and a migration structure 102. Figure 2AAs shown, semiconductor element 30 has a protrusion 33 and a mesa 35. Protrusion 33 is located above waveguide 20. Mesa 35 is located above protrusion 33 and slat portion 32. In the migration structure, light is transferred between substrate 10 and semiconductor element 30. Light propagates in the waveguide and is confined near mesa 35. This can suppress light loss.

[0113] Semiconductor element 30 includes a cladding layer 40, an active layer 42, a cladding layer 44, and a contact layer 46. Slat portion 32 includes cladding layer 40 and active layer 42. Protrusion 33 includes cladding layer 40. Portion 36 of mesa 35, located above protrusion 33, includes active layer 42, cladding layer 44, and contact layer 46. This improves the coupling efficiency between semiconductor element 30 and substrate 10 and allows for smooth light migration. Portion 37 of mesa 35, located above slat portion 32, includes cladding layer 44 and contact layer 46. Light is confined near mesa 35, thus minimizing light loss.

[0114] The cladding layer 40 is formed of n-type InP. The cladding layer 44 is formed of p-type InP. The contact layer 46 is formed of p-type InGaAs. The active layer 42 is formed of undoped GaInAsP. A pin junction is formed in the semiconductor element 30. Injecting carriers into the active layer 42 generates light. This light is concentrated near the mesa 35 of the semiconductor element 30, thus suppressing losses.

[0115] like Figure 2A As shown, the waveguide 20 protrudes beyond the protrusion 33 and the mesa 35. The protrusion 33 and the mesa 35 do not protrude but are located inward of the waveguide 20. This prevents etching of the semiconductor element 30 from the bonding interface. The mesa 35 is located inward of the protrusion 33. Etching facilitates the production of the protrusion 33 and the mesa 35. After forming the mesa 35, the protrusion 33 can be formed below the mesa 35.

[0116] The waveguide 20 has a tapered portion 21. The protrusion 33 has a tapered portion 34. The mesa 35 has a tapered portion 38. The coupling efficiency between the semiconductor element 30 and the substrate 10 can be improved, and light loss can be suppressed.

[0117] The tapered portion 34 of the protrusion 33 is joined to the tapered portion 21 of the waveguide 20. The tapered portion 38 of the mesa 35 is located above the tapered portion 34 of the protrusion 33. The multi-stage tapered structure can improve the coupling efficiency between the semiconductor element 30 and the substrate 10.

[0118] The insulating film 11 covers the silicon layer 16 of the substrate 10 and the semiconductor element 30. Since the insulating film 11 functions as a cladding layer, it is possible to suppress light loss.

[0119] Figure 1The semiconductor optical element 100 is a wavelength tunable laser element. The semiconductor optical element 100 may be an optical device different from the wavelength tunable laser element.

[0120] (Variation) Figure 20A is a top view showing a semiconductor optical element according to a modification example, and Figure 2A A migration structure 101 is also illustrated. Figure 20B FIG. 6 is a top view showing an example of a substrate 60. The description of the same structure as that in the embodiment is omitted. Figure 20A as well as Figure 20B As shown, substrate 60 includes waveguide 20, recess 24, platform 27, and slat portion 28. Waveguide 20 is connected to one end of slat portion 28. Slat portion 28 extends from one migration structure 101 to another migration structure 102. In the X-axis direction, no waveguide or recess is provided between migration structure 101 and migration structure 102. Slat portion 32 of semiconductor element 30 is bonded to slat portion 28.

[0121] According to the modified example, since the strip portion 28 is provided, the recess 24 ends near the end of the semiconductor element 30. This makes it difficult for liquid such as an etchant to enter under the semiconductor element 30. Unintended etching of the semiconductor element 30 can be suppressed.

[0122] While the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor optical element, wherein: The semiconductor optical element comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer; The silicon layer has a first waveguide, a first recess, a platform, and a first slab portion. The first recessed portion is a portion recessed relative to the surfaces of the first waveguide, the platform, and the first slat portion. The first concave portion and the platform are sequentially arranged on both sides of the first waveguide. The first waveguide is connected to one end of the first slat portion. The first slat portion is connected to the platform, The semiconductor element has a second strip portion, a protrusion, and a mesa. The second strip portion is located above the first strip portion, The protrusion protrudes from the second slat portion to above the first waveguide, The table top is located above the second slat portion and the protruding portion.

2. The semiconductor optical element according to claim 1, wherein The silicon layer has a second waveguide and a second recess, The second waveguide is connected to the end of the first slat portion opposite to the first waveguide. The second concave portion and the platform are sequentially arranged on both sides of the second waveguide. The first strip portion is located between the first recess and the second recess, The second slat portion is located above the first slat portion, the second waveguide, the second recess, and the platform on both sides of the second waveguide. The mesa extends from a position overlapping with the first waveguide to a position overlapping with the second waveguide.

3. The semiconductor optical element according to claim 1 or 2, wherein The semiconductor element comprises a first semiconductor layer, an active layer and a second semiconductor layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked in order from the side closer to the substrate, The protrusion includes the first semiconductor layer, The second slab portion includes the first semiconductor layer and the active layer, A portion of the mesa located above the protrusion includes the active layer and the second semiconductor layer. A portion of the mesa located above the second strip portion includes the second semiconductor layer. The semiconductor optical element according to claim 3 , wherein: The first semiconductor layer and the second semiconductor layer include indium phosphide, The active layer includes gallium indium arsenic phosphide. The semiconductor optical element according to claim 3 , wherein The first semiconductor layer is an n-type semiconductor layer, The second semiconductor layer is a p-type semiconductor layer. The semiconductor optical element according to claim 1 or 2, wherein The protrusion is located inside the first waveguide. The table surface is located inside the protruding portion.

7. The semiconductor optical element according to claim 1 or 2, wherein The first waveguide has a first tapered portion, The protrusion has a second tapered portion, The table has a third tapered portion, The width of the first tapered portion, the width of the second tapered portion, and the width of the third tapered portion increase as they are closer to the first strip portion and decrease as they are farther away from the first strip portion. The semiconductor optical element according to claim 7 , wherein: The second cone portion is engaged with the first cone portion, The third tapered portion is located above the second tapered portion.

9. The semiconductor optical element according to claim 1 or 2, wherein The semiconductor optical element includes an insulating film covering the silicon layer and the semiconductor element.

10. A method for manufacturing a semiconductor optical element, wherein: The method for manufacturing the semiconductor optical element comprises: A step of bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate; as well as a step of wet etching the bonded semiconductor element; The silicon layer has a first waveguide, a first recess, a platform, and a first slab portion. The first recessed portion is a portion recessed relative to the surfaces of the first waveguide, the platform, and the first slat portion. The first concave portion and the platform are sequentially arranged on both sides of the first waveguide. The first waveguide is connected to one end of the first slat portion. The first slat portion is connected to the platform, The step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slab portion, and the platforms on both sides of the first waveguide. In the wet etching step, a second strip portion, a protrusion, and a mesa are formed on the semiconductor element. The second strip portion is located above the first strip portion, The protrusion protrudes from the second slat portion to above the first waveguide, The table top is located above the second slat portion and the protruding portion.

11. The method for manufacturing a semiconductor optical element according to claim 10, wherein: The silicon layer has a second waveguide and a second recess, The second waveguide is connected to the end of the first slat portion opposite to the first waveguide. The second concave portion and the platform are sequentially arranged on both sides of the second waveguide. The first strip portion is located between the first recess and the second recess, The bonding step is a step of bonding the semiconductor element to the first waveguide, the first slab portion, the second waveguide, and the platforms on both sides of the first waveguide and the second waveguide. The mesa extends from a position overlapping with the first waveguide to a position overlapping with the second waveguide.

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