System and method for operating PFC circuit in discontinuous / critical conduction mode

Abstract

The invention relates to a system and method for operating a PFC circuit in a discontinuous / critical conduction mode. A method of operating a PFC circuit includes: receiving an input voltage at an input terminal; current in an inductor is controlled by a first switch having a drain terminal, a source terminal and a gate terminal, where the inductor is coupled between the input terminal and the drain terminal, and where: during an on time of the first switch, the current in the inductor rises from substantially zero to a peak value; during a first off time of the first switch, the current in the inductor decreases from the peak to substantially zero; and during a second off time of the first switch, the current in the inductor is substantially zero; generating a first reference voltage inversely proportional to a sum of the on time and the first off time of the first switch; and controlling the turn-on time of the first switch in response to the first reference voltage.

Description

[0001] Cross-reference to other applications

[0002] This application claims priority to U.S. patent application serial number 18 / 437,182, filed on February 8, 2024, entitled “System and Method for Operating a PFC Circuit in Discontinuous / Critical Conduction Mode,” which is incorporated by reference in its entirety into this application for all purposes. Technical Field

[0003] The present disclosure relates to power factor correction (PFC) circuits, and more particularly to PFC circuits operating in discontinuous / critical conduction mode. Background Art

[0004] A power supply can be used to convert alternating current ("ac") power provided by an electrical outlet into direct current ("dc") power that can be used by electrical devices. An important consideration in power supply design is how to efficiently deliver power to the power supply. To improve power delivery efficiency, a power factor correction (PFC) circuit can be used in the power supply. The circuit attempts to shape the current waveform to be as close as possible to the shape of the voltage waveform.

[0005] Typically, a PFC circuit is designed to include a power switch that is controlled to switch between an off state and an on state to convert the distorted input current waveform transmitted from the power distribution line into a more ideal current waveform similar in shape to the input voltage waveform. More specifically, the power switch may be coupled to an energy transfer element to transfer energy to the output of the power supply. However, PFC circuits may experience switching losses during operation. Additional losses may also be realized in the energy transfer element.

[0006] The boost topology can be used for PFC because the input current is the inductor current. To have a good power factor, the input current can be made proportional to the input voltage and follow the shape of the input mains voltage. Summary of the Invention

[0007] In some embodiments, a method of operating a power factor correction (PFC) circuit is disclosed. The method includes receiving an input voltage at an input terminal; controlling a current in an inductor via a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: during an on-time of the first switch, the current in the inductor increases from substantially zero to a peak value; during a first off-time of the first switch, the current in the inductor decreases from the peak value to substantially zero; and during a second off-time of the first switch, the current in the inductor is substantially zero; generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time, the first off-time, and the second off-time to a sum of the on-time and the first off-time.

[0008] In some embodiments, generating the first reference voltage includes: generating a first voltage that is proportional to the sum of the on-time and the first off-time of the first switch; generating a second voltage by comparing the input voltage with a second reference voltage; and generating the first reference voltage by setting the first voltage equal to the second voltage.

[0009] In some embodiments, generating the first voltage includes: generating a current signal corresponding to the first reference voltage; and transmitting the current signal to a second switch, the second switch being arranged to switch with a switching cycle proportional to the sum of the on-time and the first off-time of the first switch.

[0010] In some embodiments, generating the first voltage further includes: generating a voltage signal corresponding to the first reference voltage; and transmitting the voltage signal to a first capacitor coupled to the second switch.

[0011] In some embodiments, controlling the on-time of the first switch includes: generating a sawtooth wave signal; and comparing the sawtooth wave signal with the first reference voltage to generate a control signal for the first switch.

[0012] In some embodiments, generating the second voltage includes: generating an inverse ratio of the square of the input voltage; and multiplying the inverse ratio of the square of the input voltage by a third voltage corresponding to the input voltage.

[0013] In some embodiments, a method of operating a power factor correction (PFC) circuit is disclosed. The method includes receiving an input voltage at an input terminal; controlling a current in an inductor via a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: during an on-time of the first switch, the inductor is charged with a certain amount of energy; during a first off-time of the first switch, the certain amount of energy is discharged from the inductor; and during a second off-time of the first switch, the inductor remains discharged; generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time, the first off-time, and the second off-time to a sum of the on-time and the first off-time.

[0014] In some embodiments, the current signal is a first current signal, wherein generating the first current signal includes: generating a second current signal corresponding to the first reference voltage through a transconductance amplifier; and generating the first current signal corresponding to the second current signal through a current mirror.

[0015] In some embodiments, a method of operating a power factor correction (PFC) circuit is disclosed. The method includes receiving an input voltage at an input terminal; controlling a current in an inductor via a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: during an on-time of the first switch, the inductor is charged to a first energy state; during a first off-time of the first switch, the inductor is discharged to a second energy state; and during a second off-time of the first switch, the inductor remains in the second energy state; generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time, the first off-time, and the second off-time to a sum of the on-time and the first off-time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram illustrating an example of a power factor correction system according to some embodiments of the present disclosure;

[0017] Figure 2 Shown Figure 1A schematic diagram of an example of a compensation circuit;

[0018] Figure 3 Shown Figure 1 A schematic diagram of an example of a multiplier circuit in FIG.

[0019] Figure 4 shows the inductor current in the boost converter;

[0020] Figure 5 A schematic diagram illustrating an example of a power factor correction circuit according to some embodiments of the present disclosure;

[0021] Figure 6 A schematic diagram illustrating an example of a power factor correction circuit according to some embodiments of the present disclosure; and

[0022] Figure 7 A schematic diagram illustrating an example of a power factor correction circuit according to certain embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The circuits and related techniques disclosed herein generally relate to power converters. More specifically, the circuits, devices, and related techniques disclosed herein relate to power factor correction (PFC) circuits that operate in a discontinuous / critical conduction mode and can operate with improved efficiency by employing the circuits and techniques disclosed herein. In some embodiments, a method of operating a PFC circuit may include: receiving an input voltage at an input terminal; controlling a current in an inductor via a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: during an on-time of the first switch, the current in the inductor rises from substantially zero to a peak value; during a first off-time of the first switch, the current in the inductor decreases from the peak value to substantially zero; and during a second off-time of the first switch, the current in the inductor is substantially zero. The method further includes generating a first reference voltage that is inversely proportional to the sum of the on-time and the first off-time of the first switch; and controlling the on-time of the first switch in response to the first reference voltage so that the on-time is proportional to a ratio of the sum of the on-time, the first off-time, and the second off-time to the sum of the on-time and the first off-time.

[0024] In some embodiments, the PFC circuit may utilize one or more gallium nitride (GaN)-based and / or silicon carbide-based and / or silicon-based devices. By utilizing compound semiconductor devices, embodiments of the present disclosure may enable the power converter to operate at relatively high frequencies, with relatively higher efficiency than conventional silicon-based circuits. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details need not be employed to practice the present disclosure. To avoid obscuring the present disclosure, well-known methods related to implementation are not described in detail. Various invention embodiments are described herein, including methods, processes, systems, devices, and the like.

[0025] Figure 1 A schematic diagram of an example of a power factor correction system according to some embodiments of the present disclosure is shown. System 900 includes a power factor correction (PFC) circuit 901, a squared voltage divider 902, a compensation unit 903, an amplifier 904, two resistors 905a, 905b, a capacitor 906, an inductor 907, and a switch 908 having a drain terminal 9082, a gate terminal 9084, and a source terminal 9086. The squared voltage divider 902 can have an output node 9025 coupled to the PFC circuit 901.

[0026] Figure 2 An example of a compensation unit 903 is shown, and Figure 3 An example of a square voltage divider 902 is shown. Compensation unit 903 includes two capacitors 9031, 9032 and a resistor 9033. Square voltage divider 902 includes resistor 9021 and switch 9022. Square voltage divider 902 is configured to generate the inverse of the square of a voltage. In the illustrated embodiment, square voltage divider 902 can operate in discrete steps, while in some embodiments it can operate in a continuous manner.

[0027] The PFC circuit can operate by repeating cycles of charging and discharging an inductor. Each operating cycle includes a charging period, during which the current in the inductor transfers energy from the power source to the inductor, and a discharging period, during which the current in the inductor transfers energy from the inductor to the load.

[0028] The charge and discharge periods of an operating cycle constitute an operating cycle, and the PFC circuit typically operates in continuous conduction mode (CCM) or boundary conduction mode (BCM). In both CCM and BCM, the charge period of each cycle is followed by a discharge period, and the discharge period of an operating cycle is followed by a charge period of the next operating cycle.

[0029] In CCM, the current in the inductor does not drop to zero during an operating cycle, whereas in BCM, the current drops to zero at the end of the discharge period of each operating cycle and then recovers immediately at the beginning of the charge period of the subsequent operating cycle. BCM can be said to operate at the boundary between CCM and discontinuous conduction mode (DCM).

[0030] Discontinuous conduction mode (DCM) occurs when an operating cycle may include significant periods during which the inductor is neither charging nor discharging, during which the net inductor current is zero. Therefore, in a PFC circuit operating in DCM, each operating cycle includes a charging period, a discharging period, and a zero-current period.

[0031] Figure 4 The inductor current in the boost converter when operating in DCM is shown. For a boost converter operating in critical conduction mode (CrM), t3 = 0 or T = t1 + t2. The average input current in each switching cycle is calculated by the following expression:

[0032]

[0033] L is the inductance of the inductor in the boost converter. IN is the average input current in the cycle, and V IN is the average input voltage during the cycle.

[0034] In order to achieve an average input current proportional to the average input voltage, it is ideal to make Keep it constant (assuming the inductance of the inductor is constant). That is, Then In CrM or BCM, T = t1 + t2 + t3, and t3 = 0. However, in practice, the value of C involves multiple components in the PFC circuit and can vary or be affected by the manufacturing process even for the same circuit. If the on-time (t1) can be recursively set to the form of the equation mentioned above, the power factor will be significantly improved.

[0035] In some embodiments, a PFC circuit is disclosed that can operate to minimize the variation of the constant C in the above-mentioned expression. That is, the linear relationship will be improved and more consistent.

[0036] In the present disclosure, the power factor correction circuit operating in CrM or DCM is configured to adjust the on-time duration T substantially according to the following relationship on :

[0037]

[0038] The first parameter in the numerator includes at least one first process-related parameter, and the second parameter in the denominator includes at least one second process-related parameter. For example, the first parameter can be a single process-related parameter, or can be the product of two or more different process-related parameters (with or without other factors). Similarly, the second parameter can be a single process-related parameter, or can be the product of two or more different process-related parameters (with or without other factors).

[0039] The first process-related parameter and the second process-related parameter are equivalent electrical characteristics associated with different components in the power factor correction circuit. For example, the first process-related parameter and the second process-related parameter may include a first resistance and a second resistance of different components (the first component and the second component) in the circuit. Resistance may be replaced by capacitance, transconductance, voltage, etc. By following the form of the above relationship, the circuit component factors appearing in the numerator and denominator will be equal, so that the effects of process variations can be minimized.

[0040] Figure 5 A PFC circuit 901 according to some embodiments is shown. The PFC circuit may be used in a boost converter and may include a feedback circuit 100, an amplification circuit 200, and a comparator 300.

[0041] The amplifier circuit 200 amplifies the error associated with the output voltage from the feedback circuit 100 and drives the feedback circuit 100. The feedback circuit 100 is based on the on-time T of the boost converter. on and disconnection duration T off The comparator 300 generates an on-duration time T based on the output voltage from the amplifying circuit 200. on .

[0042] In some embodiments, the feedback circuit 100 may include a current mirror 110, a switch 111, and a capacitor 112. The current mirror 110 receives a power supply voltage Vdd and a reference current I from the amplifier circuit 200. ref , the reference current is mirrored to the current I flowing through the switch 111 mirror .like Figure 7As shown, the amplifier circuit 200 may include an operational amplifier 210 having an inverting input terminal 706, a non-inverting input terminal 708, and an output terminal 710. The output terminal 710 may be coupled to a transconductance amplifier 211 and a buffer circuit 212. The inverting input terminal 706 may be coupled to an impedance element 213. The output terminal 710 may also be coupled to a comparator 712 having an inverting input terminal 714, a non-inverting input terminal 716, and an output terminal 718. In some embodiments, a sawtooth wave signal may be applied to the inverting input terminal 714. In various embodiments, the output terminal 718 may be coupled to a gate terminal 9084.

[0043] The first reference voltage 702 can be generated by the operational amplifier 210 at the output terminal 710 and applied to the non-inverting input terminal 716. The comparator 712 can use the sawtooth wave signal and compare it with the first reference voltage 702 and generate a control signal at its output terminal 718. The control signal can be transmitted to the gate terminal 9084 and control the on-time and off-time of the switch 908. The operational amplifier 210 can generate the first reference voltage 702 by forcing the voltage at the inverting input terminal 706 to be equal to the voltage at the non-inverting input terminal 708, where the non-inverting input terminal 708 can be coupled to the output node 9025, which can have a voltage VEA. The voltage at the inverting input terminal 706 can be determined by the current I through the second switch 111. mirror The second switch 111 can be switched in a switching cycle with a period of Ton+Toff. mirror A voltage may be generated at the inverting input terminal 706 by combination with the impedance element 213 .

[0044] Feedback circuit 100 is capable of generating an average voltage across impedance element 213 by outputting an output current having an average value implemented by capacitor 112. The combination of current mirror 110, switch 111, and capacitor 112 constitutes an additional feedback path, so that the feedback path in the PFC circuit is not eliminated when operating in DCM.

[0045] like Figure 6As shown in the example depicted in , the feedback circuit 100 may include a first P-type transistor 101, a second P-type transistor 102, a switch 103, and a capacitor 104. The first P-type transistor 101 and the second P-type transistor 102 form a current mirror that reflects the current flowing through the second P-type transistor 102 and generates an output current to the switch 103. The ratio between the currents is determined by the W / L ratio of each transistor in the transistors 101 and 102. The first P-type transistor 101 has a drain terminal 101a, a gate terminal 101b, and a source terminal 101c. The second P-type transistor 102 has a drain terminal 102a, a gate terminal 102b, and a source terminal 102c. The source terminals 101c and 102c are respectively coupled to a power supply voltage. The gate terminal 101b of the first P-type transistor 101 is connected to the gate terminal 102b of the second P-type transistor 102. A node 100a between the gate terminal 101b of the first P-type transistor 101 and the gate terminal 102b of the second P-type transistor 102 is connected to the drain terminal 102a. A switch 103 is coupled to the drain terminal 101a of the first P-type transistor 101, and the drain terminal is controlled by a control signal that turns the switch 103 on for a duration T. on and disconnection duration T off The combination of the first P-type transistor 101, the second P-type transistor 102 and the switch 103 acts as a feedback path, and the capacitor 104 forms another feedback path.

[0046] Feedback circuit 100 includes two feedback paths. The first feedback path, consisting of first and second P-type transistors 101 and 102, is located at discrete intervals and is active only when switch 103 is on. The second feedback path, through capacitor 104, is always active. This prevents amplifier saturation when switch 103 is on. At the same time, capacitor 104 helps average the discrete current signals from the other feedback paths, thereby producing an average output current.

[0047] Because the feedback path through first P-type transistor 101 and second P-type transistor 102 is disconnected during the dead time in DCM, the additional feedback path ensures that feedback in the PFC circuit is not interrupted and the amplifier in amplifier circuit 200 does not saturate. The average output current of feedback circuit 100 flows out of node 100 b and regulates node 200 a in amplifier circuit 200.

[0048] The amplifier circuit 200 amplifies the difference between the node 200a and the error amplifier output voltage (also called error voltage V EA The output of the amplifier circuit 200 is used to drive the feedback circuit 100 to minimize the error at the input of the operational amplifier.

[0049] The amplifier circuit 200 includes an operational amplifier 201, a first resistor 202, an N-type transistor 203, a third P-type transistor 204, a second resistor 205, and a current source 206. The operational amplifier 201 has a non-inverting input 201a, an inverting input 201b, and an output 201c. The non-inverting input 201a is applied with an error amplifier output voltage. In one example, the error amplifier output voltage comes from Figure 1 1. A square voltage divider 902 is provided in FIG. Inverting input 201b is connected to node 100b between capacitor 104 and switch 103. First resistor 202 is coupled to node 200a between inverting input 201b and node 100b. N-type transistor 203 has a drain terminal 203a, a gate terminal 203b, and a source terminal 203c. Drain terminal 203a is coupled to drain terminal 102a of second P-type transistor 102. Gate terminal 203b is coupled to the output of operational amplifier 201. Source terminal 203c is connected to ground via second resistor 205. Third P-type transistor 204 has a drain terminal 204a, a gate terminal 204b, and a source terminal 204c. Source terminal 204c is coupled to current source 206. Gate terminal 204b is coupled between source terminal 203c and second resistor 205. Drain terminal 204a is connected to ground. The current source 206 is configured to generate a constant output current, and the capacitor 104 of the feedback circuit 100 is coupled to a node 200 c disposed between the output of the current source 206 and the third P-type transistor 204 .

[0050] Feedback circuit 100 senses the current flowing through second resistor 205 of amplifier circuit 200. The output voltage at node 200b is divided by second resistor 205 to generate a current, which acts as an input to drain terminal 102a of second P-type transistor 102, thereby forming a feedback path. Amplifier circuit 200 amplifies the error between node 200a and the error amplifier output voltage applied to non-inverting input 201a. As a result, amplifier circuit 200 drives feedback circuit 100 with minimized error at the input of operational amplifier 201.

[0051] The comparator 300 can be used to generate an on-time duration T from the output of the amplifier circuit 200. on Pulse width. The comparator 300 has a non-inverting input 300a, an inverting input 300b, and an output 300c. The non-inverting input 300a is connected to the sawtooth voltage (V SAW ) is coupled. The inverting input 300b is coupled to the node 200b between the source terminal 203c and the second resistor 205. The output 300c generates a on The on-time control signal is used to control the switch 103.

[0052] In the illustrated embodiment, the power factor correction circuit operating in CrM or DCM is configured to adjust the on-time T substantially according to the following relationship on :

[0053]

[0054] R1 represents the resistance of the first resistor 202, R2 represents the resistance of the second resistor 205, V EA Indicates from Figure 1 , and K represents the slope of the voltage ramp of the sawtooth voltage.

[0055] In some embodiments, the PFC circuits can be operated such that they follow the form of the relationship mentioned above, with the circuit component factors appearing in the numerator and denominator having the same electrical characteristics (equivalent circuit parameters) across the different circuit components, minimizing the effects of process variations. Additionally, the additional feedback path ensures that feedback within the PFC circuit is not interrupted and prevents amplifier saturation when operating in DCM.

[0056] Although the disclosed structures and techniques are described and illustrated herein with respect to certain specific configurations of PFC circuits, embodiments of the present disclosure are applicable to other configurations of power converters. For example, the techniques disclosed herein can be used in other power converter configurations, such as, but not limited to, flyback converters, ACF, AHB, and LLC converters.

[0057] In the foregoing description, embodiments of the present disclosure have been described with reference to numerous specific details, which may vary depending on the specific implementation. Therefore, the description and drawings should be regarded as illustrative rather than restrictive. The sole and exclusive indication of the scope of the present disclosure, and what the applicants intend as the scope of the present disclosure, is the literal and equivalent scope of the claims published in this application, in the specific form in which those claims are published, including any subsequent revisions. The specific details of specific embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the present disclosure.

[0058] In addition, spatial relative terms, such as "bottom" or "top", etc., can be used to describe the relationship of one element and / or feature to another element and / or feature, for example, as shown in the figure. It should be understood that spatial relative terms are intended to cover different orientations of the device in use and / or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as the "bottom" surface can then be oriented "above" other elements or features. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.

[0059] As used herein, the terms "and", "or" and "and / or" may include multiple meanings, which are also expected to depend at least in part on the context in which the terms are used. Generally, "or", if used in an associative list (such as A, B or C), is intended to mean A, B and C (used herein in an inclusive sense) as well as A, B or C (used herein in an exclusive sense). In addition, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular, or may be used to describe some combination of features, structures or characteristics. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to this example. In addition, the term "at least one", if used in an associative list (such as A, B or C), may be interpreted to mean any combination of A, B and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0060] References throughout this specification to "one example," "an example," "some examples," or "example implementations" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Thus, appearances of the phrases "in one example," "an example," "in some examples," "in some implementations," or other similar phrases throughout this specification are not necessarily all referring to the same feature, example, and / or limitation. Furthermore, particular features, structures, or characteristics may be combined into one or more examples and / or features.

[0061] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will appreciate that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatus known to those skilled in the art have not been described in detail in order to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of the appended claims and their equivalents.

[0062] One of ordinary skill in the art will understand that other modifications may be made to the apparatus and methods of the present disclosure to implement various applications of the method and system for an enhanced area getter architecture for wafer-level vacuum packaging of uncooled focal plane arrays without departing from the scope of the present disclosure.

[0063] The examples and embodiments described herein are for illustrative purposes only. Various modifications or variations thereof will be apparent to those skilled in the art. These modifications or variations will be within the spirit and scope of the present application and the scope of the appended claims.

[0064] It will be appreciated that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0065] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include the plural forms. It should also be understood that when used in this article, the terms "comprise", "comprising", "include" and / or "including" specify the presence of the features, elements and / or components, but do not exclude the presence or addition of one or more other features, elements, components and / or groups thereof. Indefinite and definite articles should cover both the plural and singular, unless the contrary is obvious from the context.

Claims

1. A method of operating a power factor correction (PFC) circuit, the method comprising: receiving an input voltage at an input terminal; Current in an inductor is controlled by a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: During an on-time of the first switch, the current in the inductor increases from substantially zero to a peak value; During a first off-time of the first switch, the current in the inductor decreases from the peak value to substantially zero; and During a second off-time of the first switch, the current in the inductor is substantially zero; generating a first reference voltage, wherein the first reference voltage is inversely proportional to a sum of the on-time and the first off-time of the first switch; as well as The on-time of the first switch is controlled in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first off-time and the second off-time to a sum of the on-time and the first off-time.

2. The method of claim 1 , wherein generating the first reference voltage comprises: generating a first voltage, wherein the first voltage is proportional to the sum of the on-time and the first off-time of the first switch; generating a second voltage by comparing the input voltage with a second reference voltage; as well as The first reference voltage is generated by setting the first voltage equal to the second voltage.

3. The method of claim 2 , wherein generating the first voltage comprises: generating a current signal corresponding to the first reference voltage; and The current signal is transmitted to a second switch arranged to switch with a switching cycle proportional to a sum of the on-time and the first off-time of the first switch.

4. The method of claim 3 , wherein generating the first voltage further comprises: generating a voltage signal corresponding to the first reference voltage; and The voltage signal is transmitted to a first capacitor coupled to the second switch.

5. The method of claim 1 , wherein controlling the on-time of the first switch comprises: generating a sawtooth wave signal; and The sawtooth wave signal is compared with the first reference voltage to generate a control signal for the first switch.

6. The method of claim 2, wherein generating the second voltage comprises: Producing an inverse proportional to the square of the input voltage; and The inverse ratio of the square of the input voltage is multiplied by a third voltage corresponding to the input voltage.

7. A method of operating a power factor correction (PFC) circuit, the method comprising: receiving an input voltage at an input terminal; Current in an inductor is controlled by a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: During the on-time of the first switch, the inductor is charged with a certain amount of energy; releasing the amount of energy from the inductor during a first off-time of the first switch; and During a second off-time of the first switch, the inductor remains discharged; generating a first reference voltage, wherein the first reference voltage is inversely proportional to a sum of the on-time and the first off-time of the first switch; as well as The on-time of the first switch is controlled in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first off-time and the second off-time to a sum of the on-time and the first off-time.

8. The method of claim 7, wherein generating the first reference voltage comprises: generating a first voltage, wherein the first voltage is proportional to the sum of the on-time and the first off-time of the first switch; generating a second voltage by comparing the input voltage with a second reference voltage; as well as The first reference voltage is generated by setting the first voltage equal to the second voltage.

9. The method of claim 8, wherein generating the first voltage comprises: generating a current signal corresponding to the first reference voltage; and The current signal is transmitted to a second switch arranged to switch with a switching cycle proportional to a sum of the on-time and the first off-time of the first switch.

10. The method of claim 9, wherein generating the first voltage further comprises: generating a voltage signal corresponding to the first reference voltage; and The voltage signal is transmitted to a first capacitor coupled to the second switch.

11. The method of claim 7, wherein controlling the on-time of the first switch comprises: generating a sawtooth wave signal; and The sawtooth wave signal is compared with the first reference voltage to generate a control signal for the first switch.

12. The method of claim 8, wherein generating the second voltage comprises: Producing an inverse proportional to the square of the input voltage; and The inverse ratio of the square of the input voltage is multiplied by a third voltage corresponding to the input voltage.

13. The method of claim 9, wherein the current signal is a first current signal, and wherein generating the first current signal comprises: A second current signal corresponding to the first reference voltage is generated by a transconductance amplifier; and the first current signal corresponding to the second current signal is generated by a current mirror.

14. A method of operating a power factor correction (PFC) circuit, the method comprising: receiving an input voltage at an input terminal; Current in an inductor is controlled by a first switch having a drain terminal, a source terminal, and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal, and wherein: During an on-time of the first switch, the inductor is charged to a first energy state; During a first off-time of the first switch, the inductor discharges to a second energy state; and During a second off-time of the first switch, the inductor remains in the second energy state; generating a first reference voltage, wherein the first reference voltage is inversely proportional to a sum of the on-time and the first off-time of the first switch; as well as The on-time of the first switch is controlled in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first off-time and the second off-time to a sum of the on-time and the first off-time.

15. The method of claim 14, wherein generating the first reference voltage comprises: generating a first voltage, wherein the first voltage is proportional to the sum of the on-time and the first off-time of the first switch; generating a second voltage by comparing the input voltage with a second reference voltage; as well as The first reference voltage is generated by setting the first voltage equal to the second voltage.

16. The method of claim 15, wherein generating the first voltage comprises: generating a current signal corresponding to the first reference voltage; and The current signal is transmitted to a second switch arranged to switch with a switching cycle proportional to a sum of the on-time and the first off-time of the first switch.

17. The method of claim 16, wherein generating the first voltage further comprises: generating a voltage signal corresponding to the first reference voltage; and The voltage signal is transmitted to a first capacitor coupled to the second switch.

18. The method of claim 14, wherein controlling the on-time of the first switch comprises: generating a sawtooth wave signal; and The sawtooth wave signal is compared with the first reference voltage to generate a control signal for the first switch.

19. The method of claim 15, wherein generating the second voltage comprises: Producing an inverse proportional to the square of the input voltage; and The inverse ratio of the square of the input voltage is multiplied by a third voltage corresponding to the input voltage.

20. The method of claim 16, wherein the current signal is a first current signal, and wherein generating the first current signal comprises: A second current signal corresponding to the first reference voltage is generated by a transconductance amplifier; and the first current signal corresponding to the second current signal is generated by a current mirror.

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