Charge pump type serial data IO interface
Through the charge pump series data IO interface, the output driving circuit and charge pump circuit designed with the full NMOS tube are solved, and the area and power consumption problems of chip data signal output driving external load is achieved, which achieves higher response speed and lower power consumption, and is suitable for high-speed systems.
Patent Information
- Application Number
- CN202510515569.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, when the data signal output of the chip needs to drive a large external load, it consumes a large circuit area and power consumption, which easily generates a latch effect, slow response speed, and complex layout design.
The charge pump series data IO interface is adopted, including a clock circuit, a charge pump circuit and an output drive circuit. The output drive circuit designed with a full NMOS tube is used to reduce the output impedance, avoid the latch effect, and pull the output voltage up to VDD through the charge pump circuit.
Simplifies the design process, reduces circuit area and power consumption, improves response speed, and is suitable for higher speed systems.
Smart Images
Figure CN120454706A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a charge pump type serial data IO interface. Background Art
[0002] The IO (input-output) port circuit is one of the basic modules in the chip. Its main function is to provide an interface between the package pins and the inside of the chip, introduce external signals into the chip to implement logical functions and output the results to the circuit outside the chip. It can be configured to support a variety of different interface standards as needed.
[0003] The data signal output of a chip or integrated circuit requires an I / O interface to drive a large external load. Typically, multiple cascaded inverters are used as I / O interfaces to drive the load. This approach consumes a large circuit area, consumes high power, and is prone to latch-up. Furthermore, the circuit's response speed is relatively slow, making it inadequate for high-speed signal output systems. Furthermore, guard ring design is required during layout design, making the design process complex. Summary of the Invention
[0004] The purpose of the present invention is to provide a charge pump type serial data IO interface to solve the above technical problems.
[0005] To achieve the above object, the present invention provides a charge pump type serial data IO interface, comprising a clock circuit, a charge pump circuit and an output drive circuit;
[0006] The data signal and the enable signal are input into the clock circuit through the two input terminals of the clock circuit. The two output terminals of the clock circuit are respectively connected to the charge pump circuit and the output drive circuit. The output terminal of the charge pump circuit is connected to the output drive circuit.
[0007] Preferably, the clock circuit includes a buffer module, a first branch module, a second branch module and a third branch module;
[0008] The buffer module includes a first buffer and a second buffer, and the data signal and the enable signal are input through the first buffer and the second buffer;
[0009] The first branch module includes a first NAND gate and three first NOT gates connected in series, wherein the first NAND gate is connected in series with the three first NOT gates;
[0010] The second branch module includes a second NAND gate and a second NOT gate connected in series;
[0011] The third branch module includes a third NOT gate, a third NAND gate, a fourth NOT gate and a third buffer;
[0012] The first input terminal of the first NAND gate, the first input terminal of the second NAND gate, and the input terminal of the third NOT gate are all connected to the first buffer;
[0013] The second input terminal of the first NAND gate, the second input terminal of the second NAND gate, and the second input terminal of the third NAND gate are all connected to the second buffer; the output terminal of the third NAND gate is connected to the first input terminal of the third NAND gate;
[0014] The input end of the first branch module is connected to the third input end of the second NAND gate.
[0015] Preferably, the charge pump circuit includes an upper charge pump module, a lower charge pump module and a switch module;
[0016] The upper charge pump module includes two load NMOS tubes and two upper differential NMOS tubes;
[0017] The drains and gates of the two load NMOS transistors are both connected to the pull-up voltage VDD, the gates of the two load NMOS transistors are respectively connected to the drains of the two upper differential NMOS transistors, the sources of the two load NMOS transistors are respectively connected to the gates of the two upper differential NMOS transistors, the gate of the upper differential NMOS transistor is connected to the source of another upper differential NMOS transistor, the sources of the two upper differential NMOS transistors are respectively connected to a first capacitor and a second capacitor, the first capacitor is connected to the output end of the first first NOT gate, and the second capacitor is connected to the output end of the second first NOT gate;
[0018] The lower charge pump module includes a lower differential NMOS transistor and a lower differential PMOS transistor. The drain of the lower differential NMOS transistor, the gate of the lower differential PMOS transistor, and the drain of the lower differential PMOS transistor are all connected to the pull-up voltage VDD. The connection end of the gate of the lower differential NMOS transistor is arranged between the second capacitor and the source of the upper differential NMOS transistor. The source electrodes of the lower differential NMOS transistor and the lower differential PMOS transistor are connected and connected to a third capacitor. The third capacitor is connected to the output end of the second branch module.
[0019] The switch module includes a first switch PMOS tube, a second switch PMOS tube and a switch NMOS tube;
[0020] The source of the first switch PMOS transistor is connected to the pull-up voltage VDD, the gate of the first switch PMOS transistor is connected to the output end of the first branch module, the drain of the first switch PMOS transistor is electrically connected to the gate of the second switch PMOS transistor, the source of the second switch PMOS transistor is connected to the source connection end of the lower differential NMOS transistor and the lower differential PMOS transistor, the drain of the second switch PMOS transistor is connected to the drain of the switch NMOS transistor and is provided with a first voltage output end, the gate of the switch NMOS transistor is connected to the output end of the second branch module via a fifth NOT gate, the source of the switch NMOS transistor is grounded, and the output end of the third buffer is the second voltage output end.
[0021] Preferably, the output drive circuit includes a pull-up NMOS tube and a pull-down NMOS tube, the drain of the pull-up NMOS tube is connected to the pull-up voltage VDD, the gate of the pull-up NMOS tube is connected to the first voltage output end of the charge pump circuit, the source of the pull-up NMOS tube is connected to the drain of the pull-down NMOS tube and is connected to the IO output end, the IO output end is connected to the filter circuit, the gate of the pull-down NMOS tube is connected to the second voltage output end of the clock circuit, and the source of the pull-down NMOS tube is connected to the ground end.
[0022] Preferably, the filter circuit is an LC filter circuit.
[0023] Therefore, the present invention adopts the above-mentioned charge pump type serial data IO interface, which has the following beneficial effects:
[0024] (1) The output driver circuit 3 includes both a pull-up NMOS transistor and a pull-down NMOS transistor. Both use an NMOS design. Compared to conventional pull-up PMOS transistors, this reduces output impedance, avoids latch-up effects, and eliminates the need for guard rings in layout design, simplifying the design process. Furthermore, the reduced output impedance improves the circuit's response speed, enabling application in higher-speed systems. It also reduces circuit area and power consumption.
[0025] (2) Use a charge pump circuit to pull the output voltage up to VDD, avoiding the threshold voltage V th resulting in a drop in output voltage.
[0026] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 This is a schematic diagram of a charge pump serial data IO interface circuit of the present invention;
[0028] Figure 2 This is a schematic diagram of the clock circuit and charge pump circuit of the present invention.
[0029] Reference numerals
[0030] 1. Clock circuit; 11. Buffer module; 12. First branch module; 13. Second branch module; 14. Third branch module; 2. Charge pump circuit; 21. Upper charge pump module; 22. Lower charge pump module; 23. Switch module; 3. Output drive circuit. DETAILED DESCRIPTION
[0031] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the inventive product is usually placed when in use. These are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention. In the description of the present invention, it should also be noted that, unless otherwise expressly specified and limited, the terms "setting", "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be a communication between the internal parts of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0032] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0033] like Figure 1 As shown, a charge pump type serial data IO interface includes a clock circuit 1, a charge pump circuit 2 and an output driver circuit 3. The data signal DATA_IN and the enable signal EN are input to the clock circuit 1 through the two input terminals of the clock circuit 1. The two output terminals of the clock circuit 1 are respectively connected to the charge pump circuit 2 and the output driver circuit 3. The output terminal of the charge pump circuit 2 is connected to the output driver circuit 3.
[0034] like Figure 2 As shown, the clock circuit 1 includes a buffer module 11, a first branch module 12, a second branch module 13 and a third branch module 14. The buffer module 11 includes a first buffer and a second buffer, through which the data signal and the enable signal are input.
[0035] The first branch module 12 includes a first NAND gate and three first NOT gates connected in series, the first NAND gate being connected in series with the three first NOT gates. The second branch module 13 includes a second NAND gate and a second NOT gate connected in series. The third branch module 14 includes a third NOT gate, a third NAND gate, a fourth NOT gate, and a third buffer. The first input of the first NAND gate, the first input of the second NAND gate, and the input of the third NAND gate are all connected to the first buffer. The second input of the first NAND gate, the second input of the second NAND gate, and the second input of the third NAND gate are all connected to the second buffer; the output of the third NOT gate is connected to the first input of the third NAND gate. The input of the first branch module 12 is connected to the third input of the second NAND gate.
[0036] The charge pump circuit 2 includes an upper charge pump module 21 , a lower charge pump module 22 and a switch module 23 .
[0037] The upper charge pump module 21 includes two load NMOS transistors (M5 and M6) and two upper differential NMOS transistors (M3 and M4). The drains and gates of the two load NMOS transistors are both connected to the pull-up voltage VDD, the gates of the two load NMOS transistors are respectively connected to the drains of the two upper differential NMOS transistors, the sources of the two load NMOS transistors are respectively connected to the gates of the two upper differential NMOS transistors, the gate of the upper differential NMOS transistor is connected to the source of the other upper differential NMOS transistor, and the sources of the two upper differential NMOS transistors are respectively connected to a first capacitor (C2) and a second capacitor (C3), the first capacitor (C2) is connected to the output end of the first first NOT gate, and the second capacitor (C3) is connected to the output end of the second first NOT gate.
[0038] The lower charge pump module 22 includes a lower differential NMOS transistor (M1) and a lower differential PMOS transistor (M2); the drain of the lower differential NMOS transistor (M1), the gate of the lower differential PMOS transistor (M2), and the drain of the lower differential PMOS transistor (M2) are all connected to the pull-up voltage VDD; the connection end of the gate of the lower differential NMOS transistor (M1) is arranged between the second capacitor (C3) and the source of the upper differential NMOS transistor (M1); the source of the lower differential NMOS transistor (M1) and the lower differential PMOS transistor (M2) are connected and connected to a third capacitor (C1); the third capacitor (C1) is connected to the output end of the second branch module 13.
[0039] The switch module 23 includes a first switch PMOS transistor (M9), a second switch PMOS transistor (M8), and a switch NMOS transistor (M7). The source of the first switch PMOS transistor (M9) is connected to the pull-up voltage VDD, the gate of the first switch PMOS transistor (M9) is connected to the output end of the first branch module 12, the drain of the first switch PMOS transistor (M9) is electrically connected to the gate of the second switch PMOS transistor (M8), the source of the second switch PMOS transistor (M8) is connected to the source connection end of the lower differential NMOS transistor (M1) and the lower differential PMOS transistor (M2), the drain of the second switch PMOS transistor (M8) is connected to the drain of the switch NMOS transistor (M7) and is provided with a first voltage output end (A1), the gate of the switch NMOS transistor (M7) is connected to the output end of the second branch module 13 through a fifth NOT gate, the source of the switch NMOS transistor (M7) is grounded, and the output end of the third buffer is the second voltage output end (A2).
[0040] The output drive circuit 3 includes a pull-up NMOS transistor (M10) and a pull-down NMOS transistor (M11). The drain of the pull-up NMOS transistor (M10) is connected to the pull-up voltage VDD. The gate of the pull-up NMOS transistor (M10) is connected to the first voltage output terminal (A1) of the charge pump circuit 2. The source of the pull-up NMOS transistor (M10) is connected to the drain of the pull-down NMOS transistor (M11) and is connected to the IO output terminal (DATA_OUT). The IO output terminal (DATA_OUT) is connected to a filter circuit, which is an LC filter circuit. The gate of the pull-down NMOS transistor is connected to the second voltage output terminal of the clock circuit, and the source of the pull-down NMOS transistor (M11) is connected to the ground terminal. Both the pull-up NMOS transistor (M10) and the pull-down NMOS transistor (M11) adopt the design of an NMOS transistor. Compared with the traditional pull-up PMOS transistor and the inverter-type drive circuit design of the pull-down NMOS transistor, this not only changes the output impedance from r op ||r on Reduce to where r op 、r on is the output impedance of PMOS and NMOS tubes, gm n The transconductance of the NMOS transistors is 0.000. This all-NMOS design completely avoids the latch-up effect that is common in traditional structures and eliminates the need for guard rings in layout design. The reduced output impedance improves circuit response speed, enabling application in higher-speed systems while also reducing circuit area and power consumption.
[0041] Here’s how it works:
[0042] When the enable signal EN is set to a low level, the first voltage output terminal (A1) and the second voltage output terminal (A2) are both at a low level, the pull-up NMOS transistor (M10) and the pull-down NMOS transistor (M11) of the output drive circuit are turned off, the circuit is in a high-impedance state, and the output is maintained;
[0043] When the enable signal EN is set to a high level, the enable signal EN has no effect on the circuit output. When the data signal DATA_IN is at a low level, the source voltage of the second switch PMOS tube (M8) is VDD, which is consistent with the gate voltage of the second switch PMOS tube (M8). In this way, the second switch PMOS tube (M8) is turned off, and the switch NMOS tube (M7) is turned on to pull the first voltage output end (A1) down to GND. At this time, the second voltage output end (A2) is at a high level, and the pull-down NMOS tube (M11) pulls the output voltage down. When the data signal DATA_IN is at a high level, due to the voltage difference of the third capacitor (C1), the source of the second switch PMOS tube (M8) is 2VDD, and the gate maintains VDD unchanged. The second switch PMOS tube (M8) is turned on, the first voltage output end (A1) is at a high level, and the pull-up NMOS tube (M10) pulls the output voltage up. The upper charge pump module provides a higher voltage to the lower differential NMOS tube (M1), so that the first voltage output terminal (A1) provides a voltage of 2VDD. Compared with the diode connection, this method has a stronger transient response capability. And the output of the output drive circuit can reach VDD instead of VDD-V th , V th is the threshold voltage, which avoids the th resulting in a drop in output voltage.
[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solutions of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.
Claims
1. A charge pump serial data IO interface, characterized in that: Including a clock circuit, a charge pump circuit and an output drive circuit; The data signal and the enable signal are input into the clock circuit through the two input terminals of the clock circuit. The two output terminals of the clock circuit are respectively connected to the charge pump circuit and the output drive circuit. The output terminal of the charge pump circuit is connected to the output drive circuit.
2. The charge pump serial data IO interface according to claim 1, wherein: The clock circuit includes a buffer module, a first branch module, a second branch module and a third branch module; The buffer module includes a first buffer and a second buffer, and the data signal and the enable signal are input through the first buffer and the second buffer; The first branch module includes a first NAND gate and three first NOT gates connected in series, wherein the first NAND gate is connected in series with the three first NOT gates; The second branch module includes a second NAND gate and a second NOT gate connected in series; The third branch module includes a third NOT gate, a third NAND gate, a fourth NOT gate and a third buffer; The first input terminal of the first NAND gate, the first input terminal of the second NAND gate, and the input terminal of the third NOT gate are all connected to the first buffer; The second input terminal of the first NAND gate, the second input terminal of the second NAND gate, and the second input terminal of the third NAND gate are all connected to the second buffer; the output terminal of the third NAND gate is connected to the first input terminal of the third NAND gate; The input end of the first branch module is connected to the third input end of the second NAND gate.
3. The charge pump serial data IO interface according to claim 2, wherein: The charge pump circuit includes an upper charge pump module, a lower charge pump module and a switch module; The upper charge pump module includes two load NMOS tubes and two upper differential NMOS tubes; The drains and gates of the two load NMOS transistors are both connected to the pull-up voltage VDD, the gates of the two load NMOS transistors are respectively connected to the drains of the two upper differential NMOS transistors, the sources of the two load NMOS transistors are respectively connected to the gates of the two upper differential NMOS transistors, the gate of the upper differential NMOS transistor is connected to the source of another upper differential NMOS transistor, the sources of the two upper differential NMOS transistors are respectively connected to a first capacitor and a second capacitor, the first capacitor is connected to the output end of the first first NOT gate, and the second capacitor is connected to the output end of the second first NOT gate; The lower charge pump module includes a lower differential NMOS transistor and a lower differential PMOS transistor. The drain of the lower differential NMOS transistor, the gate of the lower differential PMOS transistor, and the drain of the lower differential PMOS transistor are all connected to the pull-up voltage VDD. The connection end of the gate of the lower differential NMOS transistor is arranged between the second capacitor and the source of the upper differential NMOS transistor. The source electrodes of the lower differential NMOS transistor and the lower differential PMOS transistor are connected and connected to a third capacitor. The third capacitor is connected to the output end of the second branch module. The switch module includes a first switch PMOS tube, a second switch PMOS tube and a switch NMOS tube; The source of the first switch PMOS tube is connected to the pull-up voltage VDD, the gate of the first switch PMOS tube is connected to the output end of the first branch module, the drain of the first switch PMOS tube is electrically connected to the gate of the second switch PMOS tube, and the source of the second switch PMOS tube is connected to the source connection end of the lower differential NMOS tube and the lower differential PMOS tube. The drain of the second switch PMOS tube is connected to the drain of the switch NMOS tube and is provided with a first voltage output end. The gate of the switch NMOS tube is connected to the output end of the second branch module through a fifth NOT gate. The source of the switch NMOS tube is grounded. The output end of the third buffer is the second voltage output end.
4. The charge pump serial data IO interface according to claim 3, wherein: The output drive circuit includes a pull-up NMOS transistor and a pull-down NMOS transistor. The drain of the pull-up NMOS transistor is connected to the pull-up voltage VDD, the gate of the pull-up NMOS transistor is connected to the first voltage output end of the charge pump circuit, the source of the pull-up NMOS transistor is connected to the drain of the pull-down NMOS transistor and is connected to the IO output end, the IO output end is connected to the filter circuit, the gate of the pull-down NMOS transistor is connected to the second voltage output end of the clock circuit, and the source of the pull-down NMOS transistor is connected to the ground end.
5. The charge pump serial data IO interface according to claim 4, wherein: The filter circuit is an LC filter circuit.