Ferroelectric material-based homogeneous pn junction device with reconfigurable two ends and preparation method of ferroelectric material-based homogeneous pn junction device

Abstract

The invention discloses a ferroelectric material-based homogeneous pn junction device with two reconfigurable ends and a preparation method thereof, the pn junction device comprises a substrate, a gate electrode layer, a ferroelectric layer, a double floating gate layer, an insulating layer, a semiconductor layer and a source and drain electrode layer adjacent to the semiconductor layer, the gate electrode layer and the semiconductor layer are respectively distributed at two sides of the double floating gate layer at intervals, one of the ferroelectric layer and the insulating layer is formed between the gate electrode layer and the double floating gate layer, the other one of the ferroelectric layer and the insulating layer is formed between the semiconductor layer and the double floating gate layer, and the gate electrode layer, the semiconductor layer or the source-drain electrode layer is formed on the substrate; the middle part of the double floating gate layer is provided with a separation groove so as to divide the double floating gate layer into two parts. According to the invention, regulation and control of a pn junction or an np junction can be realized, programmable positive and negative photoelectric response can be further realized, external connection ports of the device are reduced, the complexity of a peripheral circuit is reduced, and the integration level of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices and integrated technology, and in particular to a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials and a preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence (AI), the explosive growth of visual information is driving an increasing demand for image processing. Traditional digital image processing systems, due to the separation of sensing and processing units, lead to redundancy, high power consumption, and latency in data transfer. The human visual system, however, exhibits remarkable efficiency and low energy consumption. The human visual cognition process begins with the photoreceptors on the retina converting light signals into electrical signals, which are then processed and pre-processed by bipolar cells. Only the key information features are extracted and transmitted to the cerebral cortex for further processing, ultimately passing them on to higher brain regions to form cognition. Therefore, constructing a system that simulates the structure and function of the human visual system, achieving a low-energy, efficient brain-like visual system, and developing a multi-dimensional integrated intelligent sensing, storage, and computing chip are of great significance and are expected to promote the further development of AI.

[0003] In the field of modern electronics, the development of semiconductor devices has always been a key factor driving technological progress. As one of the basic structures of semiconductor devices, the pn junction plays a vital role in electronics and optoelectronics. Currently, existing homogeneous pn junction devices that integrate sensing, storage, and computing generally adopt a four-terminal structure. These devices face challenges such as requiring a large number of ports, complex peripheral circuit configuration, and high hardware costs, which limit the integration and application of large-scale devices. Therefore, it is necessary to improve existing technologies to overcome these shortcomings. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials and a preparation method thereof, which can form a strong local electric field at the interface of the ferroelectric material, electrostatically dope the semiconductor, realize programmable positive and negative photoelectric response, and simulate the function of bipolar cells in the human brain. By introducing a dual floating gate electrode that does not require external connection, the external connection ports of the device are reduced, which can improve the integration and practical application of the device, and further establish a highly integrated brain-like visual system with integrated sensing, storage and computing.

[0005] The technical solution adopted by the present invention to solve its technical problems is: a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material, comprising: a substrate, a gate electrode layer, a ferroelectric layer, a double floating gate layer, an insulating layer, a semiconductor layer and a source-drain electrode layer arranged adjacent to the semiconductor layer, one of the ferroelectric layer and the insulating layer is formed between the gate electrode layer and the double floating gate layer, and the other of the two is formed between the semiconductor layer and the double floating gate layer; the gate electrode layer, the semiconductor layer or the source-drain electrode layer is formed on the substrate; wherein a separation groove is provided in the middle of the double floating gate layer to split itself into two parts; when positive and negative voltages are applied to the two ends of the source-drain electrode layer respectively, the ferroelectric layer can electrostatically dope the semiconductor layer, thereby adjusting the polarity of the semiconductor layer to form a pn junction or an np junction.

[0006] As a further improvement of the present invention, the materials of the gate electrode layer and the source / drain electrode layer are one or more of metal, conductive metal oxide, and conductive metal nitride.

[0007] As a further improvement of the present invention, the material of the ferroelectric layer is a ferroelectric material.

[0008] As a further improvement of the present invention, the material of the double floating gate layer is one or more of metal, conductive metal oxide, and conductive metal nitride.

[0009] As a further improvement of the present invention, the material of the insulating layer is oxide or two-dimensional insulating material, and the thickness of the insulating layer is several nanometers to more than ten nanometers.

[0010] As a further improvement of the present invention, the material of the semiconductor layer is a two-dimensional semiconductor, a metal oxide or an organic semiconductor.

[0011] The present invention also provides a method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, comprising the following steps:

[0012] providing a substrate;

[0013] forming a gate electrode layer on the substrate;

[0014] forming a ferroelectric layer on the gate electrode layer; wherein the material of the ferroelectric layer is hafnium-based ferroelectric, lead zirconate titanate, barium titanate, bismuth ferrite or a two-dimensional ferroelectric material;

[0015] forming a split double floating gate layer on the ferroelectric layer;

[0016] forming an insulating layer on the double floating gate layer;

[0017] A semiconductor layer and a source-drain electrode layer are sequentially formed on the insulating layer, or a source-drain electrode layer and a semiconductor layer are sequentially formed on the insulating layer, thereby producing the above-mentioned two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials.

[0018] The present invention also provides another method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, comprising the following steps:

[0019] providing a substrate;

[0020] forming a gate electrode layer on the substrate;

[0021] forming an insulating layer on the gate electrode layer;

[0022] forming a split double floating gate layer on the insulating layer;

[0023] forming a ferroelectric layer on the double floating gate layer; wherein the material of the ferroelectric layer is hafnium-based ferroelectric, lead zirconate titanate, barium titanate, bismuth ferrite or a two-dimensional ferroelectric material;

[0024] A semiconductor layer and a source-drain electrode layer are sequentially formed on the ferroelectric layer, or a source-drain electrode layer and a semiconductor layer are sequentially formed on the ferroelectric layer, thereby obtaining the above-mentioned two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials.

[0025] The present invention also provides another method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, comprising the following steps:

[0026] providing a substrate;

[0027] forming a source-drain electrode layer, a semiconductor layer, and an insulating layer in sequence on the substrate, or forming a semiconductor layer, a source-drain electrode layer, and an insulating layer in sequence on the substrate,

[0028] forming a split double floating gate layer on the insulating layer;

[0029] forming a ferroelectric layer on the double floating gate layer; wherein the material of the ferroelectric layer is organic ferroelectric or molecular ferroelectric;

[0030] A gate electrode layer is formed on the ferroelectric layer, thereby manufacturing the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as described above.

[0031] The present invention also provides another method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, comprising the following steps:

[0032] providing a substrate;

[0033] forming a source-drain electrode layer, a semiconductor layer and a ferroelectric layer in sequence on the substrate, or forming a semiconductor layer, a source-drain electrode layer and a ferroelectric layer in sequence on the substrate; wherein the material of the ferroelectric layer is organic ferroelectric or molecular ferroelectric;

[0034] forming a split double floating gate layer on the ferroelectric layer;

[0035] forming an insulating layer on the double floating gate layer;

[0036] A gate electrode layer is formed on the surface of the insulating layer, thereby manufacturing the above-mentioned two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material.

[0037] The beneficial effects of the present invention are as follows: the present invention provides a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials. By introducing a split double floating gate layer structure that does not require external connection, applying voltage at both ends of the source and drain electrode layers can realize electrostatic doping of the ferroelectric layer to the semiconductor layer, and can realize the regulation of the pn junction or np junction, and further realize programmable positive and negative photoelectric responses, thereby reducing the external connection ports of the device, reducing the complexity of the peripheral circuit, and improving the integration of the device in constructing an integrated sensing, storage and computing device. At the same time, the introduction of the double floating gate layer also helps to enhance its retention characteristics; at the same time, the preparation method of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials of the present invention is easy to operate, low in cost, and easy to achieve large-area preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic structural diagram of a first embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0039] Figure 2 This is a flow chart for preparing a first embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0040] Figure 3 The IV curve of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material of the present invention is shown;

[0041] Figure 4 This is a graph showing the positive and negative photoelectric response test results of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials of the present invention;

[0042] Figure 5 This is a schematic structural diagram of a second embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0043] Figure 6 This is a flow chart for preparing a second embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0044] Figure 7This is a schematic structural diagram of a third embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0045] Figure 8 This is a flow chart for preparing the third embodiment of the present invention of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials;

[0046] Figure 9 This is a schematic structural diagram of a fourth embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0047] Figure 10 This is a flow chart for preparing a fourth embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0048] Figure 11 This is a schematic structural diagram of a fifth embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0049] Figure 12 This is a flow chart for preparing a fifth embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0050] Figure 13 This is a schematic structural diagram of a sixth embodiment of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials according to the present invention;

[0051] Figure 14 This is a preparation flow chart of Example 6 of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials of the present invention.

[0052] The following description is made with reference to the accompanying drawings:

[0053] 1. Substrate; 2. Gate electrode layer; 3. Ferroelectric layer; 4. Double floating gate layer; 5. Insulating layer; 6. Semiconductor layer; 7. Source and drain electrode layer. DETAILED DESCRIPTION

[0054] Several preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0055] Example 1

[0056] See Figure 1 The present invention provides a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, comprising: a substrate 1, a gate electrode layer 2, a ferroelectric layer 3, a double floating gate layer 4, an insulating layer 5, a semiconductor layer 6, and a source-drain electrode layer 7 arranged adjacent to the semiconductor layer 6, wherein the gate electrode layer 2 and the semiconductor layer 6 are distributed on both sides of the double floating gate layer 4 and are spaced apart from the double floating gate layer 4, the ferroelectric layer 3 is formed between the gate electrode layer 2 and the double floating gate layer 4, the insulating layer 5 is formed between the semiconductor layer 6 and the double floating gate layer 4, and the gate electrode layer 2 is formed on the substrate 1.

[0057] Specifically, in this embodiment, the substrate 1, the gate electrode layer 2, the ferroelectric layer 3, the double floating gate layer 4, the insulating layer 5, the semiconductor layer 6 and the source-drain electrode layer 7 are stacked in sequence from bottom to top, that is, the gate electrode layer 2 is configured on the substrate 1, the ferroelectric layer 3 is configured on the gate electrode layer 2, the double floating gate layer 4 is configured on the ferroelectric layer 3, the insulating layer 5 is configured on the double floating gate layer 4, the semiconductor layer 6 is configured on the insulating layer 5, and the source-drain electrode layer 7 is configured on the semiconductor layer 6.

[0058] A separation groove is provided in the middle of the double floating gate layer 4 to split it into two parts. The source-drain electrode layer 7 includes a source electrode layer and a drain electrode layer, which are formed on the semiconductor layer 6 at a certain distance.

[0059] In this embodiment, the gate electrode layer 2 is patterned on the substrate 1, that is, the gate electrode layer 2 is formed at the top center of the substrate 1. Of course, in other embodiments of the present invention, the gate electrode layer 2 can also completely cover the substrate 1. During the design stage, the size of the gate electrode layer 2 can be changed as needed to control the area of the gate electrode layer 2 and the dual floating gate layer 4, thereby adjusting the size of the capacitor formed therebetween and, in turn, the voltage divider of the ferroelectric layer 3.

[0060] In this embodiment, the substrate 1 may be a Si / SiO 2 substrate.

[0061] In the present invention, the material of the gate electrode layer 2 is one or more of metal, conductive metal oxide, conductive metal nitride or other materials that can be used as electrodes, such as tungsten. The thickness of the gate electrode layer 2 is between tens of nanometers and hundreds of nanometers, for example, 50nm.

[0062] In the present invention, the material of the ferroelectric layer 3 is a ferroelectric material, including but not limited to traditional ferroelectric materials (such as lead zirconate titanate, barium titanate, bismuth ferrite, etc.), hafnium-based ferroelectrics, organic ferroelectric materials and two-dimensional ferroelectric materials, etc. This embodiment specifically uses hafnium-based ferroelectric materials.

[0063] In the present invention, the material of the double floating gate layer 4 is one or more of metal, conductive metal oxide, conductive metal nitride or other materials that can be used as electrodes, such as tungsten. The thickness of the double floating gate layer 4 is in the range of several nanometers to several hundred nanometers, for example, 50nm.

[0064] In the present invention, the material of the insulating layer 5 is an oxide (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) or a two-dimensional insulating material (such as BN), and the thickness of the insulating layer 5 is several nanometers to more than ten nanometers, for example, it can be 5nm to 15nm, preferably 10nm.

[0065] In the present invention, the material of the semiconductor layer 6 is a two-dimensional semiconductor, a metal oxide or an organic semiconductor. This embodiment specifically uses a two-dimensional semiconductor material.

[0066] In the present invention, the material of the source-drain electrode layer 7 is one or more of metal, conductive metal oxide, conductive metal nitride or other materials that can be used as electrodes, such as chromium / gold. The thickness of the source-drain electrode layer 7 is between tens of nanometers and hundreds of nanometers, preferably 10nm or 50nm.

[0067] Figure 3 Shown is a rectification characteristic test diagram of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material provided in Example 1 of the present invention. As shown in the figure, when positive and negative voltages are applied to the two ends of the source and drain electrode layer 7 respectively, the polarization state of the ferroelectric layer 3 can be regulated, so that the ferroelectric layer 3 electrostatically dopes the semiconductor layer 6, and then the polarity of the semiconductor layer 6 is adjusted to form a pn junction or an np junction.

[0068] Figure 4 The figure shows a photoelectric response test diagram of a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials provided in Example 1 of the present invention. As shown in the figure, after applying positive and negative voltages to the two ends of the source and drain electrode layer 7 to control the formation of a pn or np junction, and then absorbing 445nm laser, positive and negative photoelectric responses can be observed respectively. In addition, the semiconductor layer MoTe2 in the present invention has a low band gap, which can achieve a broadband photoelectric response, and repeated control of the pn or np junction can be achieved through repeated testing, thereby achieving programmable positive and negative photoelectric responses. By adjusting the size of the ferroelectric polarization state, different rectification ratios can also be achieved, as well as multi-state control of the photocurrent.

[0069] In summary, the present invention provides a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials. By introducing a split double floating gate layer 4 structure that does not require external connection, applying voltage at both ends of the source and drain electrode layer 7 can realize electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6, and can realize the regulation of the pn junction or np junction, and further realize programmable positive and negative photoelectric responses, thereby reducing the external connection ports of the device and reducing the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved. At the same time, the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics.

[0070] See Figure 2 This embodiment provides a method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, including steps S1.1 to S7.1.

[0071] S1.1, provide a substrate 1.

[0072] Specifically, the substrate 1 is a Si / SiO2 substrate. In this step, the substrate 1 is cleaned, for example, the substrate 1 is placed in acetone, anhydrous ethanol, and deionized water for ultrasonic cleaning for 1 minute to 5 minutes, preferably 3 minutes, and then the substrate 1 is dried, for example, by blowing it dry with a nitrogen gun.

[0073] S2.1, forming a gate electrode layer 2 on the substrate 1.

[0074] Specifically, in this step, substrate 1 is first patterned using photolithography or electron beam lithography, and then a layer of metal tungsten (W) is sputtered onto the surface of substrate 1 using magnetron sputtering to form gate electrode layer 2. This is not limiting, and other types of metals, conductive metal oxides, or conductive metal nitrides may also be used. In this embodiment, the sputtering power is 100 W, the sputtering time is 2 minutes, and the thickness of gate electrode layer 2 is 40 nm.

[0075] In addition, the gate electrode layer 2 can also be formed by a thermal evaporation process, wherein during the thermal evaporation process, the gate electrode layer 2 deposition rate is The gate electrode layer 2 may also be formed on the substrate 1 by using an electron beam evaporation process.

[0076] S3.1, forming a ferroelectric layer 3 on the gate electrode layer 2.

[0077] Specifically, in this step, an atomic layer deposition process (ALD) is used to deposit a ferroelectric layer 3 on the gate electrode layer 2. The material of the ferroelectric layer 3 is Hf 0.5 Zr 0.5 O2 can also be other ferroelectric materials. The thickness of the ferroelectric layer 3 is 5 nm to 15 nm, for example, 10 nm. Furthermore, other ferroelectric layer materials, such as lead zirconate titanate, can also be prepared by spin coating, or by pulsed laser deposition, such as bismuth ferrite.

[0078] S4.1, forming a double floating gate layer 4 on the ferroelectric layer 3.

[0079] Specifically, in this step, photoresist is first spin-coated on the ferroelectric layer 3. Electron beam lithography or photolithography is then used to pattern the layer into columns with widths ranging from several hundred nanometers to several micrometers. Magnetron sputtering is then used to deposit a layer of tungsten (W) onto the surface of the ferroelectric layer 3 as the dual floating gate layer 4. This is not limiting and other metals, conductive metal oxides, or conductive metal nitrides may also be used. Alternatively, thermal evaporation or electron beam evaporation may be used to form the dual floating gate layer 4 on the surface of the ferroelectric layer 3.

[0080] S5.1 , forming an insulating layer 5 on the double floating gate layer 4 .

[0081] Specifically, in this step, an atomic layer deposition (ALD) process is used to form an insulating layer 5 on the dual floating gate layer 4. The insulating layer 5 is made of an oxide material. In this embodiment, the insulating layer 5 is made of an aluminum oxide thin film, but can also be made of other oxide materials such as hafnium oxide or zirconium oxide. The thickness of the insulating layer 5 ranges from 5 nm to 15 nm, for example, 10 nm. Of course, this is not limiting. A mechanical lift-off transfer process can also be used to form a two-dimensional material such as BN on the dual floating gate layer 4.

[0082] S6.1, forming a semiconductor layer 6 on the insulating layer 5.

[0083] Specifically, in this step, a mechanical lift-off transfer process is used to deposit a semiconductor layer 6, such as MoTe2, on the insulating layer 5. Of course, other bipolar two-dimensional semiconductor materials or organic semiconductors can also be used. The transferred two-dimensional material has a thickness ranging from a few nanometers to more than ten nanometers. For example, a magnetron sputtering process can be used to deposit a metal oxide as the semiconductor layer 6 on the insulating layer 5. Alternatively, the semiconductor layer 6 can be formed by spin coating or evaporation of an organic semiconductor.

[0084] S7.1, forming a source-drain electrode layer 7 on the semiconductor layer 6.

[0085] Specifically, in this step, patterning is performed using electron beam exposure technology or photolithography technology, and then magnetron sputtering technology is used to sputter the source and drain electrode layer 7, such as metal chromium / gold (Cr / Au), on the surface of the semiconductor layer 6. The thickness of the source and drain electrode layer 7 is in the range of tens of nanometers to hundreds of nanometers, for example, 10nm or 50nm. Of course, the source and drain electrode layer 7 can also be formed by thermal evaporation process, wherein the deposition rate of Cr and Au can be and Of course, those skilled in the art will appreciate that the material of the source-drain electrode layer 7 may also be one or more of other types of metals, conductive metal oxides, or conductive metal nitride materials.

[0086] Finally, the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as described in Example 1 was obtained.

[0087] It can be seen that the preparation method of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials of the present invention forms a gate electrode layer 2 on the substrate 1 through magnetron sputtering, thermal evaporation or electron beam evaporation process, forms a ferroelectric layer 3 on the gate electrode layer 2 through atomic layer deposition process, spin coating process or pulsed laser deposition technology, forms a double floating gate layer 4 on the ferroelectric layer 3 through magnetron sputtering, thermal evaporation or electron beam evaporation process, forms an insulating layer 5 on the double floating gate layer 4 through atomic layer deposition or mechanical stripping transfer process, and forms a semiconductor layer 6 on the insulating layer 5 through mechanical stripping transfer, magnetron sputtering, spin coating or evaporation process. This method is easy to operate, low in cost, and easy to achieve large-area preparation.

[0088] Example 2

[0089] See Figure 5 The difference between this embodiment and the first embodiment is that the positions of the ferroelectric layer 3 and the insulating layer 5 are different.

[0090] Specifically, in this embodiment, the substrate 1, the gate electrode layer 2, the insulating layer 5, the double floating gate layer 4, the ferroelectric layer 3, the semiconductor layer 6 and the source-drain electrode layer 7 are stacked in sequence from bottom to top, that is, the gate electrode layer 2 is configured on the substrate 1, the insulating layer 5 is configured on the gate electrode layer 2, the double floating gate layer 4 is configured on the insulating layer 5, the ferroelectric layer 3 is configured on the double floating gate layer 4, the semiconductor layer 6 is configured on the ferroelectric layer 3, and the source-drain electrode layer 7 is configured on the semiconductor layer 6.

[0091] The materials used in this embodiment are the same as those in the first embodiment in terms of the substrate 1 , the gate electrode layer 2 , the insulating layer 5 , the double floating gate layer 4 , the ferroelectric layer 3 , the semiconductor layer 6 and the source-drain electrode layer 7 .

[0092] This embodiment introduces a split double floating gate layer 4 structure that does not require external connection. By applying voltage at both ends of the source and drain electrode layer 7, it is also possible to achieve electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6, thereby realizing the regulation of the pn junction or np junction, and further realizing programmable positive and negative photoelectric responses, thereby reducing the external connection ports of the device and the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved. At the same time, the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics.

[0093] See Figure 6 This embodiment provides a method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, including steps S1.2 to S7.2.

[0094] S1.2, provide a substrate 1.

[0095] Specifically, the substrate 1 is a Si / SiO2 substrate. In this step, the substrate 1 is cleaned, for example, the substrate 1 is placed in acetone, anhydrous ethanol, and deionized water for ultrasonic cleaning for 1 minute to 5 minutes, preferably 3 minutes, and then the substrate 1 is dried, for example, by blowing it dry with a nitrogen gun.

[0096] S2.2, forming a gate electrode layer 2 on the substrate 1.

[0097] Specifically, in this step, substrate 1 is first patterned using photolithography or electron beam lithography. Magnetron sputtering is then used to deposit a layer of tungsten (W) onto the surface of substrate 1 as gate electrode layer 2. This is not limiting; other metals, conductive metal oxides, or conductive metal nitrides may also be used. In this embodiment, the sputtering power is 100 W, the sputtering time is 2 minutes, and the thickness of gate electrode layer 2 is 40 nm.

[0098] In addition, the gate electrode layer 2 can also be formed by a thermal evaporation process, wherein during the thermal evaporation process, the gate electrode layer 2 deposition rate is The gate electrode layer 2 may also be formed on the substrate 1 by using an electron beam evaporation process.

[0099] S3.2, forming an insulating layer 5 on the gate electrode layer 2.

[0100] Specifically, in this step, an atomic layer deposition (ALD) process is used to form an insulating layer 5 on the gate electrode layer 2. The insulating layer 5 is made of an oxide material. In this embodiment, the insulating layer 5 is made of an aluminum oxide film, but may also be made of other oxide materials such as hafnium oxide or zirconium oxide. The thickness of the insulating layer 5 is in the range of 5 nm to 15 nm, for example, 10 nm. Of course, this is not limiting, and a mechanical lift-off transfer process may also be used to form a two-dimensional material such as BN on the gate electrode layer 2.

[0101] S4.2, forming a double floating gate layer 4 on the insulating layer 5.

[0102] Specifically, in this step, photoresist is first spin-coated on the insulating layer 5. Electron beam lithography or photolithography is then used to pattern the layers to form columns with widths ranging from several hundred nanometers to several micrometers. Magnetron sputtering is then used to deposit a layer of tungsten (W) onto the surface of the insulating layer 5 as the dual floating gate layer 4. This is not limiting and other metals, conductive metal oxides, or conductive metal nitrides may also be used. Alternatively, thermal evaporation or electron beam evaporation may be used to form the dual floating gate layer 4.

[0103] S5.2, forming a ferroelectric layer 3 on the double floating gate layer 4.

[0104] Specifically, in this step, an atomic layer deposition process (ALD) is used to deposit a ferroelectric layer 3 on the double floating gate layer 4. The material of the ferroelectric layer 3 is Hf 0.5 Zr 0.5 O2 can also be other ferroelectric materials. The thickness of the ferroelectric layer 3 is 5 nm to 15 nm, for example, 10 nm. Alternatively, other ferroelectric layer materials, such as lead zirconate titanate, can be prepared by spin coating. Alternatively, other ferroelectric layer materials, such as bismuth ferrite, can be deposited as free-standing thin films onto the gate dielectric layer using pulsed laser deposition.

[0105] S6.2, forming a semiconductor layer 6 on the ferroelectric layer 3.

[0106] Specifically, in this step, a mechanical lift-off transfer process is used to deposit a semiconductor layer 6, such as MoTe2, on the ferroelectric layer 3. Of course, other bipolar two-dimensional semiconductor materials or organic semiconductors can also be used. The transferred two-dimensional material has a thickness ranging from a few nanometers to more than ten nanometers. For example, a magnetron sputtering process can be used to deposit a metal oxide as the semiconductor layer 6 on the ferroelectric layer 3. Alternatively, the semiconductor layer 6 can be formed by spin coating or evaporating an organic semiconductor.

[0107] S7.2, forming a source-drain electrode layer 7 on the semiconductor layer 6.

[0108] Specifically, in this step, patterning is performed using electron beam exposure technology or photolithography technology, and then magnetron sputtering technology is used to sputter the source and drain electrode layer 7, such as metal chromium / gold (Cr / Au), on the surface of the semiconductor layer 6. The thickness of the source and drain electrode layer 7 is in the range of tens of nanometers to hundreds of nanometers, for example, 10nm or 50nm. Of course, the source and drain electrode layer 7 can also be formed by thermal evaporation process, wherein the deposition rate of Cr and Au can be and Of course, those skilled in the art will appreciate that the material of the source-drain electrode layer 7 may also be one or more of other types of metals, conductive metal oxides, or conductive metal nitride materials.

[0109] Finally, the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials as described in Example 2 was obtained. It can be seen that the preparation method of the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials of the present invention is easy to operate, low in cost, and easy to achieve large-scale preparation.

[0110] In other embodiments of the present invention, the manufacturing order of the semiconductor layer 6 and the source-drain electrode layer 7 can also be exchanged, that is, the source-drain electrode layer 7 is first formed on the ferroelectric layer 3, and then the semiconductor layer 6 is formed. Similarly, a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials can be obtained.

[0111] Example 3

[0112] See Figure 7 The difference between this embodiment and the first embodiment is that: in this embodiment, the substrate 1, the source-drain electrode layer 7, the semiconductor layer 6, the insulating layer 5, the double floating gate layer 4, the ferroelectric layer 3 and the gate electrode layer 2 are stacked in sequence from bottom to top, that is, the source-drain electrode layer 7 is configured on the substrate 1, the semiconductor layer 6 is configured on the source-drain electrode layer 7, the insulating layer 5 is configured on the semiconductor layer 6, the double floating gate layer 4 is configured on the insulating layer 5, the ferroelectric layer 3 is configured on the double floating gate layer 4, and the gate electrode layer 2 is configured on the ferroelectric layer 3.

[0113] The materials used in this embodiment are the same as those in the first embodiment in terms of the substrate 1 , the gate electrode layer 2 , the double floating gate layer 4 , the insulating layer 5 , the semiconductor layer 6 and the source-drain electrode layer 7 , but the material of the ferroelectric layer 3 is different.

[0114] Specifically, the material used for the ferroelectric layer 3 in this embodiment is organic ferroelectric, such as polymer P (VDF-TrFE).

[0115] This embodiment introduces a split double floating gate layer 4 structure that does not require external connection. By applying voltage at both ends of the source and drain electrode layer 7, it is also possible to achieve electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6, thereby realizing the regulation of the pn junction or np junction, and further realizing programmable positive and negative photoelectric responses, thereby reducing the external connection ports of the device and the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved. At the same time, the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics.

[0116] See Figure 8 In this embodiment, a method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials includes steps S1.3 to S7.3.

[0117] S1.3, provide a substrate 1.

[0118] Specifically, the substrate 1 is a Si / SiO2 substrate. In this step, the substrate 1 is cleaned, for example, the substrate 1 is placed in acetone, anhydrous ethanol, and deionized water for ultrasonic cleaning for 1 minute to 5 minutes, preferably 3 minutes, and then the substrate 1 is dried, for example, by blowing it dry with a nitrogen gun.

[0119] S2.3, forming a source-drain electrode layer 7 on the substrate 1.

[0120] Specifically, in this step, the substrate 1 is patterned using electron beam exposure technology or photolithography technology, and then the source and drain electrode layer 7, such as metal chromium / gold (Cr / Au), is sputtered on the surface of the substrate 1 using magnetron sputtering technology. The thickness of the source and drain electrode layer 7 is in the range of tens of nanometers to hundreds of nanometers, for example, 10nm or 50nm. Of course, the source and drain electrode layer 7 can also be formed by thermal evaporation process, wherein the deposition rate of Cr and Au can be and Of course, those skilled in the art will appreciate that the material of the source-drain electrode layer 7 may also be one or more of other types of metals, conductive metal oxides, or conductive metal nitride materials.

[0121] S3.3, forming a semiconductor layer 6 on the source-drain electrode layer 7.

[0122] Specifically, in this step, a mechanical lift-off transfer process is used to deposit a semiconductor layer 6, such as MoTe2, on the source / drain electrode layer 7. Of course, other bipolar two-dimensional semiconductor materials or organic semiconductors can also be used. The transferred two-dimensional material has a thickness ranging from a few nanometers to more than ten nanometers. For example, a magnetron sputtering process can be used to deposit a metal oxide as the semiconductor layer 6 on the source / drain electrode layer 7. Alternatively, the semiconductor layer 6 can be formed by spin coating or evaporating an organic semiconductor.

[0123] S4.3, forming an insulating layer 5 on the semiconductor layer 6.

[0124] Specifically, in this step, an atomic layer deposition (ALD) process is used to form an insulating layer 5 on the semiconductor layer 6. The insulating layer 5 is made of an oxide material. In this embodiment, the insulating layer 5 is made of an aluminum oxide film, but may also be made of other oxide materials such as hafnium oxide or zirconium oxide. The thickness of the insulating layer 5 is in the range of 5 nm to 15 nm, for example, 10 nm. Of course, this is not limiting, and a mechanical lift-off transfer process may also be used to form a two-dimensional material such as BN on the semiconductor layer 6.

[0125] S5.3, forming a double floating gate layer 4 on the insulating layer 5.

[0126] Specifically, in this step, photoresist is first spin-coated on the insulating layer 5. Electron beam lithography or photolithography is then used to pattern the layer into columns with widths ranging from several hundred nanometers to several micrometers. Magnetron sputtering is then used to deposit a layer of tungsten (W) onto the surface of the insulating layer 5 as the dual floating gate layer 4. This is not limiting and other metals, conductive metal oxides, or conductive metal nitrides may also be used. Alternatively, thermal evaporation or electron beam evaporation may be used to form the dual floating gate layer 4 on the surface of the insulating layer 5.

[0127] S6.3, forming a ferroelectric layer 3 on the double floating gate layer 4.

[0128] Specifically, in this step, the organic ferroelectric is formed by spin coating. Specifically, for example, a ferroelectric polymer P(VDF-TrFE) (70:30 mol%) is dissolved in diethyl carbonate to prepare a spin coating solution with a concentration of 2.5 wt%. The spin coating solution is spin-coated on the double floating gate layer 4, and then thermally annealed at 135° C. for 1 hour to promote the growth of the ferroelectric β phase to form the ferroelectric layer 3. The thickness of the formed ferroelectric layer 3 is 100 nm.

[0129] S7.3, forming a gate electrode layer 2 on the ferroelectric layer 3.

[0130] Specifically, in this step, the ferroelectric layer 3 is patterned using an electron beam exposure process or a photolithography technique, and then a layer of metal tungsten (W) is sputtered on the surface of the ferroelectric layer 3 using a magnetron sputtering technique as the gate electrode layer 2. Of course, this is not limited to this, and other types of metals, conductive metal oxides or conductive metal nitride materials can also be used. In this embodiment, the sputtering power during the sputtering process is 100W, the sputtering time is 2min, and the thickness of the gate electrode layer 2 is 40nm. In addition, the gate electrode layer 2 can also be formed by a thermal evaporation process, wherein the deposition rate of the gate electrode layer 2 during the thermal evaporation process is The gate electrode layer 2 may also be formed on the ferroelectric layer 3 by electron beam evaporation.

[0131] Finally, the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as described in Example 3 is obtained. This method is easy to operate, low in cost, and easy to achieve large-area preparation.

[0132] Example 4

[0133] See Figure 9 The difference between this embodiment and the third embodiment is that the positions of the ferroelectric layer 3 and the insulating layer 5 are different.

[0134] Specifically, in this embodiment, the substrate 1, the source-drain electrode layer 7, the semiconductor layer 6, the ferroelectric layer 3, the double floating gate layer 4, the insulating layer 5 and the gate electrode layer 2 are stacked in sequence from bottom to top, that is, the source-drain electrode layer 7 is configured on the substrate 1, the semiconductor layer 6 is configured on the source-drain electrode layer 7, the ferroelectric layer 3 is configured on the semiconductor layer 6, the double floating gate layer 4 is configured on the ferroelectric layer 3, the insulating layer 5 is configured on the double floating gate layer 4, and the gate electrode layer 2 is configured on the insulating layer 5.

[0135] In addition, the materials used for the substrate 1 , the gate electrode layer 2 , the ferroelectric layer 3 , the double floating gate layer 4 , the insulating layer 5 , the semiconductor layer 6 and the source-drain electrode layer 7 are the same as those of the third embodiment.

[0136] This embodiment introduces a split double floating gate layer 4 structure that does not require external connection. By applying voltage at both ends of the source and drain electrode layer 7, it is also possible to achieve electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6, thereby realizing the regulation of the pn junction or np junction, and further realizing programmable positive and negative photoelectric responses, thereby reducing the external connection ports of the device and the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved. At the same time, the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics.

[0137] See Figure 10 This embodiment provides a method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, including steps S1.4 to S7.4.

[0138] S1.4, provide a substrate 1.

[0139] Specifically, the substrate 1 is a Si / SiO2 substrate. In this step, the substrate 1 is cleaned, for example, the substrate 1 is placed in acetone, anhydrous ethanol, and deionized water for ultrasonic cleaning for 1 minute to 5 minutes, preferably 3 minutes, and then the substrate 1 is dried, for example, by blowing it dry with a nitrogen gun.

[0140] S2.4, forming a source-drain electrode layer 7 on the substrate 1.

[0141] Specifically, in this step, the substrate 1 is patterned using electron beam exposure technology or photolithography technology, and then the source and drain electrode layer 7, such as metal chromium / gold (Cr / Au), is sputtered on the surface of the substrate 1 using magnetron sputtering technology. The thickness of the source and drain electrode layer 7 is in the range of tens of nanometers to hundreds of nanometers, for example, 10nm or 50nm. Of course, the source and drain electrode layer 7 can also be formed by thermal evaporation process, wherein the deposition rate of Cr and Au can be and Of course, those skilled in the art will appreciate that the material of the source-drain electrode layer 7 may also be one or more of other types of metals, conductive metal oxides, or conductive metal nitride materials.

[0142] S3.4, forming a semiconductor layer 6 on the source-drain electrode layer 7.

[0143] Specifically, in this step, a mechanical stripping transfer process is used to deposit a semiconductor layer 6, such as MoTe2, on the source-drain electrode layer 7. Of course, other bipolar two-dimensional semiconductor materials or organic semiconductors can also be used. The transfer thickness of the two-dimensional material is a few nanometers to more than ten nanometers. For example, a magnetron sputtering process can be used to deposit a layer of metal oxide on the source-drain electrode layer 7 as the semiconductor layer 6; or a spin coating or evaporation deposition of an organic semiconductor can be used to form the semiconductor layer 6.

[0144] S4.4, forming a ferroelectric layer 3 on the semiconductor layer 6.

[0145] In this step, the organic ferroelectric is formed by spin coating. Specifically, P(VDF-TrFE) (70:30 mol%) ferroelectric polymer is dissolved in diethyl carbonate to prepare a spin coating solution with a concentration of 2.5 wt%. The spin coating solution is spin-coated on the semiconductor layer 6, and then thermally annealed at 135° C. for 1 hour to promote the growth of the ferroelectric β phase to form the ferroelectric layer 3. The thickness of the formed ferroelectric layer 3 is 100 nm.

[0146] S5.4, forming a double floating gate layer 4 on the ferroelectric layer 3.

[0147] Specifically, in this step, photoresist is first spin-coated on the ferroelectric layer 3. Electron beam lithography or photolithography is then used to pattern the layer into columns with widths ranging from several hundred nanometers to several micrometers. Magnetron sputtering is then used to deposit a layer of tungsten (W) onto the surface of the ferroelectric layer 3 as the dual floating gate layer 4. This is not limiting and other metals, conductive metal oxides, or conductive metal nitrides may also be used. Alternatively, thermal evaporation or electron beam evaporation may be used to form the dual floating gate layer 4 on the surface of the ferroelectric layer 3.

[0148] S6.4, forming an insulating layer 5 on the double floating gate layer 4.

[0149] Specifically, in this step, an atomic layer deposition (ALD) process is used to form an insulating layer 5 on the dual floating gate layer 4. The insulating layer 5 is made of an oxide material. In this embodiment, the insulating layer 5 is made of an aluminum oxide thin film, but can also be made of other oxide materials such as hafnium oxide or zirconium oxide. The thickness of the insulating layer 5 ranges from 5 nm to 15 nm, for example, 10 nm. Of course, this is not limiting. A mechanical lift-off transfer process can also be used to form a two-dimensional material such as BN on the dual floating gate layer 4.

[0150] S7.4, forming a gate electrode layer 2 on the insulating layer 5.

[0151] Specifically, in this step, the insulating layer 5 is patterned by electron beam exposure process or photolithography technology, and then a layer of metal tungsten (W) is sputtered on the surface of the insulating layer 5 by magnetron sputtering technology as the gate electrode layer 2. Of course, it is not limited to this, and other types of metals, conductive metal oxides or conductive metal nitride materials can also be used. In this embodiment, the sputtering power during the sputtering process is 100W, the sputtering time is 2min, and the thickness of the gate electrode layer 2 is 40nm. In addition, the gate electrode layer 2 can also be formed by a thermal evaporation process, wherein the gate electrode layer 2 deposition rate during the thermal evaporation process is The gate electrode layer 2 may also be formed on the insulating layer 5 by using an electron beam evaporation process.

[0152] Finally, the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as described in Example 4 is obtained. This method is easy to operate, low in cost, and easy to achieve large-area preparation.

[0153] In other embodiments of the present invention, the manufacturing order of the source-drain electrode layer 7 and the semiconductor layer 6 can also be exchanged, that is, the semiconductor layer 6 is first formed on the substrate 1, and then the source-drain electrode layer 7 and the ferroelectric layer 3 are formed in sequence on the semiconductor layer 6. Similarly, a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials can be obtained.

[0154] Example 5

[0155] See Figure 11 The difference between this embodiment and the first embodiment is that the positions of the semiconductor layer 6 and the source-drain electrode layer 7 are swapped.

[0156] Specifically, in this embodiment, the substrate 1, the gate electrode layer 2, the ferroelectric layer 3, the double floating gate layer 4, the insulating layer 5, the source-drain electrode layer 7 and the semiconductor layer 6 are stacked in sequence from bottom to top, that is, the gate electrode layer 2 is formed on the substrate 1, the ferroelectric layer 3 is formed on the gate electrode layer 2, the double floating gate layer 4 is formed on the ferroelectric layer 3, the insulating layer 5 is formed on the double floating gate layer 4, the source-drain electrode layer 7 is formed on the insulating layer 5, and the semiconductor layer 6 is formed on the source-drain electrode layer 7.

[0157] The materials used in this embodiment are the same as those in the first embodiment in terms of the substrate 1 , the gate electrode layer 2 , the insulating layer 5 , the double floating gate layer 4 , the ferroelectric layer 3 , the semiconductor layer 6 and the source-drain electrode layer 7 .

[0158] like Figure 12 As shown, accordingly, the method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials in this embodiment is different from that in the first embodiment only in that the order of forming the semiconductor layer 6 and the source-drain electrode layer 7 is swapped.

[0159] This embodiment introduces a split double floating gate layer 4 structure that does not require external connection. By applying voltage at both ends of the source and drain electrode layer 7, the electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6 can also be achieved, which can realize the regulation of the pn junction or np junction, and further realize programmable positive and negative photoelectric response, thereby reducing the external connection ports of the device and reducing the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved, and the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics. At the same time, the preparation method of the reconfigurable homogeneous pn junction device at both ends based on ferroelectric materials is easy to operate, low in cost, and easy to achieve large-area preparation.

[0160] Example 6

[0161] See Figure 13 The difference between this embodiment and the third embodiment is that the positions of the semiconductor layer 6 and the source-drain electrode layer 7 are swapped.

[0162] Specifically, in this embodiment, the substrate 1, the semiconductor layer 6, the source-drain electrode layer 7, the insulating layer 5, the double floating gate layer 4, the ferroelectric layer 3 and the gate electrode layer 2 are stacked in sequence from bottom to top, that is, the semiconductor layer 6 is formed on the substrate 1, the source-drain electrode layer 7 is formed on the semiconductor layer 6, the insulating layer 5 is formed on the source-drain electrode layer 7, the double floating gate layer 4 is formed on the insulating layer 5, the ferroelectric layer 3 is formed on the double floating gate layer 4, and the gate electrode layer 2 is formed on the ferroelectric layer 3.

[0163] In addition, the materials used for the substrate 1 , the gate electrode layer 2 , the ferroelectric layer 3 , the double floating gate layer 4 , the insulating layer 5 , the semiconductor layer 6 and the source-drain electrode layer 7 are the same as those of the third embodiment.

[0164] like Figure 14 As shown, accordingly, the method for preparing the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material in this embodiment is different from that in the third embodiment only in that the order of forming the semiconductor layer 6 and the source-drain electrode layer 7 is swapped.

[0165] This embodiment introduces a split double floating gate layer 4 structure that does not require external connection. By applying voltage at both ends of the source and drain electrode layer 7, the electrostatic doping of the ferroelectric layer 3 to the semiconductor layer 6 can also be achieved, which can realize the regulation of the pn junction or np junction, and further realize programmable positive and negative photoelectric response, thereby reducing the external connection ports of the device and reducing the complexity of the peripheral circuit. In terms of constructing an integrated sensing, storage and computing device, the integration of the device is improved, and the introduction of the double floating gate layer 4 also helps to enhance its retention characteristics. At the same time, the preparation method of the reconfigurable homogeneous pn junction device at both ends based on ferroelectric materials is easy to operate, low in cost, and easy to achieve large-area preparation.

[0166] In the above description, many specific details are set forth in order to fully understand the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material, characterized in that: include: A substrate (1), a gate electrode layer (2), a ferroelectric layer (3), a double floating gate layer (4), an insulating layer (5), a semiconductor layer (6), and a source-drain electrode layer (7) arranged adjacent to the semiconductor layer (6), wherein one of the ferroelectric layer (3) and the insulating layer (5) is formed between the gate electrode layer (2) and the double floating gate layer (4), and the other of the ferroelectric layer (3) and the insulating layer (5) is formed between the semiconductor layer (6) and the double floating gate layer (4); the gate electrode layer (2), the semiconductor layer (6), or the source-drain electrode layer (7) is formed on the substrate (1); wherein a separation groove is provided in the middle of the double floating gate layer (4) to split itself into two parts; when positive and negative voltages are applied to both ends of the source-drain electrode layer (7), the ferroelectric layer (3) can electrostatically dope the semiconductor layer (6), thereby adjusting the polarity of the semiconductor layer (6) to form a pn junction or an np junction.

2. The two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material according to claim 1, characterized in that: The materials of the gate electrode layer (2) and the source-drain electrode layer (7) are one or more of metals, conductive metal oxides, and conductive metal nitrides.

3. The two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material according to claim 1, characterized in that: The material of the ferroelectric layer (3) is a ferroelectric material.

4. The two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material according to claim 1, characterized in that: The material of the double floating gate layer (4) is one or more of metal, conductive metal oxide, and conductive metal nitride.

5. The two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material according to claim 1, characterized in that: The material of the insulating layer (5) is oxide or two-dimensional insulating material, and the thickness of the insulating layer (5) is from several nanometers to more than ten nanometers.

6. The two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material according to claim 1, characterized in that: The material of the semiconductor layer (6) is a two-dimensional semiconductor, a metal oxide or an organic semiconductor.

7. A method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, characterized in that: The following steps are involved: providing a substrate (1); forming a gate electrode layer (2) on the substrate (1); A ferroelectric layer (3) is formed on the gate electrode layer (2); wherein the material of the ferroelectric layer (3) is hafnium-based ferroelectric, lead zirconate titanate, barium titanate, bismuth ferrite or a two-dimensional ferroelectric material; forming a split double floating gate layer (4) on the ferroelectric layer (3); forming an insulating layer (5) on the double floating gate layer (4); A semiconductor layer (6) and a source-drain electrode layer (7) are sequentially formed on the insulating layer (5), or a source-drain electrode layer (7) and a semiconductor layer (6) are sequentially formed on the insulating layer (5), thereby obtaining a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as claimed in claim 1.

8. A method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, characterized in that: The following steps are involved: providing a substrate (1); forming a gate electrode layer (2) on the substrate (1); forming an insulating layer (5) on the gate electrode layer (2); forming a split double floating gate layer (4) on the insulating layer (5); A ferroelectric layer (3) is formed on the double floating gate layer (4); wherein the material of the ferroelectric layer (3) is hafnium-based ferroelectric, lead zirconate titanate, barium titanate, bismuth ferrite or a two-dimensional ferroelectric material; A semiconductor layer (6) and a source-drain electrode layer (7) are sequentially formed on the ferroelectric layer (3), or a source-drain electrode layer (7) and a semiconductor layer (6) are sequentially formed on the ferroelectric layer (3), thereby obtaining a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as claimed in claim 1.

9. A method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, characterized in that: The following steps are involved: providing a substrate (1); A source-drain electrode layer (7), a semiconductor layer (6), and an insulating layer (5) are sequentially formed on the substrate (1), or a semiconductor layer (6), a source-drain electrode layer (7), and an insulating layer (5) are sequentially formed on the substrate (1), forming a split double floating gate layer (4) on the insulating layer (5); A ferroelectric layer (3) is formed on the double floating gate layer (4); wherein the material of the ferroelectric layer (3) is organic ferroelectric or molecular ferroelectric; A gate electrode layer (2) is formed on the ferroelectric layer (3), thereby producing the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as claimed in claim 1.

10. A method for preparing a two-terminal reconfigurable homogeneous pn junction device based on ferroelectric materials, characterized in that: The following steps are involved: providing a substrate (1); A source-drain electrode layer (7), a semiconductor layer (6), and a ferroelectric layer (3) are sequentially formed on the substrate (1), or a semiconductor layer (6), a source-drain electrode layer (7), and a ferroelectric layer (3) are sequentially formed on the substrate (1); wherein the material of the ferroelectric layer (3) is organic ferroelectric or molecular ferroelectric; forming a split double floating gate layer (4) on the ferroelectric layer (3); forming an insulating layer (5) on the double floating gate layer (4); A gate electrode layer (2) is formed on the surface of the insulating layer (5), thereby producing the two-terminal reconfigurable homogeneous pn junction device based on ferroelectric material as claimed in claim 1.

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