Power semiconductor module device and manufacturing method thereof

Abstract

The invention relates to a power semiconductor module device and a manufacturing method thereof. A semiconductor module apparatus includes a substrate including a dielectric insulating layer and a metallization layer disposed on a first side of the dielectric insulating layer; a substrate; and a connection layer, where the connection layer is disposed between the substrate and the substrate and attaches the substrate to the substrate, the connection layer directly adjoins the substrate and a second side of the dielectric insulating layer opposite to the first side, and the connection layer includes a sintering paste and an adhesion enhancer.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor module arrangement and a method for producing such a power semiconductor module arrangement. Background Art

[0002] A power semiconductor module device typically includes at least one substrate. A semiconductor arrangement (semiconductor arrangement) including a plurality of controllable semiconductor elements (e.g., two or more IGBTs) is arranged on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are, for example, mounted on the first metallization layer. At least some of the controllable semiconductor elements of the power semiconductor module device perform multiple switching operations during operation of the power semiconductor module device. For example, when many switching operations are performed in a short period of time, the controllable semiconductor elements generate heat. Most of the heat generated during operation of the power semiconductor module device is dissipated from the controllable semiconductor elements to the substrate, and further dissipated through the base plate to a heat sink.

[0003] There is a need for a power semiconductor module arrangement in which heat can be efficiently conducted away from semiconductor elements and which can be manufactured at low cost. Summary of the Invention

[0004] A power semiconductor module device includes: a substrate including a dielectric insulating layer and a metallization layer arranged on a first side of the dielectric insulating layer; a base plate; and a connection layer, wherein the connection layer is arranged between the substrate and the base plate and attaches the substrate to the base plate, the connection layer directly adjoins the base plate and a second side of the dielectric insulating layer opposite to the first side, and the connection layer includes a sintering paste and an adhesion promoter.

[0005] A method includes forming a connection layer; arranging a substrate on a base plate, wherein the connection layer is arranged between the substrate and the base plate; and performing a sintering process to connect the substrate to the base plate through the connection layer, wherein the substrate includes a dielectric insulating layer and a metallization layer arranged on a first side of the dielectric insulating layer, when the substrate is arranged on the base plate, the connection layer directly abuts the base plate and a second side of the dielectric insulating layer opposite the first side, and the connection layer includes a sintering paste and an adhesion enhancer

[0006] The present invention may be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, like reference numerals represent corresponding components in different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view of a power semiconductor module device.

[0008] Figure 2 is a cross-sectional view of a power semiconductor module device according to an embodiment of the present disclosure.

[0009] Figure 3 is a top view of a base plate with a substrate mounted thereon.

[0010] Figure 4 is a top view of a base plate with two substrates mounted thereon.

[0011] Figure 5 is a top view of a base plate on which four substrates are mounted.

[0012] Figure 6 is a cross-sectional view of a power semiconductor module device according to an embodiment of the present disclosure.

[0013] Figure 7 is a cross-sectional view of a power semiconductor module device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that, unless otherwise specifically stated, the features and principles described with respect to the various examples can be combined with each other. In the specification and in the claims, naming certain elements as "first element", "second element", "third element", etc. should not be understood as enumeration. Instead, these names are only used to refer to different "elements". That is, for example, the presence of a "third element" does not necessarily require the presence of a "first element" and a "second element". The wires or electrical connections described herein can be a single conductive element, or can include at least two separate conductive elements connected in series and / or in parallel. The wires and electrical connections can include metal and / or semiconductor materials and can be permanently conductive (i.e., non-switchable). The semiconductor body described herein can be made of (doped) semiconductor material and can be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrically connectable pads and includes at least one semiconductor element having electrodes.

[0015] refer to Figure 1, shows a cross-sectional view of a conventional power semiconductor module device (which is simply referred to as a semiconductor module) 100. Power semiconductor module device 100 includes a housing 7 and a substrate 10. Substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to dielectric insulating layer 11. Dielectric insulating layer 11 is provided between first metallization layer 111 and second metallization layer 112.

[0016] Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; or any other metal or alloy that remains solid during operation of the power semiconductor module device 100. The substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. Alternatively, the dielectric insulating layer 11 may be composed of an organic compound and include one or more of the following materials: Al2O3, AlN, ZrO2, SiC, BeO, BN, or Si3N4. For example, the substrate 10 may be a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. Furthermore, the substrate 10 may be an insulated metal substrate (IMS). The insulated metal substrate typically includes a dielectric insulating layer 11, which includes, for example, a (filling) material such as epoxy or polyimide. For example, the material of the dielectric insulating layer 11 can be filled with ceramic particles. Such particles can include, for example, SiO2, Al2O3, AlN, SiN, or BN, and can have a diameter between about 1 μm and about 50 μm.

[0017] The substrate 10 is arranged in the housing 7. Figure 1 In the example shown, substrate 10 is arranged on baseplate 80, which forms the base surface of housing 7. Housing 7 itself comprises only sidewalls and, optionally, a roof or lid. In some power semiconductor module arrangements 100, more than one substrate 10 is arranged on the same baseplate 80 and within the same housing 7. Baseplate 80 may comprise a layer of metallic material, such as, for example, AlSiC, AlC, Al, MgSiC, or Cu. However, other materials are generally possible.

[0018] One or more semiconductor bodies 20 may be arranged on at least one substrate 10. Each semiconductor body 20 arranged on at least one substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

[0019] One or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. Figure 1 In FIG, only two semiconductor bodies 20 are shown by way of example. Figure 1 The second metallization layer 112 of the substrate 10 is a continuous layer. In some semiconductor modules 100, the second metallization layer 112 may be a structured layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. In this context, "structured layer" means that the corresponding metallization layer is not a continuous layer, but includes recesses between different parts of the layer. Such recesses are Figure 1 . In this example, the first metallization layer 111 includes three different parts. Different semiconductor bodies 20 can be mounted to the same or different parts of the first metallization layer 111. Different parts of the first metallization layer 111 can have no electrical connection, or can be electrically connected to one or more other parts using electrical connections 3 (e.g., bonding wires, for example). For example, the semiconductor bodies 20 can be electrically connected to each other or to the first metallization layer 111 using electrical connections 3. Instead of bonding wires, the electrical connections 3 can also include, for example, bonding ribbons, connecting pads, or conductor tracks, to name a few examples. One or more semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 via a conductive connection layer 60. For example, such a conductive connection layer 60 can be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver (Ag) powder) layer. One or more substrates 10 can be mechanically and thermally connected to the base plate 80 via a connection layer 62. The connection layer 62 in a conventional semiconductor module 100 can be an electrically insulating adhesive layer, a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver (Ag) powder) layer.

[0020] Figure 1 The power semiconductor module arrangement 100 shown further comprises a terminal element 4. The terminal element 4 provides an electrical connection between the interior and the exterior of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 via a second end 42, while a first end 41 of the terminal element 4 protrudes outside the housing 7. The terminal element 4 can be electrically contacted from the outside at the first end 41 of the terminal element 4.

[0021] Arranging the terminal element 4 centrally on the substrate 10 is only one example. According to other examples, the terminal element 4 may be arranged closer to or adjacent to the side wall of the housing 7. The second end 42 of the terminal element 4 may be connected to the conductive connecting layer (at the bottom of the housing 7). Figure 1 The terminal element 4 is electrically and mechanically connected to the substrate 10 (not specifically shown). This conductive connection layer can be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver (Ag) powder) layer. Alternatively, the terminal element 4 can also be coupled to the substrate by ultrasonic welding.

[0022] The power semiconductor module device 100 may further include an encapsulant 5. For example, the encapsulant 5 may be composed of or include a cured silicone gel, or may be a rigid molding compound. The encapsulant 5 may at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the substrate 10. The terminal elements 4 may be partially embedded in the encapsulant 5. However, at least their first ends 41 are not covered by the encapsulant 5 and extend from the encapsulant 5 through the housing 7 to the outside of the housing 7. The encapsulant 5 is configured to protect the components and electrical connections of the power semiconductor module 100 (particularly the components arranged inside the housing 7) from certain environmental conditions and mechanical damage. The encapsulant 5 is also configured to electrically insulate regions with different electrical potentials (e.g., different portions of the first metallization layer 111) from each other.

[0023] The second metallization layer 112 of the substrate 10 is generally not required for the overall functionality of the semiconductor module 100. That is, the second metallization layer 112 generally does not conduct any current during operation of the semiconductor module 100. Therefore, the second metallization layer 112 can generally be omitted entirely. However, it is not possible to directly attach the dielectric insulation layer 11 of the substrate 10 to the base plate 80 using conventional sintering pastes. Nevertheless, omitting the second metallization layer reduces the overall cost of the semiconductor module 100. Furthermore, by omitting the second metallization layer 112, the overall thermal resistance (Rth) of the stack formed by the substrate 10 and the base plate 80 can be reduced, and heat can be conducted more efficiently from the semiconductor body 20 to the base plate 80.

[0024] Now refer to Figure 2, a semiconductor module device 100 according to an embodiment of the present disclosure includes a substrate 10, which includes a dielectric insulating layer 11 and a metallization layer 111 arranged on a first side of the dielectric insulating layer 11. However, the substrate 10 does not include a second metallization layer 112. The semiconductor module 100 also includes a base plate 80 and a connection layer 64. The connection layer 64 is arranged between the substrate 10 and the base plate 80 and attaches the substrate 10 to the base plate 80. Since the substrate 10 does not include the second metallization layer 112, the connection layer 64 directly adjoins the base plate 80 and the second side of the dielectric insulating layer 11 opposite to the first side. The connection layer 64 includes a sintering paste 642 and an adhesion enhancer 644 (see, for example Figure 6 and Figure 7 Due to the adhesion enhancer 644 , the connection layer 64 adheres not only to the base plate 80 but also to the dielectric insulating layer 11 of the substrate 10 .

[0025] As previously described, dielectric insulating layer 11 may be made of or include one of the following materials: Al2O3; AlN; ZrO2; SiC; BeO; BN; or Si3N4. Substrate 80 may be made of or include one of the following materials: AlSiC, AlC, Al, MgSiC, or Cu. Sintering paste 642 may include, for example, at least one of copper and silver, and adhesion enhancer 644 may include, for example, titanium, chromium, or vanadium (e.g., vanadium nanoparticles) or be made of, for example, titanium, chromium, or vanadium (e.g., vanadium nanoparticles).

[0026] According to some embodiments, an adhesion enhancer 644 may be distributed within the frit paste 642. Figure 6 is schematically shown in FIG. Figure 6A cross-sectional view of a semiconductor module including a base plate 80, a substrate 10, and a connecting layer 64 is schematically shown. A portion of the connecting layer 64 is shown in an enlarged view to illustrate the adhesion enhancer 644 distributed within the sinter paste 642. To produce the connecting layer 64, the sinter paste 642 and the adhesion enhancer 644 can be mixed together. When mixed into the sinter paste 642, the adhesion enhancer 644 also exists on the surface of the connecting layer 64. When the substrate 10 is placed on the base plate 80 with the connecting layer 64 arranged therebetween, and a sintering process is performed, the adhesion enhancer 644 on the surface of the connecting layer 64 reacts with the base plate 80 and the dielectric insulating layer 11 of the substrate 10. In this way, the substrate 10 can be permanently connected to the base plate 80 even without the second metallization layer 112. After mixing the sinter paste 642 and the adhesion enhancer 644, the connecting layer 64 can be formed on the surface of the substrate 80, and then the substrate 10 can be placed on the connecting layer 64. However, it is also possible to form the connection layer 64 on the substrate (ie, on the second side of the dielectric insulating layer 11 ), and arrange the substrate 10 with the connection layer 64 formed thereon on the base plate 80 .

[0027] However, instead of distributing the adhesion enhancer 644 within the frit paste 642, the connecting layer 64 may also include a first sublayer consisting of the adhesion enhancer 644, a second sublayer consisting of the frit paste 642, and a third sublayer consisting of the adhesion enhancer 644, wherein the first sublayer is arranged so that it directly adjoins the substrate 80, the third sublayer is arranged so that it directly adjoins the dielectric insulating layer 11, and the second sublayer is arranged between the first sublayer and the third sublayer and directly adjoins the first sublayer and the third sublayer. Figure 7 is schematically shown in Figure 7 Schematically shown is a cross-sectional view of a semiconductor module comprising a base plate 80, a substrate 10 and a connection layer 64. In order to illustrate the first, second and third sub-layers, a part of the connection layer 64 is shown in an enlarged view.

[0028] The connection layer 64 comprising different sublayers can be formed in any suitable manner. According to one example, the connection layer 64 can be formed by forming a second sublayer consisting of a sinter paste, forming a first sublayer consisting of an adhesion enhancer on the first surface of the second sublayer, and forming a third sublayer consisting of an adhesion enhancer on the second surface of the second sublayer opposite to the first surface. The connection layer 64 comprising the first sublayer, the second sublayer and the third sublayer can then be arranged between the substrate 10 and the base plate 80 (for example, as a prefabricated foil). According to another example, the first sublayer is formed on the base plate 80, and the second sublayer is subsequently formed on the first sublayer. The third sublayer can then be formed on the second sublayer, thereby forming a layer stack (connection layer 64) comprising the first sublayer, the second sublayer and the third sublayer on the base plate 80. Alternatively, the layer stack (connection layer 64) can be formed on the dielectric insulating layer 11, and the substrate 10 on which the connection layer 64 is formed can then be arranged on the base plate 80. According to a further example, the first sublayer may be formed on the substrate 80, and the third sublayer may be formed on the substrate 10. In this example, the second sublayer may be formed on the first sublayer or the third sublayer before the substrate 10 is disposed on the substrate 80. That is, when the substrate 10 is disposed on the substrate 80, the formation of the connection layer 64 including the first sublayer, the second sublayer, and the third sublayer is completed.

[0029] According to yet another example, insulating layer 11 may be composed of two sub-layers. In this example, the first sub-layer includes an adhesion enhancer 644, and the second sub-layer includes a sinter paste 642. In some cases, depending on the material from which substrate 80 is made, the sub-layer of sinter paste 642 may establish a strong bond with substrate 80, eliminating the need for a third sub-layer of adhesion enhancer 644. For example, when using a copper substrate 80, a third sub-layer of adhesion enhancer 644 may not be required.

[0030] The substrate 10 and the base plate 80 generally have different coefficients of thermal expansion (CTE). The dielectric insulating layer 11 composed of AlN has a CTE of about 4×10 -6 ℃ -1 The substrate 80 made of Cu has a CTE of about 17×10 -6 ℃ -1 Generally speaking, the dielectric insulating layer 11 has a first coefficient of thermal expansion (CTE1), and the substrate 80 has a second coefficient of thermal expansion (CTE2) different from CTE1. The connecting layer 64 may have a third coefficient of thermal expansion (CTE3), where CTE1 < CTE3 < CTE2. For example, the connecting layer 64 may have a CTE of 4×10 -6 ℃ -1 and 17×10 -6 ℃ -1The CTE3 of the connecting layer 64 depends on the specific composition of the connecting layer 64. That is, by using different materials for the frit paste 642 and the adhesion enhancer 644, and by using different frit paste 642 / adhesion enhancer 644 ratios, the CTE3 of the resulting connecting layer 64 can be individually adjusted.

[0031] Generally, any size of substrate 10 can be used in the semiconductor modules described herein. In some semiconductor modules 100, only one (exactly one / no more than one) substrate 10 is arranged on the base plate 80. Figure 3 In other semiconductor modules 100 , more than one substrate 10 may be arranged on a single base plate 80 . Figure 4 Schematically shows a semiconductor module comprising two substrates 10 arranged on a base plate 80, and Figure 5 Schematically shown in FIG is a semiconductor module 100 comprising four substrates 10 arranged on a base plate 80. Any other number of substrates 10 on the base plate 80 is generally possible. Figure 3 、 Figure 4 and Figure 5 Each of the one or more substrates 10 shown in has a rectangular shape. However, other shapes are also generally possible. For example, the substrate 10 may also have rounded corners. Each of the one or more substrates 10 has a width A in a first horizontal direction and a length B in a second horizontal direction perpendicular to the first horizontal direction. The one or more substrates 10 arranged on the substrate 80 can be a relatively large substrate 10, for example, having a width A of at least 30 mm and a length B of at least 40 mm. The advantages of mounting the dielectric insulating layer 11 directly to the substrate 80 and omitting the second metallization layer 112 (improved Rth, reducing the thickness of the layer stack formed by the substrate 10, the connecting layer 64 and the substrate 80, and reducing the overall cost of the semiconductor module) become more apparent for larger substrates 10. However, smaller substrates 10 may also generally be arranged on the substrate 80 in the manner described above.

[0032] The method according to an embodiment of the present disclosure includes: forming a connecting layer 64; arranging a substrate 10 on a base plate 80, wherein the connecting layer 64 is arranged between the substrate 10 and the base plate 80; and performing a sintering process to attach the substrate 10 to the base plate 80 through the connecting layer 64, wherein the substrate 10 includes a dielectric insulating layer 11 and a metallization layer 111 arranged on a first side of the dielectric insulating layer 11, wherein when the substrate 10 is arranged on the base plate 80, the connecting layer 64 is directly adjacent to the base plate 80 and a second side of the dielectric insulating layer 11 opposite to the first side, and the connecting layer 64 includes a sintering paste 642 and an adhesion enhancer 644.

[0033] Forming connection layer 64 may include mixing frit paste 642 with adhesion enhancer 644. After frit paste 642 and adhesion enhancer 644 are mixed, connection layer 64 may be formed on the surface of substrate 80 or on the second side of dielectric insulation layer 11.

[0034] Alternatively, forming the connection layer 64 may include forming a second sublayer composed of sinter paste 642 and forming a first sublayer composed of an adhesion enhancer 644 on a first surface of the second sublayer. Forming the connection layer 64 may also include forming a third sublayer on the second sublayer, such that the second sublayer is arranged between the first sublayer and the third sublayer. Regardless of whether the connection layer 64 includes two or three sublayers, the connection layer 64 in this example may be a prefabricated pad that can be arranged on the surface of the substrate 80 or on the surface of the dielectric insulating layer 11 before the substrate 10 is arranged on the base plate 80.

[0035] Alternatively, forming the connecting layer 64 may include: forming a sublayer consisting of sintering paste 642 on the substrate 80, and forming a sublayer consisting of adhesion enhancer 644 on the sublayer consisting of sintering paste 642 or on the dielectric insulating layer 11 of the substrate 10 (the connecting layer 64 includes two sublayers), or forming the connecting layer 64 may include: forming a sublayer consisting of adhesion enhancer 644 on the substrate 80, and then forming a sublayer consisting of sintering paste 642 on the sublayer consisting of adhesion enhancer 644, and forming another sublayer consisting of adhesion enhancer 644 on the sublayer consisting of sintering paste 642 or on the dielectric insulating layer 11 of the substrate 10 (the connecting layer 64 includes three sublayers).

Claims

1. A semiconductor module device, comprising: A substrate (10) comprising a dielectric insulating layer (11) and a metallization layer (111) arranged on a first side of the dielectric insulating layer (11); base(80); as well as A connection layer (64), wherein The connecting layer (64) is arranged between the substrate (10) and the base plate (80) and attaches the substrate (10) to the base plate (80), The connecting layer (64) directly abuts the substrate (80) and a second side of the dielectric insulating layer (11) opposite the first side, and The connecting layer (64) includes a frit paste (642) and an adhesion enhancer (644).

2. The semiconductor module device according to claim 1, wherein The adhesion enhancer (644) is distributed within the frit paste (642).

3. The semiconductor module device according to claim 1, wherein The connecting layer (64) comprises a first sublayer consisting of an adhesion enhancer (644) and a second sublayer consisting of a sintering paste (642), and wherein the first sublayer is arranged such that the first sublayer directly adjoins the dielectric insulating layer (11) and the second sublayer directly adjoins the first sublayer on a side opposite to the dielectric insulating layer (11).

4. The semiconductor module device according to claim 3, wherein: The connecting layer (64) further comprises a third sublayer composed of an adhesion enhancer (644), and wherein the third sublayer directly adjoins the second sublayer such that the second sublayer is arranged between the first sublayer and the third sublayer.

5. The semiconductor module arrangement according to any one of claims 1 to 4, wherein: The sintering paste (642) includes at least one of copper and silver.

6. The semiconductor module arrangement according to claim 1, wherein: The dielectric insulating layer (11) is made of or includes one of the following materials: Al2O3; AlN; ZrO2; SiC; BeO; BN; or Si3N4.

7. The semiconductor module arrangement according to claim 1, wherein: The substrate (80) is made of or includes one of the following materials: AlSiC, AlC, Al, MgSiC or Cu.

8. The semiconductor module arrangement according to claim 1, wherein The substrate (10) has a width (A) of at least 30 mm in a first horizontal direction; and The substrate (10) has a length (B) of at least 40 mm in a second horizontal direction perpendicular to the first horizontal direction.

9. The semiconductor module arrangement according to claim 1, wherein: The dielectric insulation layer (11) has a first thermal expansion coefficient, the substrate (80) has a second thermal expansion coefficient different from the first thermal expansion coefficient, and the connecting layer (64) has a third thermal expansion coefficient, and wherein the first thermal expansion coefficient is smaller than the third thermal expansion coefficient, and the third thermal expansion coefficient is smaller than the second thermal expansion coefficient.

10. The semiconductor module arrangement according to claim 1, wherein: The adhesion enhancer (644) includes or consists of titanium, chromium, or vanadium.

11. A method comprising: forming a connecting layer (64); Arranging a substrate (10) on a base plate (80), wherein the connecting layer (64) is arranged between the substrate (10) and the base plate (80); as well as A sintering process is performed to attach the substrate (10) to the base plate (80) via the connecting layer (64), wherein The substrate (10) comprises a dielectric insulating layer (11) and a metallization layer (111) arranged on a first side of the dielectric insulating layer (11), When the substrate (10) is arranged on the base plate (80), the connecting layer (64) directly abuts the base plate (80) and a second side of the dielectric insulating layer (11) opposite to the first side, and The connecting layer (64) includes a frit paste (642) and an adhesion enhancer (644).

12. The method according to claim 11, wherein Forming the connection layer (64) includes mixing the frit paste (642) with the adhesion enhancer (644).

13. The method according to claim 12, further comprising: After mixing the sintering paste (642) with the adhesion enhancer (644), forming the connection layer (64) on the surface of the substrate (80), or The connection layer (64) is formed on the second side of the dielectric insulation layer (11).

14. The method according to claim 11, wherein Forming the connection layer (64) includes forming a second sub-layer composed of a frit paste (642) and forming a first sub-layer composed of an adhesion enhancer (644) on a first surface of the second sub-layer.

15. The method according to claim 14, wherein Forming the connection layer (64) further includes forming a third sub-layer on the second sub-layer, such that the second sub-layer is arranged between the first sub-layer and the third sub-layer.

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