Voltage reference circuit and method for operating voltage reference circuit
Through the cross-coupled compensation branch structure, the cross-coupled third and fourth transistors are used to solve the problem of poor noise and offset performance of traditional voltage reference circuits, and a high-precision and low-power voltage reference circuit design is realized.
Patent Information
- Application Number
- CN202510797773.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-16
- Publication Date
- 2025-08-15
AI Technical Summary
Traditional voltage reference circuits have poor noise and/or offset performance in high-precision applications, resulting in increased circuit size or increased cost.
Using a cross-coupled compensation branch structure, including a cross-coupled third and fourth transistors, the noise compensation branch reduces the noise and offset of the operational amplifier, and reduces the number of transistors to maintain circuit performance.
Without increasing the circuit area, noise and offset are significantly reduced, the accuracy and stability of the voltage reference circuit are improved, and power consumption is reduced.
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Figure CN120491741A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate generally to integrated circuits, and more particularly to voltage reference circuits and methods for operating voltage reference circuits. Background Art
[0002] Voltage reference circuits are widely used in electronic devices to provide a fixed and stable DC voltage. Conventional voltage reference circuits typically include an operational amplifier and a compensation circuit connected to the two input terminals of the operational amplifier. The noise transfer function from the operational amplifier to the voltage output point is related to the circuit structure of the compensation circuit. For some high-precision application scenarios, conventional voltage reference circuits are unsatisfactory in terms of noise (e.g., flicker noise) and / or offset performance. In order to reduce noise and / or voltage offset, the size of the transistors in the voltage reference circuit can be increased or the number of mask layers of the chip can be increased, which inevitably leads to an increase in the size of the voltage reference circuit or an increase in cost. It is expected that the structure of the conventional voltage reference circuit can be improved to improve the performance of the voltage reference circuit. Summary of the Invention
[0003] The present disclosure provides a voltage reference circuit and a method for operating the voltage reference circuit, which aims to solve one or more of the above problems and other potential problems.
[0004] According to a first aspect of the present disclosure, a voltage reference circuit is provided. The voltage reference circuit includes: an operational amplifier including a first input terminal and a second input terminal; a first compensation branch, the first compensation branch including a first terminal connected to the first input terminal and a second terminal connected to a reference potential, the first compensation branch including at least one first transistor arranged between the first terminal and the second terminal, the base of each first transistor being connected to the collector of the first transistor, and the emitter of the first transistor being connected to the second terminal; and a second compensation branch, the second compensation branch including a third terminal connected to the second input terminal and a fourth terminal connected to the reference potential, the second compensation branch including At least one second triode is arranged between the third end and the fourth end, the base of each second triode is connected to the collector of the second triode, and the emitter of each second triode is connected to the fourth end; wherein at least one of the first compensation branch and the second compensation branch further includes a third compensation branch, the third compensation branch includes at least one third triode, the collector of each third triode is connected to the collector of one of the first triode and the second triode, and the base of each third triode is connected to the collector of the other of the first triode and the second triode.
[0005] In some embodiments, the second compensation branch includes the third compensation branch, the third compensation branch includes at least one third triode, the collector of each third triode is connected to the collector of the first triode, and the base of each third triode is connected to the collector of the second triode; and the first compensation branch includes a fourth compensation branch, the fourth compensation branch includes at least one fourth triode, the collector of each fourth triode is connected to the collector of the second triode, and the base of each fourth triode is connected to the collector of the first triode.
[0006] In some embodiments, the number of the second triodes is K times the number of the first triodes, the number of the fourth triodes is K times the number of the third triodes, and K is a natural number greater than 1.
[0007] In some embodiments, the number of the first transistors is N, the number of the third transistors is M, M and N are natural numbers not less than 1, and M is greater than N.
[0008] In some embodiments, the second compensation branch further includes a first resistor connected between the emitter of the fourth transistor and the fourth end of the second compensation branch.
[0009] In some embodiments, the first compensation branch further includes a second resistor connected between the collector of the third transistor and the collector of the first transistor; the second compensation branch further includes a third resistor connected between the base of the third transistor and the collector of the fourth transistor.
[0010] In some embodiments, the voltage reference circuit further includes a bias unit, which is configured to provide a bias current for the first compensation branch and the second compensation branch, and the bias unit includes a fourth resistor connected to the first input terminal and a fifth resistor connected to the second input terminal, and the other end of the fourth resistor and the other end of the fifth resistor are connected together and serve as an output end of the reference voltage.
[0011] In some embodiments, the voltage reference circuit further includes a MOS transistor, the gate of which is connected to the output of the operational amplifier, the source of which is connected to a power supply, and the drain of which is connected to the output end of the reference voltage.
[0012] According to a second aspect of the present disclosure, a method for operating the voltage reference circuit described in the first aspect is provided. The method comprises: providing, via the third compensation branch, a first noise compensation voltage at the collector of at least one of the first and second transistors, which is in phase with a voltage at the corresponding input terminal of the first and second input terminals, wherein the collector of the at least one transistor is connected to the corresponding input terminal; and compensating for noise transferred from the equivalent input noise voltage of the operational amplifier to the reference voltage using the first noise compensation voltage.
[0013] In some embodiments, the second compensation branch includes the third compensation branch, the third compensation branch includes at least one third triode, the collector of each of the third triode is connected to the collector of the first triode, and the base of each of the third triode is connected to the collector of the second triode; the third compensation branch includes a fourth compensation branch, the fourth compensation branch includes at least one fourth triode, the collector of each of the fourth triode is connected to the collector of the second triode, and the base of each of the fourth triode is connected to the collector of the first triode.
[0014] The method also includes: providing a first noise compensation voltage having a phase opposite to the voltage at the first input terminal at the collector of the fourth transistor through the fourth compensation branch; compensating for noise generated by the operational amplifier at the reference voltage through the first noise compensation voltage; providing a second noise compensation voltage having a phase opposite to the voltage at the second input terminal at the collector of the third transistor through the third compensation branch; and compensating for noise generated by the operational amplifier at the reference voltage through the second noise compensation voltage.
[0015] In some embodiments, the number of the second triodes is K times the number of the first triodes, the number of the fourth triodes is K times the number of the third triodes, K is a natural number greater than 1, wherein the number of the first triodes is N, the number of the third triodes is M, M and N are natural numbers not less than 1, and M is greater than N.
[0016] In some embodiments, the second compensation branch further includes a first resistor connected between the emitter of the fourth transistor and the fourth end of the second compensation branch.
[0017] In some embodiments, the first compensation branch further includes a second resistor connected between the collector of the third transistor and the collector of the first transistor; the second compensation branch further includes a third resistor connected between the base of the third transistor and the collector of the fourth transistor.
[0018] In some embodiments, the method further includes: providing a bias unit, wherein the bias unit is configured to provide a bias current for the first compensation branch and the second compensation branch, the bias unit includes a fourth resistor connected to the first input terminal and a fifth resistor connected to the second input terminal, the other end of the fourth resistor and the other end of the fifth resistor are connected together and serve as an output end of a reference voltage; and providing a bias current for the first compensation branch and the second compensation branch through the bias unit.
[0019] According to a third aspect of the present disclosure, an integrated circuit is provided, comprising the voltage reference circuit according to any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by referring to the accompanying drawings and reading the following detailed description. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation.
[0021] Figure 1 A schematic circuit diagram showing a voltage reference circuit according to a first embodiment of the present disclosure.
[0022] Figure 2 A schematic circuit diagram of a voltage reference circuit according to a second embodiment of the present disclosure is shown.
[0023] Figure 3 A schematic circuit diagram showing a voltage reference circuit according to a third embodiment of the present disclosure.
[0024] Figure 4 A schematic circuit diagram showing a voltage reference circuit according to a fourth embodiment of the present disclosure.
[0025] Figure 5 A flow chart illustrating a method for operating a voltage reference circuit according to an embodiment of the present disclosure is shown.
[0026] Figure 6 A schematic circuit diagram of a conventional voltage reference circuit is shown.
[0027] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION
[0028] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.
[0029] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0030] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.
[0031] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.
[0032] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.
[0033] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0034] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.
[0035] The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of this application are synonymous.
[0036] Figure 1 FIG. 1 is a schematic circuit diagram of a voltage reference circuit according to a first embodiment of the present disclosure. Figure 1 As shown, the voltage reference circuit may include an operational amplifier OP, a MOS transistor M1, and a bias unit 50. The operational amplifier OP may include a first input terminal IN_1 and a second input terminal IN_2. The output of the operational amplifier OP is connected to the gate of the MOS transistor M1, the source of the MOS transistor M1 is connected to the power supply VDD, and the drain of the MOS transistor is connected to the bias unit and the reference voltage output terminal VBG. The bias unit 50 may include resistors R2 and R3, and bias current is provided to the compensation branch through the bias unit 50. It is worth noting that the illustrated embodiment is merely exemplary. In other embodiments, the MOS transistor M1 may be replaced by a resistor. Since these components are well known in the art, a detailed description thereof is omitted.
[0037] like Figure 1 As shown, the voltage reference circuit further includes a first compensation branch 10 and a second compensation branch 20. The first compensation branch 10 includes a first end connected to the first input terminal IN_1 and a second end connected to a reference potential. The first compensation branch 10 includes one or more first transistors Q1 disposed between the first end and the second end. When multiple first transistors Q1 are provided, the multiple first transistors Q1 are connected in parallel. The base of each first transistor Q1 is connected to the collector of the first transistor Q1, and the emitter of the first transistor Q1 is connected to the second end. In some embodiments, the reference potential is ground potential.
[0038] The second compensation branch 20 includes a third terminal connected to the second input terminal IN_2 and a fourth terminal connected to the reference potential. The second compensation branch 20 includes a plurality of second triodes Q2 arranged between the third terminal and the fourth terminal. The plurality of second triodes Q2 are connected in parallel with each other. The number of the second triodes Q2 can be K times the number of the first triodes Q1, where K is a natural number greater than 1. When the number of the first triodes Q1 is N (N is not less than 1), the number of the second triodes Q2 is K*N. The base of each second triode Q2 is connected to the collector of the second triode Q2, and the emitter base of each second triode Q2 is connected to the fourth terminal.
[0039] like Figure 1As shown, the first compensation branch 10 also includes a third compensation branch. The third compensation branch may include one or more third transistors Q3. In the case of multiple third transistors Q3, the multiple third transistors Q3 are connected in parallel. The collector of each third transistor Q3 is connected to the collector of the second transistor Q2, and the base of each third transistor Q3 is connected to the collector of the first transistor Q1.
[0040] According to the present disclosure, under the operation of the operational amplifier OP, the voltages at the first input terminal IN_1 and the second input terminal IN_2 are equal, and the currents flowing through the resistors R2 and R3 are equal. When noise is present at the output of the operational amplifier OP, one or more third transistors Q3 are provided as a third compensation branch to provide a noise compensation voltage at the collector of the second transistor Q2 that is in opposite phase to the voltage at the second input terminal IN_2. This reduces the noise and / or voltage offset transmitted from the second input terminal IN_2 of the operational amplifier OP to the VBG node.
[0041] The working principle of the noise compensation of the third compensation branch is as follows. As an example, when there is noise at the output of the operational amplifier OP (i.e., at the VBG node), under the action of the noise, the noise current generates a noise voltage on IN_1 after passing through the resistor R2, and then flows through the first transistor Q1 to the reference potential. In addition, the noise current generates a noise voltage on IN_2 after passing through the resistor R3, and then flows through the second transistor Q2 to the reference potential. On the other hand, the current also flows through the third transistor Q3 to the reference potential. The noise generates a noise compensation voltage at the collector of the third transistor Q3 that is opposite to the above-mentioned noise. Therefore, through the setting of the third transistor Q3, the above-mentioned noise compensation voltage compensates for the noise voltage at the IN_2 node. As a result, the noise and / or voltage offset transmitted from the second input terminal IN_2 of the operational amplifier OP to the VBG node can be reduced.
[0042] Figure 2 A schematic circuit diagram of a voltage reference circuit according to a second embodiment of the present disclosure is shown. Figure 2 The embodiment shown is Figure 1 Similarly, the difference is that instead of arranging the third transistor on the first compensation branch 10 , the third transistor Q3 is arranged on the second compensation branch 20 .
[0043] like Figure 2 As shown, the second compensation branch 20 also includes a third compensation branch. The third compensation branch may include one or more third transistors Q3. In the case of multiple third transistors Q3, the multiple third transistors Q3 are connected in parallel. The collector of each third transistor Q3 is connected to the collector of the first transistor Q1, and the base of each third transistor Q3 is connected to the collector of the second transistor Q2.
[0044] According to the present disclosure, under the operation of the operational amplifier OP, the voltages at the first input terminal IN_1 and the second input terminal IN_2 are equal, and the currents flowing through the resistors R2 and R3 are equal. When noise is present at the output of the operational amplifier OP, one or more third transistors Q3 are provided as a third compensation branch to provide a noise compensation voltage at the collector of the first transistor Q1 that is in antiphase with the voltage at the first input terminal IN_1. This reduces the noise and / or voltage offset transmitted from the first input terminal IN_1 of the operational amplifier OP to the VBG node.
[0045] The working principle of the noise compensation of the third compensation branch is as follows. As an example, when there is noise at the output of the operational amplifier OP (i.e., at the VBG node), under the action of the noise, the noise current generates a noise voltage on IN_2 after passing through the resistor R3, and then flows through the second transistor Q2 to the reference potential; in addition, the noise current generates a noise voltage on IN_1 after passing through the resistor R2, and then flows through the first transistor Q1 to the reference potential. On the other hand, the current also flows through the third transistor Q3 to the reference potential. The noise generates a noise compensation voltage at the collector of the third transistor Q3 that is in phase with the above-mentioned noise. Through the setting of the third transistor Q3, the above-mentioned noise compensation voltage compensates for the noise voltage at the IN_1 node. As a result, the noise and / or voltage offset transmitted from the first input terminal IN_1 of the operational amplifier OP to the VBG node can be reduced.
[0046] Figure 3 A schematic circuit diagram showing a voltage reference circuit according to a third embodiment of the present disclosure. Figure 3 The embodiment shown is Figure 1 and Figure 2 The embodiment shown is similar except that it is implemented as Figure 1 and Figure 2 Combinations of the embodiments shown. Figure 3 In the illustrated embodiment, noise and / or voltage offset on the first compensation branch 10 and the second compensation branch 20 can be achieved simultaneously.
[0047] like Figure 3 As shown, the voltage reference circuit includes one or more third transistors Q3 and a plurality of fourth transistors Q4. The number of the fourth transistors Q4 may be K times the number of the third transistors Q3, where K is a natural number greater than 1. When the number of the third transistors Q3 is M (M is not less than 1), the number of the fourth transistors Q4 is K*M. The third transistors Q3 and the fourth transistors Q4 are arranged in a cross-coupled manner. Figure 3As shown, the collector of each third transistor Q3 is connected to the collector of the first transistor Q1, and the base of each third transistor Q3 is connected to the collector of the second transistor Q2. The collector of each fourth transistor Q4 is connected to the collector of the second transistor Q2, and the base of each fourth transistor Q4 is connected to the collector of the first transistor Q1.
[0048] According to the present disclosure, the cross-coupled third transistor Q3 and fourth transistor Q4 can reduce the noise of the operational amplifier in both compensation branches, thereby achieving a low-noise and / or low-offset design of the voltage reference circuit without increasing the chip area.
[0049] In some embodiments, as Figure 3 As shown, the second compensation branch 20 further includes a first resistor R1 connected between the emitter of the fourth transistor Q4 and the fourth end of the second compensation branch 20. According to the present disclosure, a low power consumption design can be achieved.
[0050] The noise voltage compensation principle of the cross-coupled third and fourth transistors Q3 and Q4 is as follows. In particular, it can achieve noise voltage compensation on both sides of the branch where IN_1 and IN_2 are located. As an example, when noise is present at the output of the operational amplifier OP (i.e., at the VBG node), under the influence of the noise, the noise current generates a noise voltage on IN_1 after passing through the resistor R2, and then flows through the first transistor Q1 to the reference potential. In addition, the noise current generates a noise voltage on IN_2 after passing through the resistor R3, and then flows through the second transistor Q2 to the reference potential.
[0051] Furthermore, the noise current flows through the third transistor Q3 and reaches the reference potential. This noise generates a noise compensation voltage at the collector of the third transistor Q3 that is in antiphase with the noise. This noise compensation voltage compensates for the noise voltage at the IN_1 node. This reduces the noise and / or voltage offset transmitted from the first input terminal IN_1 of the operational amplifier OP to the VBG node.
[0052] Meanwhile, the noise current also flows through the fourth transistor Q4 and reaches the reference potential. This noise generates a noise compensation voltage at the collector of the fourth transistor Q4 that is in antiphase with the noise. This noise compensation voltage compensates for the noise voltage at the IN_2 node. This reduces the noise and / or voltage offset transmitted from the first input terminal IN_2 of the operational amplifier OP to the VBG node.
[0053] According to the present disclosure, voltage noise compensation can be achieved on both sides of the output of the operational amplifier OP through a cross-coupled compensation circuit.
[0054] According to the present disclosure, the transfer function from the noise of the operational amplifier to the reference voltage output node VBG can be approximately expressed as:
[0055]
[0056] Where V BG is the noise voltage contributed by the operation at the reference voltage output node VBG, gmQ1, gmQ2, and gmQ4 are the transconductances of transistors Q1, Q2, and Q4 respectively, and Vn,amp is the equivalent input noise voltage of the amplifier.
[0057] In some embodiments, it is desirable to minimize the absolute value of the transfer function described above, thereby minimizing the noise contributed by the operation. In this case, this can be achieved by selecting the number of first transistors Q1 and third transistors Q3. In some embodiments, the number of third transistors Q3 can be set to be greater than the number of first transistors Q1. In some embodiments, when the number of first transistors Q1 is N and the number of third transistors Q3 is M, M is greater than N. In some embodiments, the number N of first transistors Q1 can be 1, 2, 3, 4, or more; the number M of third transistors Q3 can be 2, 3, 4, 5, 6, or more. In addition, the cross-coupling of the third transistor Q3 and the fourth transistor Q4 generates negative impedance, which reduces the impedance from the VBG node to ground, thereby improving the power supply rejection ratio.
[0058] The embodiments of the present disclosure have significantly improved performance compared to the prior art. Figure 3 The embodiment shown is used as an example to illustrate a conventional voltage reference circuit. Figure 6 A comparison is made to further illustrate the performance improvement effect according to the embodiment of the present disclosure. Figure 6 As shown, the conventional voltage reference circuit may include an operational amplifier OP and transistors Q1 and Q2 connected in the form of diodes. The conventional voltage reference circuit does not have a noise compensation branch, for example, it is implemented as Figure 3 The noise compensation branch of the cross-coupled third transistor Q3 and / or the fourth transistor Q4 of the embodiment. Figure 6 In the case shown, the noise transfer function from the operational amplifier OP to the VBG output point is:
[0059]
[0060] Where V BG is the noise voltage contributed by the operation at the reference voltage output node VBG, gmQ1 and gmQ2 are the transconductances of transistors Q1 and Q2 respectively, and Vn,amp is the equivalent input noise voltage of the amplifier.
[0061] The transfer function is approximately 1 + R2 / R1. Depending on the selected values of R2 and R1, the transfer function can be adjusted. In some embodiments, the noise transfer function 1 + R2 / R1 can be set to approximately 20. This means that conventional structures will amplify the noise generated by the operation by approximately 20 times at the output.
[0062] Will Figure 3 The transfer function of the VBG of the embodiment is Figure 6 Compared with the transfer function of VBG of the traditional circuit, it is calculated as follows:
[0063]
[0064] In some embodiments, for example, when gmQ3 + gmQ4 = 15µs, gmQ3 - gmQ2 = 3µs, and R2 = 2M, and when N = 2 and M = 3, the calculated attenuation factor according to the disclosed embodiments can be as high as 7.8 compared to conventional solutions. This means that the operational amplifier-to-VBG noise of the proposed solution is 1 / 7.8 times that of conventional solutions. By selecting different values for N and M, the noise attenuation performance can be further improved. For example, when N = 3 and M = 4, the aforementioned noise psrr is further reduced and improved.
[0065] Figure 4 A schematic circuit diagram showing a voltage reference circuit according to a fourth embodiment of the present disclosure. Figure 4 The embodiment shown is Figure 3 The embodiment shown is similar in that the third transistor Q3 and the fourth transistor Q4 are arranged in a cross-coupled manner, but the resistors are arranged in a different manner. Figure 4 As shown, the first compensation branch 10 further includes a second resistor R4 connected between the collector of the third transistor Q3 and the collector of the first transistor Q1. The second compensation branch 20 further includes a third resistor R1 connected between the base of the third transistor Q3 and the collector of the fourth transistor Q4. It is worth noting that the resistor arrangement shown is merely exemplary, and the resistors may be arranged in any other suitable manner as long as the inventive concepts of the present disclosure are implemented.
[0066] Figure 5 A flowchart illustrating a method for operating a voltage reference circuit according to an embodiment of the present disclosure is provided. At block 502, a first noise compensation voltage, which is in phase with the voltage at the corresponding input terminal of first input terminal IN_1 and second input terminal IN_2, is provided at the collector of at least one of first transistor Q1 and second transistor Q2 via a third compensation branch. The collector of at least one of the transistors is connected to the corresponding input terminal. At block 504, the noise voltage delivered to the VBG node by the operational amplifier is compensated by the first noise compensation voltage.
[0067] In some embodiments, the first compensation branch 10 includes a third compensation branch, the third compensation branch includes M third transistors Q3, the collector of each third transistor Q3 is connected to the collector of the first transistor Q1, and the base of each third transistor Q3 is connected to the collector of the second transistor Q2, where M is a natural number not less than 1; the second compensation branch 20 includes a fourth compensation branch, the fourth compensation branch includes K*M fourth transistors Q4, the collector of each fourth transistor Q4 is connected to the collector of the second transistor Q2, and the base of each fourth transistor Q4 is connected to the collector of the first transistor Q1. According to the present disclosure, the method may further include: providing a first noise compensation voltage with a phase opposite to the voltage at the first input terminal IN_1 at the collector of the fourth transistor Q4 through the fourth compensation branch; compensating the noise voltage transmitted to the VBG node by the first noise compensation voltage; providing a second noise compensation voltage with a phase opposite to the voltage at the second input terminal IN_2 at the collector of the third transistor Q3 through the third compensation branch; and compensating the noise voltage transmitted to the VBG node by the second noise compensation voltage.
[0068] In some embodiments, M may be greater than N.
[0069] In some embodiments, the second compensation branch 20 may further include a first resistor R1 connected between the emitter of the fourth transistor Q4 and the fourth end of the second compensation branch 20 .
[0070] In some embodiments, the first compensation branch 10 may further include a second resistor R4 connected between the collector of the third transistor Q3 and the collector of the first transistor Q1; the second compensation branch 20 also includes a third resistor connected between the base of the third transistor Q3 and the collector of the fourth transistor Q4.
[0071] In some embodiments, the method may further include: providing a bias unit 50, the bias unit being configured to provide a bias current for the first compensation branch 10 and the second compensation branch 20, the bias unit including a fourth resistor R2 connected to the first input terminal IN_1 and a fifth resistor R3 connected to the second input terminal IN_2, the other end of the fourth resistor R2 and the other end of the fifth resistor R3 being connected together and serving as an output end of a reference voltage; and providing a bias current for the first compensation branch 10 and the second compensation branch 20 through the bias unit 50.
[0072] According to the present disclosure, an integrated circuit is further provided, comprising the voltage reference circuit according to the present disclosure.
[0073] In addition, although adopting specific order to describe each operation, this should be understood as requiring such operation to be carried out in the specific order shown or in sequential order, or requiring that all illustrated operations should be carried out to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.
[0074] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.
[0075] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A voltage reference circuit, comprising: an operational amplifier (OP), comprising a first input terminal (IN_1) and a second input terminal (IN_2); a first compensation branch (10), the first compensation branch (10) comprising a first end connected to the first input end (IN_1) and a second end connected to a reference potential, the first compensation branch (10) comprising at least one first transistor (Q1) arranged between the first end and the second end, the base of each first transistor (Q1) being connected to the collector of the first transistor (Q1), and the emitter of the first transistor (Q1) being connected to the second end; as well as a second compensation branch (20), the second compensation branch (20) comprising a third end connected to the second input end (IN_2) and a fourth end connected to the reference potential, the second compensation branch (20) comprising at least one second triode (Q2) arranged between the third end and the fourth end, the base of each second triode (Q2) being connected to the collector of the second triode (Q2), and the emitter of each second triode (Q2) being connected to the fourth end; At least one of the first compensation branch (10) and the second compensation branch (20) further includes a third compensation branch, the third compensation branch including at least one third triode (Q3), the collector of each third triode (Q3) being connected to the collector of one of the first triode (Q1) and the second triode (Q2), and the base of each third triode (Q3) being connected to the collector of the other of the first triode (Q1) and the second triode (Q2).
2. The voltage reference circuit according to claim 1 , wherein the second compensation branch ( 20 ) includes the third compensation branch, the third compensation branch including at least one third transistor ( Q3 ), the collector of each third transistor ( Q3 ) being connected to the collector of the first transistor ( Q1 ), and the base of each third transistor ( Q3 ) being connected to the collector of the second transistor ( Q2 ); and The first compensation branch (10) includes a fourth compensation branch, the fourth compensation branch including at least one fourth transistor (Q4), the collector of each fourth transistor (Q4) being connected to the collector of the second transistor (Q2), and the base of each fourth transistor (Q4) being connected to the collector of the first transistor (Q1).
3. The voltage reference circuit according to claim 2, wherein the number of the second transistors (Q2) is K times the number of the first transistors (Q1), the number of the fourth transistors (Q4) is K times the number of the third transistors (Q3), and K is a natural number greater than 1.
4. The voltage reference circuit according to claim 2 or 3, wherein the number of the first transistors (Q1) is N, the number of the third transistors (Q3) is M, M and N are natural numbers not less than 1, and M is greater than N.
5. The voltage reference circuit according to any one of claims 2 to 4, wherein the second compensation branch (20) further comprises a first resistor (R1) connected between the emitter of the fourth transistor (Q4) and the fourth end of the second compensation branch (20).
6. The voltage reference circuit according to any one of claims 2 to 4, wherein the first compensation branch (10) further includes a second resistor (R4) connected between the collector of the third transistor (Q3) and the collector of the first transistor (Q1); and the second compensation branch (20) further includes a third resistor connected between the base of the third transistor (Q3) and the collector of the fourth transistor (Q4).
7. The voltage reference circuit according to any one of claims 1 to 4, further comprising a bias unit (50), wherein the bias unit is configured to provide a bias current for the first compensation branch (10) and the second compensation branch (20), wherein the bias unit comprises a fourth resistor (R2) connected to the first input terminal (IN_1) and a fifth resistor (R3) connected to the second input terminal (IN_2), wherein the other end of the fourth resistor (R2) and the other end of the fifth resistor (R3) are connected together and serve as an output end of a reference voltage.
8. The voltage reference circuit according to claim 7, further comprising a MOS transistor, wherein the gate of the MOS transistor is connected to the output of the operational amplifier (OP), the source of the MOS transistor is connected to a power supply, and the drain of the MOS transistor is connected to the output end of the reference voltage.
9. A method for operating the voltage reference circuit of claim 1, comprising: providing a first noise compensation voltage having a phase opposite to that of a voltage at a corresponding input terminal of the first input terminal (IN_1) and the second input terminal (IN_2) at a collector of at least one of the first transistor (Q1) and the second transistor (Q2) through the third compensation branch, wherein the collector of the at least one transistor is connected to the corresponding input terminal; and The noise transferred from the equivalent input noise voltage of the operational amplifier to the reference voltage is compensated by the first noise compensation voltage.
10. The method according to claim 9, wherein The second compensation branch (20) includes the third compensation branch, the third compensation branch includes at least one third triode (Q3), the collector of each third triode (Q3) is connected to the collector of the first triode (Q1), and the base of each third triode (Q3) is connected to the collector of the second triode (Q2); The third compensation branch (10) includes a fourth compensation branch, the fourth compensation branch includes at least one fourth triode (Q4), the collector of each fourth triode (Q4) is connected to the collector of the second triode (Q2), and the base of each fourth triode (Q4) is connected to the collector of the first triode (Q1); The method further comprises: providing a first noise compensation voltage having a phase opposite to that of the voltage at the first input terminal (IN_1) at the collector of the fourth transistor (Q4) through the fourth compensation branch; Compensating for noise generated by the operational amplifier at a reference voltage by using the first noise compensation voltage; providing a second noise compensation voltage having a phase opposite to that of the voltage at the second input terminal (IN_2) at the collector of the third transistor (Q3) through the third compensation branch; and Noise generated by the operational amplifier at a reference voltage is compensated by the second noise compensation voltage.
11. The method according to claim 10, wherein the number of the second transistors (Q2) is K times the number of the first transistors (Q1), the number of the fourth transistors (Q4) is K times the number of the third transistors (Q3), K is a natural number greater than 1, wherein the number of the first transistors (Q1) is N, the number of the third transistors (Q3) is M, M and N are natural numbers not less than 1, and M is greater than N.
12. The method according to claim 10 or 11, wherein the second compensation branch (20) further comprises a first resistor (R1) connected between the emitter of the fourth transistor (Q4) and the fourth end of the second compensation branch (20).
13. The method according to claim 10 or 11, wherein the first compensation branch (10) further includes a second resistor (R4) connected between the collector of the third transistor (Q3) and the collector of the first transistor (Q1); and the second compensation branch (20) further includes a third resistor connected between the base of the third transistor (Q3) and the collector of the fourth transistor (Q4).
14. The method according to any one of claims 9 to 11, further comprising: A bias unit (50) is provided, the bias unit being configured to provide a bias current for the first compensation branch (10) and the second compensation branch (20), the bias unit comprising a fourth resistor (R2) connected to the first input terminal (IN_1) and a fifth resistor (R3) connected to the second input terminal (IN_2), the other end of the fourth resistor (R2) and the other end of the fifth resistor (R3) being connected together and serving as an output end of a reference voltage; as well as The bias unit (50) provides a bias current for the first compensation branch (10) and the second compensation branch (20).
15. An integrated circuit comprising the voltage reference circuit according to any one of claims 1 to 8.