FPGA (Field Programmable Gate Array) clock layout and wiring method and system

Abstract

The invention relates to the technical field of clock layout and wiring, and discloses an FPGA (Field Programmable Gate Array) clock layout and wiring method and system, the method is applied to an FPGA device, the FPGA device comprises a plurality of clock domains, and the method comprises the following steps: reducing bounding boxes of clocks in the clock domains until the number of the clocks in each clock domain is legal; allocating the clock resources of the clocks, so that the bounding boxes of the clocks allocated to the same clock resource are not overlapped, and the clock resources of the clocks do not exceed the corresponding bounding box range; after clock resource allocation is completed, a clock balance tree is constructed in a bounding box of each clock, so that delay of each clock from a source to each destination node is the same; and realizing routing from a clock source to a root node of the clock balance tree through a routing algorithm. Clock resources are allocated in advance, and a clock balance tree is constructed, so that the problem of resource congestion in a layout and wiring process is avoided, and attenuation and interference of signals in a transmission process can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of clock layout and routing, and in particular to a FPGA clock layout and routing method and system. Background Art

[0002] FPGAs (Field Programmable Gate Arrays, or FPGAs for short) can be programmed to implement a variety of complex digital logic functions. Their configurability includes even more complex clock architecture logic for synchronizing operations, controlling timing, optimizing performance, and simplifying design. However, the physical structure and functionality of the clock network in FPGAs are pre-fabricated and cannot be adjusted for different application scenarios. Generally speaking, an FPGA device is divided into multiple clock domains, each of which contains limited clock resources. This means that the number of clocks allocated to each clock domain cannot exceed a preset value, which is far less than the total number of clocks an FPGA is required to provide. For high-utilization designs, as the design scale and complexity increase, FPGAs often need to support hundreds of clocks. Therefore, the clock architecture, with its additional clock restrictions, further complicates layout and routing. Traditional FPGA layout and routing methods already struggle to support large-scale clock structures.

[0003] Therefore, there is an urgent need for a layout and routing method that can support ultra-large-scale clocks in FPGAs. Summary of the Invention

[0004] In view of this, the present application provides an FPGA clock layout and routing method and system, which can support the layout and routing of ultra-large-scale FPGA clocks. The technical solution is as follows.

[0005] In a first aspect, the present invention provides an FPGA clock layout and routing method, which is applied to an FPGA device including multiple clock domains. The method includes:

[0006] Reduce the bounding box of the clocks in the clock domain until the number of clocks in each clock domain is legal;

[0007] Allocate clock resources so that the bounding boxes of clocks allocated to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes;

[0008] After clock resource allocation is completed, a clock balancing tree is constructed within the bounding box of each clock so that the delay from the source to each destination node is the same for each clock;

[0009] The routing algorithm is used to implement the routing from the clock source to the root node of the clock balancing tree.

[0010] In an optional implementation, shrinking the bounding box of the clocks in the clock domain until the number of clocks in each clock domain is legal includes:

[0011] Set the capacity limit in each clock domain; the capacity limit is used to represent the maximum number of clocks in each clock domain;

[0012] The bounding boxes of the clocks in each clock domain are adjusted through an iterative method so that the number of all clocks in the clock domain does not exceed the capacity limit corresponding to each clock domain.

[0013] In an optional implementation manner, allocating clock resources of the clock pair includes:

[0014] Get the distance and layout parameters between each clock in each clock domain;

[0015] A unique resource identifier is assigned to each clock according to the distance and layout parameters, so that the bounding boxes of clocks assigned to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

[0016] In an optional implementation, building a clock balancing tree within the bounding box of each clock includes:

[0017] Select the root node of the clock balancing tree within the bounding box of the current clock;

[0018] Starting from the root node, branch nodes are expanded hierarchically until a target node within the bounding box is reached; wherein, in a path from the root node to any target node, the number of branch nodes passed through is equal.

[0019] In an optional implementation, implementing routing from the clock source to the root node of the clock balancing tree by using a routing algorithm includes:

[0020] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and then starts visiting the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining a traversal access path.

[0021] According to the traversed access path, the target access path is obtained to realize the routing from the clock source to the root node of the clock balancing tree.

[0022] The present invention provides an FPGA clock layout and routing method, which has the following advantages.

[0023] The FPGA clock layout and routing method of the present invention is applied to an FPGA device comprising multiple clock domains. By reducing the bounding boxes of clocks within the clock domains until the number of clocks within each clock domain is legal, the number of clocks within the clock domains is legalized, ensuring that the number of clocks within each clock domain does not exceed the resource carrying capacity of the clock domain, and that the layout and routing can effectively support these clocks. After legalization is completed, the clock resources of the clocks are allocated so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of the clocks do not exceed the corresponding bounding box range, thereby alleviating the layout and routing resource congestion problem caused by ultra-large-scale clocks. After the clock resource allocation is completed, a clock balance tree is constructed within the bounding boxes of each clock so that the delay of each clock from the source to each destination node is the same, which can reduce signal synchronization problems caused by clock skew. Through this structure, the transmission time of the clock signal can be ensured to be consistent, which can effectively solve the clock skew problem in the FPGA layout and routing process, thereby optimizing the clock performance of the system. By implementing routing from the clock source to the root node of the clock balancing tree through a routing algorithm, it is possible to ensure that the route from the clock source to the clock balancing tree is the shortest, thereby minimizing the delay of the clock signal and avoiding the introduction of additional skew and delay due to an excessively long clock transmission path. The FPGA clock layout and routing method provided by the present invention, by allocating clock resources in advance, can support hundreds of clock scales under the premise of limited clock routing resources, ensuring that resource congestion will not occur in the subsequent layout and routing process. In addition, the construction of the clock balancing tree of this embodiment further reduces clock skew while meeting the complex constraints of layout and routing, enhances signal integrity, effectively reduces signal attenuation and interference during transmission, and improves overall system performance.

[0024] In a second aspect, the present invention provides an FPGA clock placement and routing system, which is applied to an FPGA device, the FPGA device including multiple clock domains, and the system includes:

[0025] The legalization module is used to reduce the bounding box of clocks in the clock domain until the number of clocks in each clock domain is legal;

[0026] A clock resource allocation module is used to allocate clock resources of clocks so that the boundary boxes of clocks allocated to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding boundary boxes;

[0027] The balanced tree construction module is used to build a clock balanced tree within the boundary box of each clock after clock resource allocation is completed, so that the delay of each clock from the source to each destination node is the same;

[0028] The routing module is used to implement routing from the clock source to the root node of the clock balancing tree through a routing algorithm.

[0029] In an optional implementation, the legalization module is specifically configured to:

[0030] Set the capacity limit in each clock domain; the capacity limit is used to represent the maximum number of clocks in each clock domain;

[0031] The bounding boxes of the clocks in each clock domain are adjusted through an iterative method so that the number of all clocks in the clock domain does not exceed the capacity limit corresponding to each clock domain.

[0032] In an optional implementation manner, the clock resource allocation module is specifically configured to:

[0033] Get the distance and layout parameters between each clock in each clock domain;

[0034] A unique resource identifier is assigned to each clock according to the distance and layout parameters, so that the bounding boxes of clocks assigned to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

[0035] In an optional embodiment, the balanced tree construction module is specifically used to:

[0036] Determine the source node, target node, and branch node from the clock source;

[0037] Select the root node of the clock balancing tree within the bounding box of the current clock;

[0038] Starting from the root node, branch nodes are expanded hierarchically until a target node within the bounding box is reached; wherein, in a path from the root node to any target node, the number of branch nodes passed through is equal.

[0039] In an optional implementation, the routing module is specifically configured to:

[0040] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and then starts visiting the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining a traversal access path.

[0041] According to the traversed access path, the target access path is obtained to realize the routing from the clock source to the root node of the clock balancing tree.

[0042] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute the FPGA clock layout and routing method of the first aspect or any corresponding embodiment thereof.

[0043] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the FPGA clock layout and routing method of the first aspect or any corresponding embodiment thereof.

[0044] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, which are used to enable a computer to execute the FPGA clock layout and routing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 The present invention is a flowchart illustrating a method for FPGA clock layout and routing according to an exemplary embodiment.

[0047] Figure 2 The figure is a specific flow chart of an FPGA clock layout and routing method according to an exemplary embodiment.

[0048] Figure 3 The figure is a schematic diagram of constructing a clock balancing tree according to an exemplary embodiment.

[0049] Figure 4 The figure is a schematic diagram showing the construction of routing from a clock source to a balanced tree according to an exemplary embodiment.

[0050] Figure 5 This is a structural diagram of an FPGA clock layout and routing system provided in an embodiment of the present application.

[0051] Figure 6 It is a structural diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0053] It should be understood that the "indication" mentioned in the embodiments of this application can be a direct indication, an indirect indication, or an indication of an association. For example, "A indicates B" can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association between A and B.

[0054] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0055] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). This application does not limit its specific implementation method.

[0056] FPGAs (Field Programmable Gate Arrays, or FPGAs) can be programmed to implement a variety of complex digital logic functions. Their configurability includes even more complex clock architecture logic for synchronizing operations, controlling timing, optimizing performance, and simplifying design. However, the physical structure and functionality of the clock network in FPGAs are pre-configured and cannot be adjusted for different application scenarios. Generally speaking, an FPGA device is divided into multiple clock domains, each of which contains limited clock resources. This limits the number of clocks allocated to each clock domain to a preset value, which is significantly smaller than the total number of clocks an FPGA is required to provide. For high-utilization designs, as the design scale and complexity increase, FPGAs often need to support hundreds of clocks. Therefore, the clock architecture imposes additional clock restrictions, further complicating layout and routing. Traditional FPGA layout and routing methods already struggle to support large-scale clock structures. This necessitates the adoption of new technologies to support the layout and routing of ultra-large-scale clocks in FPGAs.

[0057] Therefore, an embodiment of the present invention provides an FPGA clock placement and routing method. By pre-allocating clock resources, this method supports hundreds of clocks within limited clock routing resources, ensuring that resource congestion does not occur during the subsequent placement and routing process. Furthermore, the construction of a clock balancing tree in this embodiment further reduces clock skew, enhances signal integrity, effectively minimizes signal attenuation and interference during transmission, and improves overall system performance while meeting complex placement and routing constraints.

[0058] The FPGA clock layout and routing method provided in this embodiment is applied to an FPGA device, which includes multiple clock domains. The method flow of the method is as follows: Figure 1 As shown, the following steps are included.

[0059] S101 : Shrinking the boundary boxes of clocks in the clock domains until the number of clocks in each clock domain is legal.

[0060] During FPGA clock placement, especially during Global Placement, clock resources are often not adequately constrained, potentially causing the number of clocks in each clock domain to exceed its resource capacity. Therefore, it's necessary to reduce the bounding box of clocks within a clock domain until the number of clocks in all clock domains is legal. Legal means ensuring that, given the clock resources, the number of clocks in each clock domain does not exceed the resource capacity of that clock domain, and that placement and routing can effectively support these clocks.

[0061] S102 : Allocate clock resources of the clocks so that the boundary boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of the clocks do not exceed the range of the corresponding boundary boxes.

[0062] To avoid layout and routing resource conflicts caused by too many clocks, after legalizing the number of clocks, clock resources must be allocated to ensure that the bounding boxes of each clock do not overlap and to prevent resource interference between clocks during layout and routing. Specifically, each clock is assigned a unique resource identifier based on its layout location to ensure that these resources do not conflict.

[0063] S103 : After the clock resources are allocated, a clock balancing tree is constructed within the boundary box of each clock, so that the delay of each clock from the source to each destination node is the same.

[0064] In FPGA design, clock skew is a common problem that can lead to signal synchronization errors and even system instability. To address this issue, this embodiment solves it by constructing an H-tree (clock balance tree). An H-tree is a symmetrical and evenly distributed tree structure that ensures equal clock delays from the clock source node to each sink node, reducing signal synchronization issues caused by clock skew. Through this structure, the transmission time of the clock signal can be ensured to remain consistent, thereby optimizing the clock performance of the system.

[0065] S104: Implement routing from the clock source to the root node of the clock balancing tree through a routing algorithm.

[0066] In FPGA designs, clock sources are typically located in the Clock Management Tile (CMT). Routing from the CMT to the root node of the clock balancing tree is a critical aspect of clock tree design. Routing algorithms are used to ensure the shortest possible route from the clock source to the clock balancing tree, minimizing clock signal delay and avoiding the additional skew and delay introduced by long clock transmission paths.

[0067] The FPGA clock placement and routing method provided in this embodiment uses pre-allocation of clock resources to support hundreds of clocks within limited clock routing resources, ensuring that resource congestion does not occur during subsequent placement and routing. Furthermore, the construction of a clock balancing tree in this embodiment further reduces clock skew, enhances signal integrity, and effectively minimizes signal attenuation and interference during transmission, while meeting complex placement and routing constraints. This improves overall system performance.

[0068] In order to better illustrate the above embodiment, the above steps will be described in detail below. The specific process is as follows: Figure 2 shown.

[0069] Step S101 involves reducing the bounding boxes of clocks within a clock domain until the number of clocks within each clock domain is legal. The specific process includes: first, defining the resource constraints within each clock domain, specifically the maximum number of clocks supported by each clock domain, i.e., the capacity of each clock domain. The clock layout problem is then transformed into a flow network problem, where the capacity of each clock source, clock network, and clock domain is considered as a node and edge in the network. The capacity constraint of each clock domain determines the maximum flow rate at each node. An iterative method is then used to adjust the clock bounding boxes so that the number of clocks within the clock domain does not exceed the maximum supported value. In each iteration, the layout of the clocks within the clock domain is adjusted based on the flow distribution and constraints. Each adjustment attempts to reduce the bounding boxes of clock signals that exceed the clock domain capacity until all clock domains meet the legalization criteria. After several rounds of iterations, the number of clocks in the clock domain gradually becomes legal. At this point, a determination is made as to whether the target state has been reached, i.e., the number of clocks in all clock domains no longer exceeds the capacity constraint. If convergence is achieved, the iteration is terminated.

[0070] The above-mentioned iterative algorithm may adopt an iterative min cost flow-based algorithm (an iterative algorithm based on minimum cost flow), such as SPFA (Shortest Path Faster Algorithm), Successive Shortest Path Algorithm (continuous shortest path algorithm) or Cycle-Canceling Algorithm (cycle cancellation algorithm).

[0071] Step S102 allocates clock signals to different resources while ensuring that the layouts of these clocks do not conflict, thereby avoiding interference in clock resource usage. The layout and routing process can be viewed as a graph coloring problem. Each clock is considered a node in the graph, and layout conflicts between two clocks are considered edge connections. If the bounding boxes of two clocks overlap, there is a conflict between the two clocks and different resources should be allocated. This problem is transformed into a graph coloring problem, which requires assigning a "color" to each clock node, with different colors representing different resources, to ensure that adjacent nodes (clocks) do not share the same resources. The specific process includes: first, detecting whether there is a conflict between clocks. Clock conflicts typically depend on their position in the layout, bounding box size, distance, and the degree of interference between them. By calculating the distance between clocks and layout parameters, it is determined which clock signals require different resource identifiers. Subsequently, each clock node is assigned a unique resource identifier (color) to ensure that no two adjacent nodes (i.e., conflicting clocks in the layout) have the same resource identifier.

[0072] The above allocation methods can use graph coloring-based allocation algorithms, such as the greedy algorithm. This method scans the nodes of the graph and selects the smallest resource number for each node to ensure that adjacent nodes do not share the same resources. Although this method may not achieve the optimal solution, it usually provides a close approximation. Backtracking algorithms try all possible resource allocations to find the optimal solution that meets the conditions. This method is more accurate but computationally intensive and is suitable for small-scale layout problems. Heuristic algorithms, such as genetic algorithms or simulated annealing, use specific heuristic search strategies to find the optimal solution.

[0073] The basic idea of the H-tree structure in step S103 is to select the root node of the clock balance tree within the bounding box of the current clock; starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes passed through in the path from the root node to any target node is equal. Specifically, the H-tree structure is a recursive tree structure that ensures that the lengths of each branch at each level are equal, so that the delay of each target node receiving the clock signal remains consistent. It can effectively reduce clock skew and improve the clock performance and system stability of the FPGA design. The structure of the H-tree includes: the source node (Clock Source) is usually the starting point of the clock signal and the root node of the H-tree. The branch node recursively divides the clock signal path, and each branch has the same length and characteristics to ensure that each target node receives an equal delay. The destination node (Sink Nodes) is the node that ultimately receives the clock signal, usually the various modules or logic units within the FPGA.

[0074] The specific construction process of the above H-tree is as follows Figure 3 As shown, it includes: selecting a clock source as the root node, which represents the starting point of the clock signal. All other nodes will receive the signal transmitted from the clock source. The clock source signal is distributed to two child nodes, which are branches of the clock signal. Then, these two child nodes are distributed to more distant child nodes to form a recursive structure. The number of branch nodes at each layer is equal, and the length of each branch path is also equal. This ensures that the path delay from all target nodes to the source node is equal, thereby reducing clock skew. Each time it is distributed, the symmetry between the subtrees is ensured to ensure that each node is at the same level and has the same propagation path length as other nodes. When a leaf node (sink node) is reached, the recursion stops. Each leaf node is the final clock target node.

[0075] In practical designs, clock tree construction not only requires consideration of symmetry but also optimization of physical parameters such as latency, power consumption, and routing resources. H-tree optimization strategies can be employed. For example, branch lengths can be optimized to reduce propagation delay variations between different paths, thereby minimizing clock skew. The tree's height can also be balanced to ensure that all leaf nodes are evenly spaced from the root. In practical FPGA or IC design, routing resources are limited. Therefore, the tree can be optimized by selecting an appropriate number and structure of branches to minimize complexity and reduce routing area. Different resistors and capacitors within the tree can be optimized to avoid asymmetry at certain nodes due to excessive propagation delays. Each path in the H-tree is optimized to ensure that clock signals reach each target node with the minimum possible propagation delay. Dynamic programming algorithms can be used to calculate the minimum delay for each path, ensuring consistent signal arrival times. The tree's hierarchy is then adjusted to ensure that the length and load of each branch are as balanced as possible at each level, minimizing delay variations between long and short paths.

[0076] In step S104, the routing design from the clock source to the root node of the clock balancing tree must not only consider the transmission distance of the clock signal, but also ensure that the delay and skew of the clock signal are minimized. The routing algorithm is used to determine the shortest path from the clock source to each target node, thereby reducing the delay in signal transmission. The specific process includes: starting from the clock source (CMT), adding it to the queue. Traversing the nodes directly connected to the clock source layer by layer, and adding these nodes to the queue. Expand the nodes according to the hierarchical structure to ensure that each node is accessed within the shortest path. Finally, find the shortest path from the clock source to the root node of the clock balancing tree.

[0077] The above routing algorithm can adopt the BFS-based (breadth-first search) algorithm, and its process is as follows: Figure 4 As shown in the figure, the BFS algorithm is a graph traversal algorithm that visits all adjacent nodes layer by layer along the hierarchical structure of the graph. Its core idea is to start from an initial node (source node), visit all nodes adjacent to the current node, and then visit unvisited adjacent nodes in turn. Specifically, starting from the clock source node, initialize a queue, put the clock source node into the queue, and mark it as visited. Take the nodes out of the queue one by one, and check all the adjacent nodes of the node (i.e., the logic blocks connected to it, clock distribution resources, etc.). For each adjacent node, if it has not been visited, add it to the queue and record its path. When all target nodes have been traversed, a clock tree can be constructed based on the traversal record path. This tree will ensure that the path from the clock source to each receiving node is the shortest.

[0078] In summary, the FPGA clock layout and routing method provided by the embodiment of the present invention is applied to an FPGA device that includes multiple clock domains. By reducing the bounding box of the clocks in the clock domain until the number of clocks in each clock domain is legal, the number of clocks in the clock domain is legalized, ensuring that the number of clocks in each clock domain does not exceed the resource carrying capacity of the clock domain, and that the layout and routing can effectively support these clocks. After the legalization is completed, the clock resources of the clocks are allocated so that the bounding boxes of the clocks allocated to the same clock resource do not overlap, and the clock resources of the clocks do not exceed the corresponding bounding box range, thereby alleviating the layout and routing resource congestion problem caused by ultra-large-scale clocks. After the clock resources are allocated, a clock balance tree is constructed within the bounding box of each clock so that the delay of each clock from the source to each destination node is the same, which can reduce the signal synchronization problem caused by clock skew. Through this structure, the transmission time of the clock signal can be ensured to be consistent, which can effectively solve the clock skew problem in the FPGA layout and routing process, thereby optimizing the clock performance of the system. By implementing routing from the clock source to the root node of the clock balancing tree through a routing algorithm, it is possible to ensure that the route from the clock source to the clock balancing tree is the shortest, thereby minimizing the delay of the clock signal and avoiding the introduction of additional skew and delay due to an excessively long clock transmission path. The FPGA clock layout and routing method provided by the present invention, by allocating clock resources in advance, can support hundreds of clock scales under the premise of limited clock routing resources, ensuring that resource congestion will not occur in the subsequent layout and routing process. In addition, the construction of the clock balancing tree of this embodiment further reduces clock skew while meeting the complex constraints of layout and routing, enhances signal integrity, effectively reduces signal attenuation and interference during transmission, and improves overall system performance.

[0079] In the embodiments of the present application, an FPGA clock layout and routing system is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0080] The embodiment of the present application provides an FPGA clock layout and routing system. Figure 5 : This is a schematic diagram of the structure of an FPGA clock placement and routing system provided in an embodiment of the present application. The system is applied to an FPGA device, and the FPGA device includes multiple clock domains. The system includes:

[0081] A legalization module 501 is used to reduce the bounding box of clocks in the clock domain until the number of clocks in each clock domain is legal;

[0082] A clock resource allocation module 502 is configured to allocate clock resources to clocks so that the bounding boxes of clocks allocated to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes;

[0083] A balanced tree construction module 503 is used to construct a clock balanced tree within the boundary box of each clock after clock resource allocation is completed, so that the delay of each clock from the source to each destination node is the same;

[0084] The routing module 504 is configured to implement routing from the clock source to the root node of the clock balancing tree through a routing algorithm.

[0085] In an optional implementation, the legalization module 501 is specifically configured to:

[0086] Set the capacity limit in each clock domain; the capacity limit is used to represent the maximum number of clocks in each clock domain;

[0087] The bounding boxes of the clocks in each clock domain are adjusted through an iterative method so that the number of all clocks in the clock domain does not exceed the capacity limit corresponding to each clock domain.

[0088] In an optional implementation manner, the clock resource allocation module 502 is specifically configured to:

[0089] Get the distance and layout parameters between each clock in each clock domain;

[0090] A unique resource identifier is assigned to each clock according to the distance and layout parameters, so that the bounding boxes of clocks assigned to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

[0091] In an optional implementation, the balanced tree construction module 503 is specifically configured to:

[0092] Select the root node of the clock balancing tree within the bounding box of the current clock;

[0093] Starting from the root node, branch nodes are expanded hierarchically until a target node within the bounding box is reached; wherein, in a path from the root node to any target node, the number of branch nodes passed through is equal.

[0094] In an optional implementation, the routing module 504 is specifically configured to:

[0095] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and then starts visiting the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining a traversal access path.

[0096] According to the traversed access path, the target access path is obtained to realize the routing from the clock source to the root node of the clock balancing tree.

[0097] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0098] The FPGA clock placement and routing system in this embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0099] The embodiment of the present invention also provides a computer device having the above Figure 5 The following FPGA clock placement and routing system is shown.

[0100] See also Figure 6 , Figure 6 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information in the graphical user interface on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0101] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0102] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0103] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0104] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0105] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 can be connected via a bus or other means. Figure 6 The bus connection is taken as an example.

[0106] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0107] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0108] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A FPGA clock layout and routing method, characterized in that: The method is applied to an FPGA device, wherein the FPGA device includes multiple clock domains, and the method includes: Reduce the bounding box of the clocks in the clock domain until the number of clocks in each clock domain is legal; Allocate clock resources so that the bounding boxes of clocks allocated to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes; After clock resource allocation is completed, a clock balancing tree is constructed within the bounding box of each clock so that the delay from the source to each destination node is the same for each clock; The routing algorithm is used to implement the routing from the clock source to the root node of the clock balancing tree.

2. The method according to claim 1, characterized in that Shrinking the bounding boxes of the clocks in the clock domains until the number of clocks in each clock domain is legal includes: Setting capacity limits within each clock domain; the capacity limits are used to characterize the maximum number of clocks within each clock domain; The bounding boxes of the clocks in each clock domain are adjusted through an iterative method so that the number of all clocks in the clock domain does not exceed the capacity limit corresponding to each clock domain.

3. The method according to claim 2, characterized in that The allocating clock resources of the clock includes: Get the distance and layout parameters between each clock in each clock domain; A unique resource identifier is assigned to each clock according to the distance and layout parameters, so that the bounding boxes of clocks assigned to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

4. The method according to claim 3, characterized in that The step of constructing a clock balancing tree within the boundary box of each clock includes: Select the root node of the clock balancing tree within the bounding box of the current clock; Starting from the root node, branch nodes are expanded hierarchically until a target node within the bounding box is reached; wherein, in a path from the root node to any target node, the number of branch nodes passed through is equal.

5. The method according to claim 4, characterized in that The routing from the clock source to the root node of the clock balancing tree is realized by using a routing algorithm, including: Starting from the current node of the clock source, accessing the adjacent nodes of the current node through the routing algorithm, and after accessing the adjacent nodes, starting from the adjacent nodes again until accessing the root node of the clock balance tree, thereby obtaining a traversal access path; According to the traversed access path, the target access path is obtained to realize the routing from the clock source to the root node of the clock balancing tree.

6. An FPGA clock placement and routing system, characterized in that: The system is applied to an FPGA device, wherein the FPGA device includes multiple clock domains, and the system includes: The legalization module is used to reduce the bounding box of clocks in the clock domain until the number of clocks in each clock domain is legal; A clock resource allocation module is used to allocate clock resources of clocks so that the boundary boxes of clocks allocated to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding boundary boxes; The balanced tree construction module is used to build a clock balanced tree within the boundary box of each clock after clock resource allocation is completed, so that the delay of each clock from the source to each destination node is the same; The routing module is used to implement routing from the clock source to the root node of the clock balancing tree through a routing algorithm.

7. The system according to claim 6, characterized in that The legalization module is specifically used to: Setting capacity limits within each clock domain; the capacity limits are used to characterize the maximum number of clocks within each clock domain; The bounding boxes of the clocks in each clock domain are adjusted through an iterative method so that the number of all clocks in the clock domain does not exceed the capacity limit corresponding to each clock domain.

8. The system according to claim 7, characterized in that The clock resource allocation module is specifically configured to: Get the distance and layout parameters between each clock in each clock domain; A unique resource identifier is assigned to each clock according to the distance and layout parameters, so that the bounding boxes of clocks assigned to the same clock resource do not overlap and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

9. The system according to claim 8, characterized in that The balanced tree construction module is specifically used to: Select the root node of the clock balancing tree within the bounding box of the current clock; Starting from the root node, branch nodes are expanded hierarchically until a target node within the bounding box is reached; wherein, in a path from the root node to any target node, the number of branch nodes passed through is equal.

10. The system according to claim 9, characterized in that The routing module is specifically used to: Starting from the current node of the clock source, accessing the adjacent nodes of the current node through the routing algorithm, and after accessing the adjacent nodes, starting from the adjacent nodes again until accessing the root node of the clock balance tree, thereby obtaining a traversal access path; According to the traversed access path, the target access path is obtained to realize the routing from the clock source to the root node of the clock balancing tree.

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